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Change subject: drivers/i2c/rt5645: Add RT5645 amp driver
......................................................................
Patch Set 23: Code-Review+2
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/81773/comment/279638d9_5895c511 :
PS9, Line 9: Add RT5645 AMP support.
> That does not justify a separate file per se. […]
The reason is the newly added pin not support in generic I2C driver. Generic I2C driver not support gpio pin as dsd property yet.
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Change subject: acpi: Make acpi_device_write_dsd_gpio() public
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Patch Set 11: Code-Review+2
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Martin L Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81994?usp=email )
Change subject: Documentation/framework/azalea: Add mainboard documentation
......................................................................
Documentation/framework/azalea: Add mainboard documentation
It's important that people understand that this coreboot port is not
going to be a replacement for the UEFI firmware for most people. This
is an unofficial port with non-production-level code from AMD. I hope
to port from FSP to openSIL in the upcoming months, but the openSIL is
strictly proof-of-concept, getting ready for upcoming platforms.
Signed-off-by: Martin Roth <gaumless(a)gmail.com>
Change-Id: Idc6fe5e194cf17da1e48ca7be3334682c2fba166
---
A Documentation/mainboard/framework/azalea/azalea.md
A Documentation/mainboard/framework/azalea/azalea.png
M Documentation/mainboard/index.md
3 files changed, 118 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/81994/1
diff --git a/Documentation/mainboard/framework/azalea/azalea.md b/Documentation/mainboard/framework/azalea/azalea.md
new file mode 100644
index 0000000..bc340d8
--- /dev/null
+++ b/Documentation/mainboard/framework/azalea/azalea.md
@@ -0,0 +1,109 @@
+# Azalea board (Framework 13 AMD Ryzen 7040 series)
+
+## Notice
+**This firmware is not production quality**, and is being developed only as a
+proof-of-concept. AMD's FSP and openSIL firmwares for the Phoenix SoC are not
+fully featured. It is recommended that you do not replace the OEM Firmware on
+your Azalea board if you are using it as a daily-driver laptop.
+
+Most notably, suspend is not supported in this firmware. You should in theory
+still be able to use hibernate from the OS, but S3 and S0i3 are not being
+developed or tested.
+
+## Azalea Platform Specs
+- CPU
+ - AMD Ryzen 5 7640U (4.9GHz, 6-cores) or
+ - AMD Ryzen 7 7840U (5.1Ghz, 8 cores)
+- Memory
+ - 2 DDR5 SO-DIMM slots - Each accepting 32GiB DDR5-5600 SO-DIMMs
+- Storage
+ - 2280 M.2 M-Key slot - 1 NVMe M.2 SSD
+- WIFI/BT:
+ - 2230 M.2 E-Key slot
+ - Comes with AMD RZ616 Wi-Fi 6E / BT 5.2
+ - Intel modules tend not to work
+- Battery
+ - 55Wh with Ryzen 5
+ - 61Wh with Ryzen 7
+- Ports
+ - 4 expansion slots
+- Audio
+ - Realtek ALC295 Codec
+ - 3.5mm combo headphone jack
+- EC
+ - Nuvoton NPCX993
+
+## Mainboard
+![Azalea Mainboard](azalea.png)
+
+Notice that the SPI ROM here is socketed. For mass-production devices, it's
+soldered down.
+
+## Flashing coreboot
+```{eval-rst}
++---------------------+--------------------------------+
+| Type | Value |
++=====================+================================+
+| Socketed flash | no |
++---------------------+--------------------------------+
+| Vendor | GigaDevice or Winbond |
++---------------------+--------------------------------+
+| Model | 25LR256EYIG or 25Q256JWEQ |
++---------------------+--------------------------------+
+| Size | 32 MiB |
++---------------------+--------------------------------+
+| Voltage | 1.8V |
++---------------------+--------------------------------+
+| In circuit flashing | Yes, if header is populated |
++---------------------+--------------------------------+
+| Package | WSON8 |
++---------------------+--------------------------------+
+| Write protection | No |
++---------------------+--------------------------------+
+| Internal flashing | Yes |
++---------------------+--------------------------------+
+```
+
+## Update instructions
+
+### Warning
+**Before flashing, make sure you have a hardware flash tool to recover the
+system.**
+
+**This procedure can render your laptop un-bootable until the ROM chip is
+updated.**
+
+**The coreboot project assumes no liability for firmware that does not work as
+expected.**
+
+### Flashing Notes
+Before starting, please look over the
+[Flashing firmware tutorial](https://doc.coreboot.org/tutorial/flashing_firmware/index.html)
+and make a backup of *your* ROM chip to recover if anything goes wrong.
+
+The typical way to flash a chip still attached to a board is to use a test clip
+of some sort which allows you to connect an external programmer to the pins of
+the SPI ROM or pads on the mainboard. These can be found for sale in various
+places by searching for "WSON8 test clip". An SOIC8 test clip (commonly referred
+to generically as "pomona clips") may work as well.
+
+There are a number of hardware flash tools which can be used. *Make sure you
+pick a programmer that supports 1.8V flashing.* You can damage your board by
+flashing at 3.3V or 5V. Professional developers tend to use the Dediprog SF100,
+but that's a very expensive tool for someone only doing this once.
+
+## Schematics and Pinout information
+
+### Partial Mainboard Schematic
+A block diagram and partial mainboard schematic has been released by Framework
+Computer Inc under the CC By 4.0 license.
+[The schematic is available on their github site.](https://github.com/FrameworkComputer/Framework-Laptop-13/blob/main/M…
+
+### Pinouts
+- [Webcam Interface Pinout](https://github.com/FrameworkComputer/Framework-Laptop-13/tree/main/…
+- [EDP Mainboard Interface Pinout](https://github.com/FrameworkComputer/Framework-Laptop-13/tree/main/…
+- [Audio Board Interface Pinout](https://github.com/FrameworkComputer/Framework-Laptop-13/tree/main/…
+- [Speaker Interface Pinout](https://github.com/FrameworkComputer/Framework-Laptop-13/tree/main/…
+- [Battery Interface Pinout](https://github.com/FrameworkComputer/Framework-Laptop-13/tree/main/…
+- [Input Cover (Keyboard/Trackpad) Interface Pinout](https://github.com/FrameworkComputer/Framework-Laptop-13/tree/main/…
+- [Fan Interface Pinout](https://github.com/FrameworkComputer/Framework-Laptop-13/tree/main/…
diff --git a/Documentation/mainboard/framework/azalea/azalea.png b/Documentation/mainboard/framework/azalea/azalea.png
new file mode 100644
index 0000000..e728d85
--- /dev/null
+++ b/Documentation/mainboard/framework/azalea/azalea.png
Binary files differ
diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md
index 7559628..309e8bc 100644
--- a/Documentation/mainboard/index.md
+++ b/Documentation/mainboard/index.md
@@ -111,6 +111,15 @@
D41S <foxconn/d41s.md>
```
+## Framework
+
+```{toctree}
+:maxdepth: 1
+
+Azalea (Framework 13 Ryzen 7040 series) <framework/azalea/azalea.md>
+```
+
+
## Gigabyte
```{toctree}
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Change subject: util/ifdtool: Add support for checking GPR0 status
......................................................................
Patch Set 5:
(1 comment)
File util/ifdtool/ifdtool.c:
https://review.coreboot.org/c/coreboot/+/81928/comment/879418c9_169e8174 :
PS4, Line 1802: reg.data.write_protect_en
> Hi Reka, […]
Yes, that's what I meant. My point is that just because the enable bit is set, it doesn't necessarily mean protection is enabled. E.g. if the range is 0, it's not really enabled. So it depends whether you really only care about the enable bit, or about protection being correctly enabled.
Can I ask what you're planning to use this for? Is it just for developers to use locally, or are you planning to use it in some automated process / test?
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Change subject: lib/device_tree: Add some FDT helper functions
......................................................................
Patch Set 19:
(7 comments)
File src/lib/device_tree.c:
https://review.coreboot.org/c/coreboot/+/81081/comment/9ab06159_956b5431 :
PS12, Line 214: ince address-cells and size-cells are not inherited
> I mean sounds like they're acknowledging that Linux is intentionally doing something else to improve […]
Done
https://review.coreboot.org/c/coreboot/+/81081/comment/3e9bebc0_040ded3c :
PS12, Line 235: } while (be32dec(blob + offset) != FDT_TOKEN_END_NODE);
> Yeah, I think keeping the code simple is more important here. […]
Done
File src/lib/device_tree.c:
https://review.coreboot.org/c/coreboot/+/81081/comment/83f7f05f_1f213c58 :
PS18, Line 175: ""
> Okay, I see. But it sounds like we agree that that doesn't make sense anymore after fdt_find_subnodes_by_prefix() became a separate function? So let's design fdt_find_node() such that it is as equivalent as possible in what it does to dt_find_node(), I think that makes understanding the design much easier.
I agree.
Done
> Yes, that was my idea, just make it skip the fdt_next_node_name() call. Anyway, I mostly proposed this because it sounded like you were very interested in maximizing performance for this code, but I understand now that you were referring to something else with that. If you don't think a few extra strlen() here and there matter, feel free to ignore those microoptimzations, I don't care that much either way.
Done
https://review.coreboot.org/c/coreboot/+/81081/comment/8d20aa9d_08213b3d :
PS18, Line 188: size_t path_count
> I think you should match `dt_find_node()` with this API for consistency (e.g. […]
Done
https://review.coreboot.org/c/coreboot/+/81081/comment/f4146d0a_6ef31ca2 :
PS18, Line 251: #define PATH_ARRAY_MAX 10
> I think this should go at the top of the file (maybe call it FDT_PATH_MAX_DEPTH to clarify that it d […]
Done
https://review.coreboot.org/c/coreboot/+/81081/comment/049c686e_9c6f8d0a :
PS18, Line 255: 128
> This should also be a named constant (e.g. FDT_PATH_MAX_LEN).
Done
https://review.coreboot.org/c/coreboot/+/81081/comment/1d924a6f_83e73a90 :
PS18, Line 265: }
> I think this would be cleaner with `memcpy()` and `strtok_r()`: […]
Done
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Hello Jakub Czapiga, Julius Werner, Martin L Roth, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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The following approvals got outdated and were removed:
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Change subject: lib/device_tree: Add some FDT helper functions
......................................................................
lib/device_tree: Add some FDT helper functions
This adds some helper functions for FDT, since more and more mainboards
seem to need FDT nowadays. For example our QEMU boards need it in order
to know how much RAM is available. Also all RISC-V boards in our tree
need FDT.
This also adds some tests in order to test said functions.
Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com>
Change-Id: I2fb1d93c5b3e1cb2f7d9584db52bbce3767b63d8
---
M src/include/device_tree.h
M src/lib/device_tree.c
M tests/lib/Makefile.mk
A tests/lib/device_tree-test.c
A tests/lib/tegra30-ouya.dtb.xxd
A tests/lib/virt.dtb.xxd
M util/lint/lint-000-license-headers
7 files changed, 14,237 insertions(+), 47 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/81081/19
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Change subject: drivers/i2c/rt5645: Add RT5645 amp driver
......................................................................
Patch Set 23:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/81773/comment/535684a3_dc0ffa08 :
PS9, Line 9: Add RT5645 AMP support.
> 5650 and 5645 are in the same series, different from 5663.
That does not justify a separate file per se. Please don’t let me diff both files, to see what differences there are. You need to convince the reviewers.
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Change subject: mb/google/nissa/var/anraggar: Add cbj_sleeve to control mic jack
......................................................................
Patch Set 18:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/81774/comment/64199315_9015110a :
PS18, Line 7: Add cbj_sleeve to control mic jack
:
Also mention that you replace the generic driver?
https://review.coreboot.org/c/coreboot/+/81774/comment/523897c7_850cccb9 :
PS18, Line 9: Added
Add
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Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81960?usp=email )
Change subject: arch/x86: Enable long mode entry into payload for x86_64 support
......................................................................
Patch Set 1:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/81960/comment/1160f3e9_261921ef :
PS1, Line 15: transition.
Why would there be such issues? wouldn't libpayload be responsible
to switch to long mode properly? The payload (depthcharge) should be
only C code, isn't it?
File src/arch/x86/boot.c:
https://review.coreboot.org/c/coreboot/+/81960/comment/9a1d0092_595ed63d :
PS1, Line 25: if (CONFIG(PAYLOAD_X86_64_SUPPORT)) {
AIUI, the payload handover and the coreboot tables are the most important
ABI pieces of coreboot. Making this a compile-time option would mean that
the resulting coreboot is suddenly incompatible to all prior (x86) payload
builds. So, shouldn't this be decided at runtime, maybe based on information
from CBFS?
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