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Change subject: [MTL-x64]arch/x86: Update X86_64 memcpy for 4 byte copy
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS3:
> So the code that literally says
> `YES! memcpy() works. FDATAn does not require 32-bit accesses.` requires 32-bit access and you think changing memcpy to 32bit is a good idea?
>
> It's not memcpy that broke the SPI flash r/w ops. FDATA always has been a 32-bit register, but was never treated like that.
I agree with Patrick that FDATA is 32-bit register and MMIO write is the correct approach rather fixing the memcopy.
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Change subject: device_util: Handle domain device in dev_get_domain
......................................................................
Patch Set 1: Code-Review+2
(1 comment)
File src/device/device_util.c:
https://review.coreboot.org/c/coreboot/+/81957/comment/06f117c4_57ab6856 :
PS1, Line 255: dev
This also fixes a potential NULL-deref of `dev` here. Maybe worth to mention
in the commit message.
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Change subject: [MTL-x64]arch/x86: Update X86_64 memcpy for 4 byte copy
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS3:
> > > fix your code […]
So the code that literally says
`YES! memcpy() works. FDATAn does not require 32-bit accesses.` requires 32-bit access and you think changing memcpy to 32bit is a good idea?
It's not memcpy that broke the SPI flash r/w ops. FDATA always has been a 32-bit register, but was never treated like that.
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Change subject: intel/alderlake: Add helper functions for Power Management
......................................................................
Patch Set 7:
(1 comment)
File src/soc/intel/alderlake/chip.h:
https://review.coreboot.org/c/coreboot/+/81638/comment/e2692088_e220bf98 :
PS4, Line 799: };
> > The current ADL code shows that we can do better and hardcoded a default in
> coreboot. IMO, that's a good idea (I would even hardcode all UPD defaults in
> coreboot).
>
> The current code leaves devices without ASPM and friends enabled, even with the Kconfig option set. In that state, there are serious issues with devices, particularly SSDs - some won't be detected, they can drop off, and it can cause issues with payloads (yes, as expected, edk2 is the worst).
Not saying the state is good. Just the fact that the default is set in coreboot
sources. That's a good design. I assume it's undocumented what `auto` means,
so that would indeed not be a good default.
>
> Maybe it is just a question of what the default value is, but IMO, it's not better -the "default" should be the most compatible - which is going to be the default in FSP.
Do you mean ASPM? Your code comments and those in FSP headers say the FSP default
is `auto`, too? FWIW, the most compatible is always to turn it off.
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Change subject: acpi: Make acpi_device_write_dsd_gpio() public
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Patch Set 11: Code-Review+2
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Change subject: [MTL-x64]arch/x86: Update X86_64 memcpy for 4 byte copy
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS3:
> > fix your code
>
> For reference, that would be the MRC cache code mentioned in the commit message.
for details:
https://github.com/coreboot/coreboot/blame/main/src/soc/intel/common/block/…
we can always modify that code to do a write32p
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Change subject: [MTL-x64]arch/x86: Update X86_64 memcpy for 4 byte copy
......................................................................
Patch Set 3:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/81959/comment/e9c2d812_384ca8b8 :
PS3, Line 7: [MTL-x64]
> can u remove this ?
Acknowledged
Patchset:
PS3:
> > fix your code […]
We've validated this change required based on Mrc Cache Read/Write. This is not related to Mrc Cache, but rather spi flash r/w. Changing memcpy to 8 bytes, broke the spi flash r/w ops for old/new platforms. The spi flash driver is using memcpy since early 2017 and we've not changed anything recently.
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Change subject: soc/intel/xeon_sp: Add soc_add_dram_resources
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Patch Set 1: Code-Review+2
(1 comment)
File src/soc/intel/xeon_sp/uncore.c:
https://review.coreboot.org/c/coreboot/+/81958/comment/871c2af7_d4b1b868 :
PS1, Line 274: index += soc_add_dram_resources(dev, mc_values, index);
I expect that the order in which resources are reported shouldn't matter much.
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