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Change subject: arch/x86: Enable long mode entry into payload for x86_64 support
......................................................................
Patch Set 7:
(1 comment)
File src/arch/x86/boot.c:
https://review.coreboot.org/c/coreboot/+/81960/comment/653d352a_ce4ce8c7 :
PS3, Line 47: is_payload_64_bit_enabled
> yes. Either that or use long_mode_call_3arg() to switch to long mode before calling the payload. I haven't tested that but should work fine.
I have tried following ur review comment and after some experiement I have concluded that supporting 64-bit payload with 32-bit coreboot is not pratical to launch because the `long_mode_call_3arg` and associated pagetable codes are only getting compiled when CONFIG_ARCH_BOOTBLOCK_X86_32 Kconfig remains enabled. Even I tried to W/A that but eventually started running into issue due to relocation type which seems to be different between 32-bit coreboot code is tring to compile 64-bit entrypoint for payload. Rather for now, I have added `die` to forbid such entry.
src/cpu/x86/64bit/pt.S:23: Error: cannot represent relocation type BFD_RELOC_64
/opt/coreboot-sdk/lib/gcc/i386-elf/11.3.0/../../../../i386-elf/bin/as: /build/rex/tmp/portage/sys-boot/coreboot-9999/work/build/rex0-serial/romstage/cpu/x86/64bit/pt.o: unsupported relocation type: 0x1
I don't believe below one is the correct approach to skip the compilation issue with 32-bit coreboot
```
diff --git a/src/cpu/x86/64bit/pt.S b/src/cpu/x86/64bit/pt.S
index 67e4b1b8bf6..a9e763f86aa 100644
--- a/src/cpu/x86/64bit/pt.S
+++ b/src/cpu/x86/64bit/pt.S
@@ -20,16 +20,28 @@
.global PM4LE
.align 4096
PM4LE:
+#if CONFIG(ARCH_BOOTBLOCK_X86_64)
.quad _GEN_DIR(PDPE_table)
+#else
+.long _GEN_DIR(PDPE_table)
+#endif
```
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Hello Arthur Heymans, Julius Werner, Jérémy Compostella, Kapil Porwal, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Verified+1 by build bot (Jenkins)
Change subject: arch/x86: Enable long mode entry into payload for x86_64 support
......................................................................
arch/x86: Enable long mode entry into payload for x86_64 support
This patch allows coreboot to enter libpayload in long mode (64-bit)
instead of protected mode (32-bit), enabling support for upcoming Intel
platforms and payloads requiring access to memory beyond 4GB.
This change ensures compatibility between libpayload and depthcharge,
preventing compilation issues and stack misalignment during the
transition.
Note: 32-bit coreboot and 64-bit payload is unsupported configuration
at this moment.
BUG=b:242829490
TEST=Entered libpayload in long mode, successfully parsed coreboot
table.
Change-Id: Ic5e6f0af11c05e8b075b8c20880c012747a1df9b
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
---
M src/arch/x86/boot.c
1 file changed, 58 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/81960/8
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Change subject: mb/dell/optiplex_9020: Implement late HWM initialization
......................................................................
Patch Set 8:
(1 comment)
Patchset:
PS8:
> DO NOT MERGE THIS YET. HERE's WHY: […]
Set it to unresolved if you want this to be a blocker. (Doing it now)
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Change subject: mb/dell/optiplex_9020: Implement late HWM initialization
......................................................................
Patch Set 8:
(1 comment)
Patchset:
PS8:
DO NOT MERGE THIS YET. HERE's WHY:
hi, this works perfectly on SFF but bricks the 9020 MT. symptom: backlight turns on, but then i see nothing. no text, no image, seemingly i can't get to the payload at all. the system hangs. will get a log in a little while.
putting this here as a matter of urgency. i urge NOT to merge this patch yet, until MT is fixed.
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Change subject: drivers/i2c/rt5645: Add RT5645 amp driver
......................................................................
Patch Set 23:
(1 comment)
File src/drivers/i2c/rt5645/rt5645.c:
https://review.coreboot.org/c/coreboot/+/81773/comment/33e612af_67d0ce95 :
PS23, Line 93: static char name[5];
> This is ACPI device name which can be 4 chars at max.
you're right, I was mixing up the ACPI device name and the HID
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Change subject: drivers/pc80/tpm: Disable device if TPM not present
......................................................................
Patch Set 3:
(1 comment)
File src/drivers/pc80/tpm/tis.c:
https://review.coreboot.org/c/coreboot/+/80455/comment/d8c18f3e_daf7bc2f :
PS3, Line 911: &family
`NULL` can be used instead.
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Change subject: drivers/crb: Disable device if CRB TPM not present
......................................................................
Patch Set 2:
(1 comment)
File src/drivers/crb/tis.c:
https://review.coreboot.org/c/coreboot/+/80454/comment/d6d43fea_f05c3969 :
PS2, Line 212: &family
You can use `NULL` now.
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Change subject: mb/aoostar: Add AOOSTAR R1 (WTR_R1)
......................................................................
Patch Set 2:
(10 comments)
Patchset:
PS2:
Hi, and thanks for contributing!
File src/mainboard/aoostar/wtr_r1/bootblock.c:
https://review.coreboot.org/c/coreboot/+/82010/comment/64fccfa9_781c42e0 :
PS2, Line 1:
Remove blank line
File src/mainboard/aoostar/wtr_r1/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/82010/comment/cab6dc78_e7a1ccaa :
PS2, Line 16: register "usb2_ports[0]" = "USB2_PORT_MID(OC3)" # Type-C Port1
: register "usb2_ports[1]" = "USB2_PORT_MID(OC3)" # Type-C Port2
: register "usb2_ports[2]" = "USB2_PORT_MID(OC3)" # FPS connector
: register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN
: register "usb2_ports[4]" = "USB2_PORT_MID(OC3)" # USB3/2 Type A port1
: register "usb2_ports[5]" = "USB2_PORT_MID(OC1)" # USB3/2 Type A port2
: register "usb2_ports[6]" = "USB2_PORT_MID(OC1)" # USB3/2 Type A port3
: register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Type A/ M.2 WLAN
: register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
:
: register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC3)" # USB3/2 Type A port1
: register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # USB3/2 Type A port2
: register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # USB3/2 Type A port3
: r
Please move into the devicetree below.
https://review.coreboot.org/c/coreboot/+/82010/comment/f0e8b80d_e1026757 :
PS2, Line 81: device ref ipu off end
Already disabled in chipset devicetree, remove.
https://review.coreboot.org/c/coreboot/+/82010/comment/bb4b3539_bbd67f78 :
PS2, Line 117: device ref heci1 on end
Enabled in chipset devicetree, remove.
https://review.coreboot.org/c/coreboot/+/82010/comment/e267df02_7847be35 :
PS2, Line 230: device ref p2sb on end
P2SB is hidden by the FSP, which is configured accordingly in chipset devicetree. Remove.
https://review.coreboot.org/c/coreboot/+/82010/comment/ff7ec4cf_c2215fa1 :
PS2, Line 231: device ref emmc off end
Already disabled in chipset devicetree, remove.
https://review.coreboot.org/c/coreboot/+/82010/comment/66fa3c7a_8e8f5919 :
PS2, Line 233: device ref ufs off end
Already disabled in chipset devicetree, remove.
File src/mainboard/aoostar/wtr_r1/gpio.h:
PS2:
Remove comments to GPIOs which are configured with PAD_NC.
https://review.coreboot.org/c/coreboot/+/82010/comment/ed74f689_e3133600 :
PS2, Line 222: /* ------- GPIO Group PCIe vGPIO ------- */
Remove the superfluous comments below.
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Change subject: mb/aoostar: Add AOOSTAR R1 (WTR_R1)
......................................................................
mb/aoostar: Add AOOSTAR R1 (WTR_R1)
AOOSTAR R1 is a Chinese NAS based on Intel N100 (Alder Lake N), with two 3.5" HDD slots, an M.2 NVMe 2280 SSD slot and a single DDR4 SODIMM slot.
It also comes with 2x 2.5Gb Intel NICs, Intel AX200 WiFi + BT and USB-C Alt-DP Power Delivery.
Working:
- Automatic FAN control (IT8613E SuperIO)
- M.2 NVME slot
- 2x SATA ports
- 2.0 USB ports
- USB-C port with Alt-DP and PD
- HDMI / DisplayPort ports
- 2x 2.5Gb NICs
- WiFi + BT
- ASPM (Unavailable on stock)
- Linux/Windows UEFI booting with EDK2
Broken:
- Power button (OFF->ON broken, ON->OFF works)
- USB 3.0 ports
Untested:
- Internal audio
- MicroSD card reader
- S3
My motivation for doing this port is enabling ASPM, as it makes a great difference on idle power consumption (from 8.4W to 5W measured from the wall).
The last remaining annoyance of this port is the power button not working. I spent a few hours double checking the SuperIO registers but then I gave up.
A workaround for this is to use the "ON after power loss" feature and reconnect the power cord to turn on the board. It's not a big problem for a NAS that will stay ON 24/7.
Compiled with IFD descriptor, ME blob and vgabios blob (ID 8086,0406) extracted from vendor BIOS.
The board can be flashed externally using a 1.8V adapter, I used a CH341a modded for 3.3V I/O.
Internal flashing could work too as SPI flash is not read/write protected, but I haven't tried.
Change-Id: I9414eb742b6b90459e010b038c1994537e9801a5
Signed-off-by: Federico Amedeo Izzo <federico(a)izzo.pro>
---
A src/mainboard/aoostar/Kconfig
A src/mainboard/aoostar/Kconfig.name
A src/mainboard/aoostar/wtr_r1/Kconfig
A src/mainboard/aoostar/wtr_r1/Kconfig.name
A src/mainboard/aoostar/wtr_r1/Makefile.mk
A src/mainboard/aoostar/wtr_r1/board_info.txt
A src/mainboard/aoostar/wtr_r1/bootblock.c
A src/mainboard/aoostar/wtr_r1/data.vbt
A src/mainboard/aoostar/wtr_r1/devicetree.cb
A src/mainboard/aoostar/wtr_r1/dsdt.asl
A src/mainboard/aoostar/wtr_r1/gpio.h
A src/mainboard/aoostar/wtr_r1/romstage_fsp_params.c
12 files changed, 970 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/82010/2
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