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Change subject: soc/intel/xeon_sp: Add _OSC ASL generation utils for IIO stacks
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
Hi all,
I tentatively raise a new patch train (topic: _OSC) to cover the _OSC implementation topic for Xeon-SP. In this CR, as an alternative of CL81652, static OSC handler (\_SB.OSCP) is implemented for better readability and maintenance. CL 81377 provides an example for how to use the new mechanism and managed to test in archercity CRB. Let us discuss and look forward to your good inputs.
Some related points:
1. The new _OSC proves to work with OS, as below,
[ 5.217993] ACPI: PCI Root Bridge [HQ18] (domain 0000 [bus ea-eb])
[ 5.217995] acpi PNP0A08:1b: _OSC: OS supports [ExtendedConfig ASPM ClockPM Segments MSI EDR HPX-Type3]
[ 5.218027] acpi PNP0A08:1b: _OSC: platform does not support [SHPCHotplug AER LTR DPC]
[ 5.218086] acpi PNP0A08:1b: _OSC: OS now controls [PCIeHotplug PME PCIeCapability]
However, when using iasl -d, the decoded form looks not so straightforward,
Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities
{
Return (\_SB.POSC) /* External reference */
Arg0
Arg1
Arg2
Arg3
0x15
Zero
One
}
I hope it could be decoded as,
Return (\_SB.POSC(Arg0, Arg1, ...)).
Not sure if something needs to be improved, or it is due to the iasl tool itself.
2. I'm thinking to put POSC to a sub scope of \_SB, but didn't find a proper _HID for it. IMO, putting POSC into a sub scope of \_SB instead of directly under \_SB might be helpful to reduce the name conflicts for other methods under \_SB. But not sure whether this is worthwhile.
3. The whole patch train still have a couple of CLs in WIP state due to clang build errors. Hence this is just for early discussion.
Thanks
Shuo Liu
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Change subject: mb/google/nissa/var/anraggar: Add cbj_sleeve to control mic jack
......................................................................
Patch Set 20:
(1 comment)
File src/mainboard/google/brya/Kconfig:
https://review.coreboot.org/c/coreboot/+/81774/comment/7429ecb0_f6578653 :
PS19, Line 10: select DRIVERS_I2C_RT5645
> woops, yes.
Sorry for my mistake.
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Change subject: drivers/i2c/rt5645: Add RT5645 amp driver
......................................................................
Patch Set 24:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/81773/comment/8083c18d_62a1c245 :
PS9, Line 9: Add RT5645 AMP support.
> Thank you for giving some background. I think, upstream has the policy of reducing duplicate code. […]
Done
File src/drivers/i2c/rt5645/rt5645.c:
https://review.coreboot.org/c/coreboot/+/81773/comment/13a72710_7da3a527 :
PS23, Line 42: 10EC5650
> > agreed, this should only be the fallback if not specified in the chip definition […]
Done
https://review.coreboot.org/c/coreboot/+/81773/comment/3f23d098_e90350bc :
PS23, Line 46: acpigen_write_STA(acpi_device_status(dev));
> > we might want to set this to hidden if present, since there won't be a Windows driver for this ACP […]
Is it correct to change it to `ACPI_STATUS_DEVICE_HIDDEN_ON`?
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Change subject: mb/google/nissa/var/anraggar: Add cbj_sleeve to control mic jack
......................................................................
mb/google/nissa/var/anraggar: Add cbj_sleeve to control mic jack
Add a new GPIO port cbj-sleeve for kernel driver to call. At the same
time, a new rt5645 driver is added to replace the generic driver to
parse gpio. After entering the system, it is pulled high by the kernel
to enable the MIC function.
BUG=None
TEST=MIC function is normal
Change-Id: I093be6a3e357aae389fcbe8291a9701c40b62e15
Signed-off-by: Jianeng Ceng <cengjianeng(a)huaqin.corp-partner.google.com>
---
M src/mainboard/google/brya/Kconfig
M src/mainboard/google/brya/variants/anraggar/overridetree.cb
2 files changed, 4 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/81774/20
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Change subject: drivers/i2c/rt5645: Add RT5645 amp driver
......................................................................
drivers/i2c/rt5645: Add RT5645 amp driver
In order to be different from rt5663, the driver of RT5645 is
specially declared.
Add RT5645 AMP support. The kernel driver of 5650 is written
in rt5645.c. Add acpi name cbj-sleeve-gpios for power gate GPIO.
ALC5650 DataSheet Rev 0.93
Realtek upstream link:
https://lore.kernel.org/all/20240404035747.118064-1-derek.fang@realtek.com/
BUG=None
TEST=verified in anraggar and probe device rt5650 succeed
```
\_SB.PCI0.I2C3.RT58: Realtek RT5650
```
Change-Id: I602fcc4dd8576043943f6e20884edc4703350320
Signed-off-by: Jianeng Ceng <cengjianeng(a)huaqin.corp-partner.google.com>
---
A src/drivers/i2c/rt5645/Kconfig
A src/drivers/i2c/rt5645/Makefile.mk
A src/drivers/i2c/rt5645/chip.h
A src/drivers/i2c/rt5645/rt5645.c
4 files changed, 143 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/81773/24
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Change subject: mb/google/nissa/var/anraggar: Add cbj_sleeve to control mic jack
......................................................................
Patch Set 19: -Code-Review
(1 comment)
File src/mainboard/google/brya/Kconfig:
https://review.coreboot.org/c/coreboot/+/81774/comment/d565bbfd_12ed2157 :
PS19, Line 10: select DRIVERS_I2C_RT5645
> please follow alphabetic order, should be after `DRIVERS_I2C_NAU8825`
woops, yes.
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Change subject: libpayload: Add x86_64 (64-bit) support
......................................................................
Patch Set 19:
(1 comment)
File payloads/libpayload/arch/x86/multiboot.c:
https://review.coreboot.org/c/coreboot/+/81968/comment/b7856c42_294b4558 :
PS19, Line 123: loader_ebx
Use rsi in case of x86_64.
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