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Change subject: soc/intel/xeon_sp: Set domain0's ACPI name as PCI0
......................................................................
Patch Set 2:
This change is ready for review.
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Change subject: soc/intel/xeon_sp/acpi: Refactor Xeon-SP ASL file location
......................................................................
soc/intel/xeon_sp/acpi: Refactor Xeon-SP ASL file location
soc/intel/xeon_sp/acpi/*.asl are actually used only by SKX and CPX
platforms and not forward compatible to later SoC generations.
Move them to soc/intel/xeon_sp/acpi/gen1/ for clean maintenance.
TEST=Build and boot on intel/archercity CRB
Change-Id: Ib060b123ab0fd761f00d9a0573e9b73d600ea9ef
Signed-off-by: Shuo Liu <shuo.liu(a)intel.com>
---
M src/mainboard/intel/cedarisland_crb/dsdt.asl
M src/mainboard/ocp/deltalake/dsdt.asl
M src/mainboard/ocp/tiogapass/dsdt.asl
R src/soc/intel/xeon_sp/acpi/gen1/gpio.asl
R src/soc/intel/xeon_sp/acpi/gen1/iiostack.asl
R src/soc/intel/xeon_sp/acpi/gen1/pch.asl
R src/soc/intel/xeon_sp/acpi/gen1/pch_irq.asl
R src/soc/intel/xeon_sp/acpi/gen1/pci_irqs.asl
R src/soc/intel/xeon_sp/acpi/gen1/southcluster.asl
R src/soc/intel/xeon_sp/acpi/gen1/uncore.asl
R src/soc/intel/xeon_sp/acpi/gen1/uncore_irq.asl
11 files changed, 6 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/82033/1
diff --git a/src/mainboard/intel/cedarisland_crb/dsdt.asl b/src/mainboard/intel/cedarisland_crb/dsdt.asl
index 3d83217..59ce66c 100644
--- a/src/mainboard/intel/cedarisland_crb/dsdt.asl
+++ b/src/mainboard/intel/cedarisland_crb/dsdt.asl
@@ -22,7 +22,7 @@
{
Device (PCI0)
{
- #include <soc/intel/xeon_sp/acpi/southcluster.asl>
+ #include <soc/intel/xeon_sp/acpi/gen1/southcluster.asl>
#include <soc/intel/common/block/acpi/acpi/lpc.asl>
}
diff --git a/src/mainboard/ocp/deltalake/dsdt.asl b/src/mainboard/ocp/deltalake/dsdt.asl
index c1e8bee..8442319 100644
--- a/src/mainboard/ocp/deltalake/dsdt.asl
+++ b/src/mainboard/ocp/deltalake/dsdt.asl
@@ -20,11 +20,11 @@
#include <cpu/intel/common/acpi/cpu.asl>
// CPX-SP ACPI tables
- #include <soc/intel/xeon_sp/acpi/uncore.asl>
+ #include <soc/intel/xeon_sp/acpi/gen1/uncore.asl>
// LPC related entries
Scope (\_SB.PC00)
{
- #include <soc/intel/xeon_sp/acpi/pch.asl>
+ #include <soc/intel/xeon_sp/acpi/gen1/pch.asl>
}
}
diff --git a/src/mainboard/ocp/tiogapass/dsdt.asl b/src/mainboard/ocp/tiogapass/dsdt.asl
index 06145c4..49f20f1 100644
--- a/src/mainboard/ocp/tiogapass/dsdt.asl
+++ b/src/mainboard/ocp/tiogapass/dsdt.asl
@@ -15,9 +15,9 @@
#include "acpi/platform.asl"
#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
#include <cpu/intel/common/acpi/cpu.asl>
- #include <soc/intel/xeon_sp/acpi/uncore.asl>
+ #include <soc/intel/xeon_sp/acpi/gen1/uncore.asl>
Scope (\_SB.PC00)
{
- #include <soc/intel/xeon_sp/acpi/pch.asl>
+ #include <soc/intel/xeon_sp/acpi/gen1/pch.asl>
}
}
diff --git a/src/soc/intel/xeon_sp/acpi/gpio.asl b/src/soc/intel/xeon_sp/acpi/gen1/gpio.asl
similarity index 100%
rename from src/soc/intel/xeon_sp/acpi/gpio.asl
rename to src/soc/intel/xeon_sp/acpi/gen1/gpio.asl
diff --git a/src/soc/intel/xeon_sp/acpi/iiostack.asl b/src/soc/intel/xeon_sp/acpi/gen1/iiostack.asl
similarity index 100%
rename from src/soc/intel/xeon_sp/acpi/iiostack.asl
rename to src/soc/intel/xeon_sp/acpi/gen1/iiostack.asl
diff --git a/src/soc/intel/xeon_sp/acpi/pch.asl b/src/soc/intel/xeon_sp/acpi/gen1/pch.asl
similarity index 81%
rename from src/soc/intel/xeon_sp/acpi/pch.asl
rename to src/soc/intel/xeon_sp/acpi/gen1/pch.asl
index fef68b0..93d468a 100644
--- a/src/soc/intel/xeon_sp/acpi/pch.asl
+++ b/src/soc/intel/xeon_sp/acpi/gen1/pch.asl
@@ -3,7 +3,7 @@
/* This file should be included in the proper platform ACPI \_SB PCI scope */
/* GPIO */
-#include <soc/intel/xeon_sp/acpi/gpio.asl>
+#include <soc/intel/xeon_sp/acpi/gen1/gpio.asl>
/* LPC 0:1f.0 */
#include <soc/intel/common/block/acpi/acpi/lpc.asl>
diff --git a/src/soc/intel/xeon_sp/acpi/pch_irq.asl b/src/soc/intel/xeon_sp/acpi/gen1/pch_irq.asl
similarity index 100%
rename from src/soc/intel/xeon_sp/acpi/pch_irq.asl
rename to src/soc/intel/xeon_sp/acpi/gen1/pch_irq.asl
diff --git a/src/soc/intel/xeon_sp/acpi/pci_irqs.asl b/src/soc/intel/xeon_sp/acpi/gen1/pci_irqs.asl
similarity index 100%
rename from src/soc/intel/xeon_sp/acpi/pci_irqs.asl
rename to src/soc/intel/xeon_sp/acpi/gen1/pci_irqs.asl
diff --git a/src/soc/intel/xeon_sp/acpi/southcluster.asl b/src/soc/intel/xeon_sp/acpi/gen1/southcluster.asl
similarity index 100%
rename from src/soc/intel/xeon_sp/acpi/southcluster.asl
rename to src/soc/intel/xeon_sp/acpi/gen1/southcluster.asl
diff --git a/src/soc/intel/xeon_sp/acpi/uncore.asl b/src/soc/intel/xeon_sp/acpi/gen1/uncore.asl
similarity index 100%
rename from src/soc/intel/xeon_sp/acpi/uncore.asl
rename to src/soc/intel/xeon_sp/acpi/gen1/uncore.asl
diff --git a/src/soc/intel/xeon_sp/acpi/uncore_irq.asl b/src/soc/intel/xeon_sp/acpi/gen1/uncore_irq.asl
similarity index 100%
rename from src/soc/intel/xeon_sp/acpi/uncore_irq.asl
rename to src/soc/intel/xeon_sp/acpi/gen1/uncore_irq.asl
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Hello Arthur Heymans, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Tim Chu, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Verified+1 by build bot (Jenkins)
Change subject: soc/intel/xeon_sp/spr: Support dynamic domain SSDT generation
......................................................................
soc/intel/xeon_sp/spr: Support dynamic domain SSDT generation
Domain SSDT is dynamically generated by soc_pci_domain_fill_ssdt.
SPR has 2 SKUs, XCC and MCC. Dynamic domain SSDT generation could
better fit both. One possible side-effect might be the extra
performance cost for generating these tables, which should not bring
big impact on high performance server CPUs.
TEST=Build and boot intel/archercity CRB
Linux ACPI host bridge parsing logs are kept the same before and
after, with below issue fixed.
[ 5.124087] ACPI BIOS Error (bug): Could not resolve symbol
[\_SB.PC16], AE_NOT_FOUND (20221020/dswload2-162)
[ 5.124087] ACPI Error: AE_NOT_FOUND, During name lookup/catalog
(20221020/psobject-220)
[ 5.124087] ACPI: Skipping parse of AML opcode: OpcodeName
unavailable (0x0010)
Change-Id: Icc5843feadc840d87c49b2aa4259716264520dba
Signed-off-by: Shuo Liu <shuo.liu(a)intel.com>
---
M src/soc/intel/xeon_sp/acpi.c
M src/soc/intel/xeon_sp/chip_gen1.c
M src/soc/intel/xeon_sp/include/soc/acpi.h
D src/soc/intel/xeon_sp/spr/acpi/cxl_resource.asl
D src/soc/intel/xeon_sp/spr/acpi/dino_resource.asl
D src/soc/intel/xeon_sp/spr/acpi/iiostack.asl
D src/soc/intel/xeon_sp/spr/acpi/pci_resource.asl
D src/soc/intel/xeon_sp/spr/acpi/ubox_resource.asl
M src/soc/intel/xeon_sp/spr/acpi/uncore.asl
M src/soc/intel/xeon_sp/spr/ioat.c
M src/soc/intel/xeon_sp/spr/soc_acpi.c
11 files changed, 107 insertions(+), 327 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/81377/22
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Change subject: soc/intel/xeon_sp: Add soc_add_dram_resources
......................................................................
Patch Set 4:
(1 comment)
Patchset:
PS1:
> Please do not submit before the new implementation is under review. […]
@Nico, @Angel,
soc_add_dram_resources for gen6 is at
https://review.coreboot.org/c/coreboot/+/81316/49/src/soc/intel/xeon_sp/chi…, which is at not-implemented status at the moment. However IMO, I think soc_add_dram_resources should be already in a clear state as an API after rounds of reviews now. I'm open for further discussions if any.
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Change subject: soc/intel/xeon_sp: Add soc_add_dram_resources
......................................................................
Patch Set 4:
(2 comments)
File src/soc/intel/xeon_sp/chip_gen1.c:
https://review.coreboot.org/c/coreboot/+/81958/comment/7169d7d3_f56eafea :
PS1, Line 234: * @param mc_values List of system memory map variables.
> e.g. When SoC codes is adding >4G resources, it might check some conflicts with MMCFG_BASE/LIMIT, e. […]
Done
File src/soc/intel/xeon_sp/uncore.c:
https://review.coreboot.org/c/coreboot/+/81958/comment/03416173_0b3018d0 :
PS1, Line 306: } else {
> Hi Nico and all, I tentatively uploaded a new version to reflect some changes mentioned and move ahe […]
Done
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Hello Angel Pons, Arthur Heymans, Chen, Gang C, Christian Walter, David Hendricks, Jincheng Li, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, TangYiwei, Tim Chu, build bot (Jenkins),
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Change subject: soc/intel/xeon_sp: Add Granite Rapids initial codes
......................................................................
soc/intel/xeon_sp: Add Granite Rapids initial codes
coreboot GNR (Granite Rapids) is a FSP 2.4 based, no-PCH, single
IO-APIC Xeon-SP platform. The same set of codes is also used
for SRF (Sierra Forest) SoC.
This patch initially sets the code set up.
1. All register definitions are forked from SPR (Sapphire Rapids)
and EBG (Emmisburg PCH)'s codes are reused.
2. src/soc/intel/xeon_sp/chip_gen6.c is newly added as chip
common codes for 6th Gen Xeon-SP SoC (Granite Rapids) and later.
TEST=Build and boot on intel/archercity CRB
Change-Id: I3084e1b5abf25d8d9504bebeaed2a15b916ed56b
Signed-off-by: Shuo Liu <shuo.liu(a)intel.com>
Signed-off-by: Gang Chen <gang.c.chen(a)intel.com>
Signed-off-by: Jincheng Li <jincheng.li(a)intel.com>
---
M MAINTAINERS
M src/soc/intel/xeon_sp/Makefile.mk
A src/soc/intel/xeon_sp/chip_gen6.c
A src/soc/intel/xeon_sp/gnr/Kconfig
A src/soc/intel/xeon_sp/gnr/Makefile.inc
A src/soc/intel/xeon_sp/gnr/acpi/gpe.asl
A src/soc/intel/xeon_sp/gnr/chip.c
A src/soc/intel/xeon_sp/gnr/chip.h
A src/soc/intel/xeon_sp/gnr/chipset.cb
A src/soc/intel/xeon_sp/gnr/cpu.c
A src/soc/intel/xeon_sp/gnr/include/soc/cpu.h
A src/soc/intel/xeon_sp/gnr/include/soc/pci_devs.h
A src/soc/intel/xeon_sp/gnr/include/soc/soc_msr.h
A src/soc/intel/xeon_sp/gnr/include/soc/soc_util.h
A src/soc/intel/xeon_sp/gnr/include/soc/vpd.h
A src/soc/intel/xeon_sp/gnr/ramstage.c
A src/soc/intel/xeon_sp/gnr/romstage.c
A src/soc/intel/xeon_sp/gnr/soc_acpi.c
A src/soc/intel/xeon_sp/gnr/soc_util.c
M src/soc/intel/xeon_sp/include/soc/acpi.h
M src/soc/intel/xeon_sp/include/soc/fsp_upd.h
M src/soc/intel/xeon_sp/lockdown.c
M src/soc/intel/xeon_sp/spr/soc_acpi.c
23 files changed, 1,185 insertions(+), 20 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/81316/49
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Hello Angel Pons, Arthur Heymans, Christian Walter, Felix Held, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Nico Huber, Patrick Rudolph, Tim Chu, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: soc/intel/xeon_sp: Add soc_add_dram_resources
......................................................................
soc/intel/xeon_sp: Add soc_add_dram_resources
SoC specific DRAM resource, e.g. 4GB above DRAM memory map, CXL,
et al, are different across SoC generations. This patch separates
the codes so that different SoC generations could have different
implementations.
TEST=Build and boot on intel/archercity CRB
Change-Id: Ie15b11e1f4cdc861324286b1397f9c5e431b74ab
Signed-off-by: Shuo Liu <shuo.liu(a)intel.com>
---
M src/soc/intel/xeon_sp/chip_gen1.c
M src/soc/intel/xeon_sp/include/soc/chip_common.h
M src/soc/intel/xeon_sp/uncore.c
3 files changed, 69 insertions(+), 44 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/81958/4
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