coreboot-gerrit March 2024

coreboot-gerrit@coreboot.org

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[M] Change in coreboot[main]: arch/riscv: Basic illegal instruction handling
by Paul Menzel (Code Review) 26 Mar '24

26 Mar '24

Attention is currently required from: Philipp Hug, ron minnich. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81306?usp=email ) Change subject: arch/riscv: Basic illegal instruction handling ...................................................................... Patch Set 11: (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/81306/comment/ba4cd7d3_2e487087 : PS11, Line 7: arch/riscv: Basic illegal instruction handling Just a … [View More]

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[XL] Change in coreboot[main]: soc/intel/xeon_sp: Add GraniteRapids initial codes
by Paul Menzel (Code Review) 26 Mar '24

26 Mar '24

Attention is currently required from: Arthur Heymans, Chen, Gang C, Christian Walter, David Hendricks, Jincheng Li, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Nico Huber, Patrick Rudolph, Shuo Liu, TangYiwei, Tim Chu. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81316?usp=email ) Change subject: soc/intel/xeon_sp: Add GraniteRapids initial codes ...................................................................... Patch Set 26: (2 comments) … [View More]File src/soc/intel/xeon_sp/chip_gen6.c: PS26: Please describe this file and generations in the commit message. https://review.coreboot.org/c/coreboot/+/81316/comment/0057c042_6de268f3 : PS26, Line 80: .read_resources = iio_pci_domain_read_resources, : .set_resources = pci_domain_set_resources, : .scan_bus = pci_host_bridge_scan_bus, : #if CONFIG(HAVE_ACPI_TABLES) : .acpi_name = soc_acpi_name, : .write_acpi_tables = northbridge_write_acpi_tables, : .acpi_fill_ssdt = pci_domain_fill_ssdt, Please format the = consistently. (I’d prefer just one space.) -- To view, visit https://review.coreboot.org/c/coreboot/+/81316?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3084e1b5abf25d8d9504bebeaed2a15b916ed56b Gerrit-Change-Number: 81316 Gerrit-PatchSet: 26 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: TangYiwei Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Tue, 26 Mar 2024 16:05:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment [View Less]

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[XL] Change in coreboot[main]: soc/intel/xeon_sp: Add GraniteRapids initial codes
by Paul Menzel (Code Review) 26 Mar '24

26 Mar '24

Attention is currently required from: Arthur Heymans, Chen, Gang C, Christian Walter, David Hendricks, Jincheng Li, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Nico Huber, Patrick Rudolph, Shuo Liu, TangYiwei, Tim Chu. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81316?usp=email ) Change subject: soc/intel/xeon_sp: Add GraniteRapids initial codes ...................................................................... Patch Set 26: (7 comments) … [View More]Commit Message: https://review.coreboot.org/c/coreboot/+/81316/comment/705e8d9f_d844c99e : PS26, Line 7: GraniteRapids Granite Rapids https://review.coreboot.org/c/coreboot/+/81316/comment/94b3b596_5696d592 : PS26, Line 9: GraniteRapids Granite Rapids https://review.coreboot.org/c/coreboot/+/81316/comment/8b0e70ee_f5e56f0b : PS26, Line 9: FSP2.4 FSP 2.4 https://review.coreboot.org/c/coreboot/+/81316/comment/49b9cc15_6b39264b : PS26, Line 11: SierraForest Sierra Forest https://review.coreboot.org/c/coreboot/+/81316/comment/984e77a0_ce8268ec : PS26, Line 13: setups the code set sets the code set up. https://review.coreboot.org/c/coreboot/+/81316/comment/87afb10f_c3c66114 : PS26, Line 14: SapphireRapids Sapphire Rapids Patchset: PS26: Please add an entry to MAINTAINERS. -- To view, visit https://review.coreboot.org/c/coreboot/+/81316?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3084e1b5abf25d8d9504bebeaed2a15b916ed56b Gerrit-Change-Number: 81316 Gerrit-PatchSet: 26 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: TangYiwei Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Tue, 26 Mar 2024 16:03:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment [View Less]

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[XS] Change in coreboot[main]: arch/x86/include/arch: Add feature check macros
by Paul Menzel (Code Review) 26 Mar '24

26 Mar '24

Attention is currently required from: Arthur Heymans, Jincheng Li, Shuo Liu. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81133?usp=email ) Change subject: arch/x86/include/arch: Add feature check macros ...................................................................... Patch Set 7: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/81133/comment/01723e5e_104b5ce9 : PS7, Line 7: Add feature check macros Maybe: Define … [View More]

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[L] Change in coreboot[main]: mainboard/intel: Add Beechnut City CRB initial support
by Paul Menzel (Code Review) 26 Mar '24

26 Mar '24

Attention is currently required from: Arthur Heymans, Chen, Gang C, David Hendricks, Jincheng Li, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Shuo Liu, TangYiwei. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81322?usp=email ) Change subject: mainboard/intel: Add Beechnut City CRB initial support ...................................................................... Patch Set 5: (2 comments) Commit Message: https://review.coreboot.org/c/… [View More]

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[XS] Change in coreboot[main]: lib/spd_bin: Add LPDDR5X dram_type in use_ddr4_params
by Paul Menzel (Code Review) 26 Mar '24

26 Mar '24

Attention is currently required from: Ashish Kumar Mishra, Karthik Ramasubramanian. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81437?usp=email ) Change subject: lib/spd_bin: Add LPDDR5X dram_type in use_ddr4_params ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/81437/comment/5b51f871_c1951b6b : PS2, Line 9: For dram_type 21 the switch … [View More]

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[M] Change in coreboot[main]: soc/intel/xeon_sp: Add device to proximity domain map utils
by Patrick Rudolph (Code Review) 26 Mar '24

26 Mar '24

Attention is currently required from: Arthur Heymans, Chen, Gang C, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Shuo Liu, Tim Chu, Ziang Wang. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81440?usp=email ) Change subject: soc/intel/xeon_sp: Add device to proximity domain map utils ...................................................................... Patch Set 6: (1 comment) File src/soc/intel/xeon_sp/numa.c: https://… [View More]

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[M] Change in coreboot[main]: Support for creating hybrid vboot images
by Vladimir Serbinenko (Code Review) 26 Mar '24

26 Mar '24

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[M] Change in coreboot[main]: Support for creating hybrid vboot images
by Vladimir Serbinenko (Code Review) 26 Mar '24

26 Mar '24

Attention is currently required from: Julius Werner, Nick Vaccaro, Yu-Ping Wu. Vladimir Serbinenko has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81508?usp=email ) Change subject: Support for creating hybrid vboot images ...................................................................... Patch Set 5: (1 comment) Patchset: PS5: > I'm honestly not really sure what you're trying to do here anyway. […] My goal is to dual-boot between UEFI (or other … [View More]payload) and normal ChromeOS. Limitations: 1) RW needs to stay the same as changing it would break ChromeOS mechanism 2) Moreover ChromeOS may have requirements on coreboot so that it's advantageous to continue using unmodified RW to avoid breakage 3) Without some changes to ACPI and implementation of SMMSTORE some OS including Windows will not install at all and some may exhibit shortcomings (I think I had some but I don't use RW_LEGACY any longer) 4) FMAP layout can't be modified because of both RW and update requirements RO, on the other hand, can be modified after unlock. I understand payload phylosophy but here 2 scenarios of booting have contradictory requirements on ramstage: 1) Windows (and few other OS) need improved ACPI and SMMSTORE 2) ChromeOS needs coreboot not to change This is more akin to CMOS bootblock philosophy of switching between r[oa]mstage. Ans also akin the idea of using whatever space is available. We really have only 2 places to put alternative r[oa]mstage: RW_LEGACY and RO_COREBOOT. Former is tight on space. Hence the design proposed in those patches. I believe this configurable hack could be of value to chrultrabook community where "How to multiboot ChromeOS and Windows" is a common request -- To view, visit https://review.coreboot.org/c/coreboot/+/81508?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9b26c332f5bf6befd62b5930b19d1b20e76261e7 Gerrit-Change-Number: 81508 Gerrit-PatchSet: 5 Gerrit-Owner: Vladimir Serbinenko <phcoder(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Tue, 26 Mar 2024 15:10:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment [View Less]

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[L] Change in coreboot[main]: soc/intel/xeon_sp/spr: Support dynamic domain SSDT generation
by Shuo Liu (Code Review) 26 Mar '24

26 Mar '24

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Tim Chu. Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81377?usp=email ) Change subject: soc/intel/xeon_sp/spr: Support dynamic domain SSDT generation ...................................................................... Patch Set 11: (1 comment) File src/soc/intel/xeon_sp/chip_gen1.c: https://review.coreboot.org/c/… [View More]

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coreboot-gerrit March 2024