coreboot-gerrit March 2024

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[M] Change in coreboot[main]: soc/intel/xeon_sp: Add PD_TYPE_CLUSTER
by Shuo Liu (Code Review) 26 Mar '24

26 Mar '24

Attention is currently required from: Arthur Heymans, Chen, Gang C, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Tim Chu, Ziang Wang. Hello Arthur Heymans, Chen, Gang C, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Tim Chu, Ziang Wang, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81443?usp=email to look at the new patch set (#2). Change subject: soc/intel/xeon_sp: Add PD_TYPE_CLUSTER ...................................................................... soc/intel/xeon_sp: Add PD_TYPE_CLUSTER Add a new proximity type to represent the sub-NUMA cluster. Change-Id: I32558983780f302ff4893901540a90baebf47add Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> Signed-off-by: Ziang Wang <ziang.wang(a)intel.com> Signed-off-by: Gang Chen <gang.c.chen(a)intel.com> --- M src/soc/intel/xeon_sp/include/soc/numa.h M src/soc/intel/xeon_sp/numa.c M src/soc/intel/xeon_sp/spr/chip.c M src/soc/intel/xeon_sp/spr/soc_util.c M src/soc/intel/xeon_sp/uncore.c 5 files changed, 44 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/81443/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81443?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I32558983780f302ff4893901540a90baebf47add Gerrit-Change-Number: 81443 Gerrit-PatchSet: 2 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Ziang Wang <ziang.wang(a)intel.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Ziang Wang <ziang.wang(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: device/device_util: Use const qualifier
by Shuo Liu (Code Review) 26 Mar '24

26 Mar '24

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Jonathan Zhang, Jérémy Compostella, Lean Sheng Tan, Shuo Liu, Tim Chu. Shuo Liu has uploaded a new patch set (#13) to the change originally created by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/81275?usp=email ) The following approvals got outdated and were removed: Code-Review+2 by Shuo Liu, Verified+1 by build bot (Jenkins) Change subject: device/device_util: Use const qualifier ...................................................................... device/device_util: Use const qualifier Allows to use the function in more places that expect the struct device to be readonly. Change-Id: Iac04fe6931a43070f6638b399adbff2ce64829c9 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> --- M src/device/device_util.c M src/include/device/device.h M src/soc/intel/xeon_sp/chip_common.c M src/soc/intel/xeon_sp/include/soc/chip_common.h M src/soc/intel/xeon_sp/uncore_acpi.c 5 files changed, 24 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/81275/13 -- To view, visit https://review.coreboot.org/c/coreboot/+/81275?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iac04fe6931a43070f6638b399adbff2ce64829c9 Gerrit-Change-Number: 81275 Gerrit-PatchSet: 13 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: soc/intel/xeon_sp: Add PD_TYPE_CLUSTER
by Shuo Liu (Code Review) 26 Mar '24

26 Mar '24

Attention is currently required from: Arthur Heymans, Chen, Gang C, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Tim Chu, Ziang Wang. Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81443?usp=email ) Change subject: soc/intel/xeon_sp: Add PD_TYPE_CLUSTER ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Since the SPR FSP-API it not with full support for SNC, we have to stop here. However, we send out this codes to help our vendors to have their embargo SNC enabling based on some public settings. Open to any discussions. Thanks! -- To view, visit https://review.coreboot.org/c/coreboot/+/81443?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I32558983780f302ff4893901540a90baebf47add Gerrit-Change-Number: 81443 Gerrit-PatchSet: 1 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Ziang Wang <ziang.wang(a)intel.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Ziang Wang <ziang.wang(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Tue, 26 Mar 2024 12:54:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[main]: soc/intel/xeon_sp: Add PD_TYPE_CLUSTER
by Shuo Liu (Code Review) 26 Mar '24

26 Mar '24

Attention is currently required from: Arthur Heymans, Chen, Gang C, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Tim Chu, Ziang Wang. Hello Chen, Gang C, Ziang Wang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/81443?usp=email to review the following change. Change subject: soc/intel/xeon_sp: Add PD_TYPE_CLUSTER ...................................................................... soc/intel/xeon_sp: Add PD_TYPE_CLUSTER Add a new proximity type to represent the sub-NUMA cluster. Change-Id: I32558983780f302ff4893901540a90baebf47add Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> Signed-off-by: Ziang Wang <ziang.wang(a)intel.com> Signed-off-by: Gang Chen <gang.c.chen(a)intel.com> --- M src/soc/intel/xeon_sp/include/soc/numa.h M src/soc/intel/xeon_sp/numa.c M src/soc/intel/xeon_sp/spr/chip.c M src/soc/intel/xeon_sp/spr/soc_util.c M src/soc/intel/xeon_sp/uncore.c 5 files changed, 26 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/81443/1 diff --git a/src/soc/intel/xeon_sp/include/soc/numa.h b/src/soc/intel/xeon_sp/include/soc/numa.h index b00eb88..58a31da 100644 --- a/src/soc/intel/xeon_sp/include/soc/numa.h +++ b/src/soc/intel/xeon_sp/include/soc/numa.h @@ -17,6 +17,7 @@ * Generic Initiator domain is a CXL memory device. */ PD_TYPE_GENERIC_INITIATOR, + PD_TYPE_CLUSTER, PD_TYPE_MAX }; @@ -38,6 +39,7 @@ * sockets, so we need a bitmap. */ uint8_t socket_bitmap; + uint8_t cluster_bitmap; /* Relative distances (memory latency) from all domains */ uint8_t *distances; /* @@ -68,4 +70,6 @@ uint32_t memory_to_pd(const struct SystemMemoryMapElement *mem); uint32_t device_to_pd(const struct device *dev); +uint8_t soc_get_cluster_count(void); + #endif /* NUMA_H */ diff --git a/src/soc/intel/xeon_sp/numa.c b/src/soc/intel/xeon_sp/numa.c index 8340f4d..e9ffa18 100644 --- a/src/soc/intel/xeon_sp/numa.c +++ b/src/soc/intel/xeon_sp/numa.c @@ -19,6 +19,7 @@ printk(BIOS_DEBUG, "\tproximity domain %d:\n", i); printk(BIOS_DEBUG, "\t\ttype:%d\n", pds.pds[i].pd_type); printk(BIOS_DEBUG, "\t\tsocket_bitmap:0x%x\n", pds.pds[i].socket_bitmap); + printk(BIOS_DEBUG, "\t\tcluster_bitmap:0x%x\n", pds.pds[i].cluster_bitmap); printk(BIOS_DEBUG, "\t\tdevice:%s\n", pds.pds[i].dev ? dev_path(pds.pds[i].dev) : ""); printk(BIOS_DEBUG, "\t\tbase(64MB):0x%x\n", pds.pds[i].base); printk(BIOS_DEBUG, "\t\tsize(64MB):0x%x\n", pds.pds[i].size); @@ -29,6 +30,7 @@ { uint8_t num_sockets = soc_get_num_cpus(); uint8_t num_cxlnodes = get_cxl_node_count(); + uint8_t num_clusters = soc_get_cluster_count(); const IIO_UDS *hob = get_iio_uds(); /* @@ -42,7 +44,7 @@ * HDM has one and only one CXL node info entry. Each CXL node info entry * represents a generic initiator proximity domain. */ - pds.num_pds = num_cxlnodes + num_sockets; + pds.num_pds = num_cxlnodes + num_sockets + num_sockets * num_clusters; pds.pds = xmalloc(sizeof(struct proximity_domain) * pds.num_pds); if (!pds.pds) die("%s %d out of memory.", __FILE__, __LINE__); @@ -60,6 +62,16 @@ if (!pds.pds[i].distances) die("%s %d out of memory.", __FILE__, __LINE__); i++; + /* Fill in cluster domains */ + for (uint8_t cluster = 0; cluster < num_clusters; cluster++) { + pds.pds[i].pd_type = PD_TYPE_CLUSTER; + pds.pds[i].socket_bitmap = 1 << hob->PlatformData.IIO_resource[socket].SocketID; + pds.pds[i].cluster_bitmap = 1 << cluster; + pds.pds[i].distances = malloc(sizeof(uint8_t) * pds.num_pds); + if (!pds.pds[i].distances) + die("%s %d out of memory.", __FILE__, __LINE__); + i++; + } } /* If there are no CXL nodes, we are done */ @@ -97,7 +109,7 @@ uint32_t size = 0; for (i = 0; i < pds.num_pds; i++) { - if (pds.pds[i].pd_type == PD_TYPE_PROCESSOR) + if (pds.pds[i].pd_type != PD_TYPE_GENERIC_INITIATOR) continue; size += pds.pds[i].size; } @@ -166,3 +178,8 @@ } } } + +__weak uint8_t soc_get_cluster_count(void) +{ + return 0; +} diff --git a/src/soc/intel/xeon_sp/spr/chip.c b/src/soc/intel/xeon_sp/spr/chip.c index 7b934ba..30432b5 100644 --- a/src/soc/intel/xeon_sp/spr/chip.c +++ b/src/soc/intel/xeon_sp/spr/chip.c @@ -177,7 +177,7 @@ uint32_t ep_bus; uint8_t i; for (i = 0; i < pds.num_pds; i++) { - if (pds.pds[i].pd_type == PD_TYPE_PROCESSOR) + if (pds.pds[i].pd_type != PD_TYPE_GENERIC_INITIATOR) continue; ep_bus = PCI_BDF(pds.pds[i].dev) >> 20; if (ep_bus == ecrc_bus + 1) diff --git a/src/soc/intel/xeon_sp/spr/soc_util.c b/src/soc/intel/xeon_sp/spr/soc_util.c index 41b256c..7a3308d 100644 --- a/src/soc/intel/xeon_sp/spr/soc_util.c +++ b/src/soc/intel/xeon_sp/spr/soc_util.c @@ -93,7 +93,7 @@ bool is_iio_cxl_stack_res(const STACK_RES *res) { for (uint8_t i = 0; i < pds.num_pds; i++) { - if (pds.pds[i].pd_type == PD_TYPE_PROCESSOR) + if (pds.pds[i].pd_type != PD_TYPE_GENERIC_INITIATOR) continue; uint32_t bus = PCI_BDF(pds.pds[i].dev) >> 20; diff --git a/src/soc/intel/xeon_sp/uncore.c b/src/soc/intel/xeon_sp/uncore.c index 306aaf3..b2db4ed94 100644 --- a/src/soc/intel/xeon_sp/uncore.c +++ b/src/soc/intel/xeon_sp/uncore.c @@ -284,7 +284,7 @@ /* CXL Memory */ uint8_t i; for (i = 0; i < pds.num_pds; i++) { - if (pds.pds[i].pd_type == PD_TYPE_PROCESSOR) + if (pds.pds[i].pd_type != PD_TYPE_GENERIC_INITIATOR) continue; if (CONFIG(OCP_VPD)) { -- To view, visit https://review.coreboot.org/c/coreboot/+/81443?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I32558983780f302ff4893901540a90baebf47add Gerrit-Change-Number: 81443 Gerrit-PatchSet: 1 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Ziang Wang <ziang.wang(a)intel.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Ziang Wang <ziang.wang(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[main]: soc/intel/xeon_sp: Add fill_pd_distances
by Shuo Liu (Code Review) 26 Mar '24

26 Mar '24

Attention is currently required from: Chen, Gang C, Ziang Wang. Hello Chen, Gang C, Ziang Wang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/81442?usp=email to review the following change. Change subject: soc/intel/xeon_sp: Add fill_pd_distances ...................................................................... soc/intel/xeon_sp: Add fill_pd_distances Update a simple algorithm to cover some basic case for proximity domain distance handling, include NUMA and CXL 1.1 Type-2 devices. In the same time, the local variable usage of fill_pds() is optimized. Change-Id: I2b666dc2a140d1bb1fdff9bc7b835d5cf5b4bbc5 Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> Signed-off-by: Ziang Wang <ziang.wang(a)intel.com> Signed-off-by: Gang Chen <gang.c.chen(a)intel.com> --- M src/soc/intel/xeon_sp/include/soc/numa.h M src/soc/intel/xeon_sp/numa.c M src/soc/intel/xeon_sp/uncore.c 3 files changed, 36 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/81442/1 diff --git a/src/soc/intel/xeon_sp/include/soc/numa.h b/src/soc/intel/xeon_sp/include/soc/numa.h index 929b61c..b00eb88 100644 --- a/src/soc/intel/xeon_sp/include/soc/numa.h +++ b/src/soc/intel/xeon_sp/include/soc/numa.h @@ -57,6 +57,7 @@ void dump_pds(void); void fill_pds(void); +void fill_pd_distances(void); /* * Return the total size of memory regions in generic initiator affinity diff --git a/src/soc/intel/xeon_sp/numa.c b/src/soc/intel/xeon_sp/numa.c index 2c7bb65..8340f4d 100644 --- a/src/soc/intel/xeon_sp/numa.c +++ b/src/soc/intel/xeon_sp/numa.c @@ -50,8 +50,8 @@ memset(pds.pds, 0, sizeof(struct proximity_domain) * pds.num_pds); /* Fill in processor domains */ - uint8_t i, j, socket; - for (socket = 0, i = 0; i < num_sockets; socket++) { + uint8_t i = 0; + for (uint8_t socket = 0; socket < num_sockets; socket++) { if (!soc_cpu_is_enabled(socket)) continue; pds.pds[i].pd_type = PD_TYPE_PROCESSOR; @@ -59,13 +59,6 @@ pds.pds[i].distances = malloc(sizeof(uint8_t) * pds.num_pds); if (!pds.pds[i].distances) die("%s %d out of memory.", __FILE__, __LINE__); - /* hard code the distances for now, till we know how to calculate them. */ - for (j = 0; j < pds.num_pds; j++) { - if (j == i) - pds.pds[i].distances[j] = 0x0a; - else - pds.pds[i].distances[j] = 0x0e; - } i++; } @@ -75,10 +68,9 @@ #if CONFIG(SOC_INTEL_HAS_CXL) /* There are CXL nodes, fill in generic initiator domain after the processors pds */ - uint8_t skt_id, cxl_id; const CXL_NODE_SOCKET *cxl_hob = get_cxl_node(); - for (skt_id = 0, i = num_sockets; skt_id < MAX_SOCKET; skt_id++, i++) { - for (cxl_id = 0; cxl_id < cxl_hob[skt_id].CxlNodeCount; ++cxl_id) { + for (uint8_t skt_id = 0; skt_id < MAX_SOCKET; skt_id++) { + for (uint8_t cxl_id = 0; cxl_id < cxl_hob[skt_id].CxlNodeCount; ++cxl_id) { const CXL_NODE_INFO node = cxl_hob[skt_id].CxlNodeInfo[cxl_id]; pds.pds[i].pd_type = PD_TYPE_GENERIC_INITIATOR; pds.pds[i].socket_bitmap = node.SocketBitmap; @@ -89,13 +81,7 @@ pds.pds[i].distances = malloc(sizeof(uint8_t) * pds.num_pds); if (!pds.pds[i].distances) die("%s %d out of memory.", __FILE__, __LINE__); - /* hard code the distances until we know how to calculate them */ - for (j = 0; j < pds.num_pds; j++) { - if (j == i) - pds.pds[i].distances[j] = 0x0a; - else - pds.pds[i].distances[j] = 0x0e; - } + i++; } } #endif @@ -151,3 +137,32 @@ { return socket_to_pd(mem->SocketId); } + +#define PD_DISTANCE_SELF 0x0A +#define PD_DISTANCE_SAME_SOCKET 0x0C +#define PD_DISTANCE_CROSS_SOCKET 0x14 +#define PD_DISTANCE_MAX 0xFF +#define PD_DISTANCE_IO_EXTRA 0x01 + +void fill_pd_distances(void) +{ + for (int i = 0; i < pds.num_pds; i++) { + for (int j = 0; j < pds.num_pds; j++) { + if (i == j) { + pds.pds[i].distances[j] = PD_DISTANCE_SELF; + continue; + } + + if (pds.pds[i].socket_bitmap == pds.pds[j].socket_bitmap) + pds.pds[i].distances[j] = PD_DISTANCE_SAME_SOCKET; + else + pds.pds[i].distances[j] = PD_DISTANCE_CROSS_SOCKET; + + if (pds.pds[i].pd_type == PD_TYPE_GENERIC_INITIATOR) + pds.pds[i].distances[j] += PD_DISTANCE_IO_EXTRA; + + if (pds.pds[j].pd_type == PD_TYPE_GENERIC_INITIATOR) + pds.pds[i].distances[j] += PD_DISTANCE_IO_EXTRA; + } + } +} diff --git a/src/soc/intel/xeon_sp/uncore.c b/src/soc/intel/xeon_sp/uncore.c index 4af88cc..306aaf3 100644 --- a/src/soc/intel/xeon_sp/uncore.c +++ b/src/soc/intel/xeon_sp/uncore.c @@ -344,6 +344,7 @@ if (!once) { /* Construct NUMA data structure. This is needed for CXL. */ fill_pds(); + fill_pd_distances(); dump_pds(); once = true; } -- To view, visit https://review.coreboot.org/c/coreboot/+/81442?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2b666dc2a140d1bb1fdff9bc7b835d5cf5b4bbc5 Gerrit-Change-Number: 81442 Gerrit-PatchSet: 1 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Ziang Wang <ziang.wang(a)intel.com> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Ziang Wang <ziang.wang(a)intel.com> Gerrit-MessageType: newchange

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[L] Change in coreboot[main]: acpi: Add acpigen_write_OSC_pci_domain
by Shuo Liu (Code Review) 26 Mar '24

26 Mar '24

Attention is currently required from: Arthur Heymans, Christian Walter, Cliff Huang, Johnny Lin, Jonathan Zhang, Lance Zhao, Nico Huber, Paul Menzel, Tim Chu, Tim Wawrzynczak. Hello Arthur Heymans, Christian Walter, Cliff Huang, Johnny Lin, Jonathan Zhang, Lance Zhao, Lean Sheng Tan, Nico Huber, Patrick Rudolph, Tim Chu, Tim Wawrzynczak, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81375?usp=email to look at the new patch set (#13). Change subject: acpi: Add acpigen_write_OSC_pci_domain ...................................................................... acpi: Add acpigen_write_OSC_pci_domain Add dynamic PCI domain _OSC ASL generation codes, supporting both PCIe and CXL domains. Dynamic domain SSDT generation is not a must. It would be helpful for some SoC codes to better fit multiple SKUs and with strong CPU performance to run table generation logics. Change-Id: I711ce5350d718e47feb2912555108801ad7f918d Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> --- M src/acpi/acpigen_pci.c M src/include/acpi/acpigen_pci.h M src/soc/intel/xeon_sp/gnr/soc_acpi.c 3 files changed, 312 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/81375/13 -- To view, visit https://review.coreboot.org/c/coreboot/+/81375?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I711ce5350d718e47feb2912555108801ad7f918d Gerrit-Change-Number: 81375 Gerrit-PatchSet: 13 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset

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[L] Change in coreboot[main]: acpi: Add acpigen_write_OSC_pci_domain
by Shuo Liu (Code Review) 26 Mar '24

26 Mar '24

Attention is currently required from: Arthur Heymans, Christian Walter, Cliff Huang, Johnny Lin, Jonathan Zhang, Lance Zhao, Nico Huber, Paul Menzel, Tim Chu, Tim Wawrzynczak. Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81375?usp=email ) Change subject: acpi: Add acpigen_write_OSC_pci_domain ...................................................................... Patch Set 12: (6 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/81375/comment/38b83eed_62b25fe9 : PS12, Line 9: dynamic > Why? What runtime information does it depend on? This is mainly for xeon-sp codes that one set of codes needs to handle multiple SKU or silicon, where the PCIe/CXL domain layout are totally different, thus cannot be easily covered by one set of static DSDT. https://review.coreboot.org/c/coreboot/+/81375/comment/6bee088e_eff7be17 : PS12, Line 11: > Tested how? This patch is tested afterwards in https://review.coreboot.org/c/coreboot/+/81377. File src/acpi/acpigen_pci.c: https://review.coreboot.org/c/coreboot/+/81375/comment/7756058b_0c973ebe : PS12, Line 127: : if (is_cxl_domain) { : /* : * If ((Arg0 != ToUUID (PCI_HOST_BRIDGE_OSC_UUID)) && : * (Arg0 != ToUUID (CXL_HOST_BRIDGE_OSC_UUID))) : */ : acpigen_write_if(); : acpigen_emit_byte(LAND_OP); : acpigen_emit_byte(LNOT_OP); : acpigen_emit_byte(LEQUAL_OP); : acpigen_emit_byte(ARG0_OP); : acpigen_write_uuid(PCI_HOST_BRIDGE_OSC_UUID); : acpigen_emit_byte(LNOT_OP); : acpigen_emit_byte(LEQUAL_OP); : acpigen_emit_byte(ARG0_OP); : acpigen_write_uuid(CXL_HOST_BRIDGE_OSC_UUID); : } else { : /* : * If (Arg0 != ToUUID (PCI_HOST_BRIDGE_OSC_UUID)) : */ : acpigen_write_if(); : acpigen_emit_byte(LNOT_OP); : acpigen_emit_byte(LEQUAL_OP); : acpigen_emit_byte(ARG0_OP); : acpigen_write_uuid(PCI_HOST_BRIDGE_OSC_UUID); : } : : > This seems unnecessary, you could also make it an `If ... ElseIf ... Else UNRECOGNIZED_UUID` below. For PCIe domain, only PCIe UUID can be handled; but for CXL domain, it can handle both. Personally I think to separately list PCIe/CXL cases would be more clear? https://review.coreboot.org/c/coreboot/+/81375/comment/ac21714f_f6466284 : PS12, Line 272: |= > I see `RETE` is initially set to `0`. But the `|=` still seems odd (given […] Yes ... I only directly assign RETE when there is an immediately return after the assignment. For this site, since no directly return (at least in this function) the pattern is not used. https://review.coreboot.org/c/coreboot/+/81375/comment/04d67eb8_6340a858 : PS12, Line 317: acpigen_write_create_dword_field(LOCAL7_OP, 0x10, "OTRC"); > What about the PCIe fields? On this path, it seems we would return CTRL unaltered. […] The current assumption is, for a CXL domain, if the OS calls _OSC using a PCIe UUID, acpigen_OSC_handle_pcie_request will handle; if the OS calls _OSC using a CXL UUID, acpigen_OSC_handle_cxl_request will handle. For the current tested case, such logic is adequate. Maybe we could update later when there is some further needs? https://review.coreboot.org/c/coreboot/+/81375/comment/f5bf627d_3c2971f2 : PS12, Line 348: __weak unsigned long get_granted_pci_features(const struct device *domain) : { : return 0; : } : : __weak unsigned long get_granted_cxl_features(const struct device *domain) : { : return 0; : } > The whole code above seems to do nothing without these. […] Please refer to https://review.coreboot.org/c/coreboot/+/81377 where the code is called and tested. The main reason is that different mainboard/SoC might have different _OSC feature granted based on its capability and user config, hence the mainboard/SoC codes can override this to link their logics. -- To view, visit https://review.coreboot.org/c/coreboot/+/81375?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I711ce5350d718e47feb2912555108801ad7f918d Gerrit-Change-Number: 81375 Gerrit-PatchSet: 12 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Tue, 26 Mar 2024 12:46:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: lib/spd_bin: Add LPDDR5X dram_type in use_ddr4_params
by Subrata Banik (Code Review) 26 Mar '24

26 Mar '24

Attention is currently required from: Ashish Kumar Mishra, Karthik Ramasubramanian. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81437?usp=email ) Change subject: lib/spd_bin: Add LPDDR5X dram_type in use_ddr4_params ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81437?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id78ef90c0dc2e869c1f0424674b982ba64ba3939 Gerrit-Change-Number: 81437 Gerrit-PatchSet: 3 Gerrit-Owner: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Tue, 26 Mar 2024 11:45:28 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: drivers/mipi: Fine tune clock for BOE_NV110WUM_L60 and IVO_T109NW41
by Paul Menzel (Code Review) 26 Mar '24

26 Mar '24

Attention is currently required from: Ruihai Zhou, Yidi Lin, cong yang. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81438?usp=email ) Change subject: drivers/mipi: Fine tune clock for BOE_NV110WUM_L60 and IVO_T109NW41 ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/81438/comment/34b50b89_9a8d6a40 : PS4, Line 11: Just keep consistent with the Linux kernel panel driver : configuration. Please reference the commit and the file. -- To view, visit https://review.coreboot.org/c/coreboot/+/81438?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic44c86f062d4e836f403ee97f2fc6370fff02797 Gerrit-Change-Number: 81438 Gerrit-PatchSet: 4 Gerrit-Owner: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: cong yang <yangcong5(a)huaqin.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Gerrit-Attention: cong yang <yangcong5(a)huaqin.corp-partner.google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Tue, 26 Mar 2024 11:36:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: lib/spd_bin: Add LPDDR5X dram_type in use_ddr4_params
by Paul Menzel (Code Review) 26 Mar '24

26 Mar '24

Attention is currently required from: Ashish Kumar Mishra, Karthik Ramasubramanian, Subrata Banik. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81437?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: lib/spd_bin: Add LPDDR5X dram_type in use_ddr4_params ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/81437/comment/22808f7a_b9aaf609 : PS3, Line 15: [NOTE ] Defaulting to using DDR4 params. Please add dram_type check for : 21 to use_ddr4_params Please use one line and indent it by four spaces. -- To view, visit https://review.coreboot.org/c/coreboot/+/81437?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id78ef90c0dc2e869c1f0424674b982ba64ba3939 Gerrit-Change-Number: 81437 Gerrit-PatchSet: 3 Gerrit-Owner: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Tue, 26 Mar 2024 11:36:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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