coreboot-gerrit March 2024

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[S] Change in coreboot[main]: device/device_util: Use const qualifier
by Shuo Liu (Code Review) 26 Mar '24

26 Mar '24

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Jonathan Zhang, Jérémy Compostella, Lean Sheng Tan, Patrick Rudolph, Tim Chu. Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81275?usp=email ) Change subject: device/device_util: Use const qualifier ...................................................................... Patch Set 11: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81275?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iac04fe6931a43070f6638b399adbff2ce64829c9 Gerrit-Change-Number: 81275 Gerrit-PatchSet: 11 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Tue, 26 Mar 2024 10:23:21 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: device/device_util: Use const qualifier
by Shuo Liu (Code Review) 26 Mar '24

26 Mar '24

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Jonathan Zhang, Jérémy Compostella, Lean Sheng Tan, Patrick Rudolph, Tim Chu. Shuo Liu has uploaded a new patch set (#11) to the change originally created by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/81275?usp=email ) Change subject: device/device_util: Use const qualifier ...................................................................... device/device_util: Use const qualifier Allows to use the function in more places that expect the struct device to be readonly. Change-Id: Iac04fe6931a43070f6638b399adbff2ce64829c9 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> --- M src/device/device_util.c M src/include/device/device.h M src/soc/intel/xeon_sp/chip_common.c M src/soc/intel/xeon_sp/include/soc/chip_common.h M src/soc/intel/xeon_sp/uncore_acpi.c 5 files changed, 21 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/81275/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/81275?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iac04fe6931a43070f6638b399adbff2ce64829c9 Gerrit-Change-Number: 81275 Gerrit-PatchSet: 11 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: device/device_util: Use const qualifier
by Shuo Liu (Code Review) 26 Mar '24

26 Mar '24

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Jonathan Zhang, Jérémy Compostella, Lean Sheng Tan, Patrick Rudolph, Tim Chu. Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81275?usp=email ) Change subject: device/device_util: Use const qualifier ...................................................................... Patch Set 10: (1 comment) File src/device/device_util.c: https://review.coreboot.org/c/coreboot/+/81275/comment/d9c0144e_c4464fa6 : PS2, Line 252: given PCI device > I make an update and hope this could be okay. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/81275?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iac04fe6931a43070f6638b399adbff2ce64829c9 Gerrit-Change-Number: 81275 Gerrit-PatchSet: 10 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Tue, 26 Mar 2024 10:20:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: device/device_util: Use const qualifier
by Shuo Liu (Code Review) 26 Mar '24

26 Mar '24

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Jonathan Zhang, Jérémy Compostella, Lean Sheng Tan, Patrick Rudolph, Tim Chu. Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81275?usp=email ) Change subject: device/device_util: Use const qualifier ...................................................................... Patch Set 10: (1 comment) File src/device/device_util.c: https://review.coreboot.org/c/coreboot/+/81275/comment/379be5fe_9d79d19c : PS2, Line 252: given PCI device > struct device could be anything. […] I make an update and hope this could be okay. -- To view, visit https://review.coreboot.org/c/coreboot/+/81275?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iac04fe6931a43070f6638b399adbff2ce64829c9 Gerrit-Change-Number: 81275 Gerrit-PatchSet: 10 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Tue, 26 Mar 2024 10:20:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: device/device_util: Use const qualifier
by Shuo Liu (Code Review) 26 Mar '24

26 Mar '24

Attention is currently required from: Christian Walter, Johnny Lin, Jonathan Zhang, Jérémy Compostella, Lean Sheng Tan, Patrick Rudolph, Tim Chu. Shuo Liu has uploaded a new patch set (#10) to the change originally created by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/81275?usp=email ) Change subject: device/device_util: Use const qualifier ...................................................................... device/device_util: Use const qualifier Allows to use the function in more places that expect the struct device to be readonly. Change-Id: Iac04fe6931a43070f6638b399adbff2ce64829c9 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> --- M src/device/device_util.c M src/include/device/device.h M src/soc/intel/xeon_sp/chip_common.c M src/soc/intel/xeon_sp/include/soc/chip_common.h M src/soc/intel/xeon_sp/uncore_acpi.c 5 files changed, 21 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/81275/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/81275?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iac04fe6931a43070f6638b399adbff2ce64829c9 Gerrit-Change-Number: 81275 Gerrit-PatchSet: 10 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: soc/intel/xeon_sp: Update FSP-T UPD for FSP2.4
by Lean Sheng Tan (Code Review) 26 Mar '24

26 Mar '24

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81313?usp=email ) ( 8 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/intel/xeon_sp: Update FSP-T UPD for FSP2.4 ...................................................................... soc/intel/xeon_sp: Update FSP-T UPD for FSP2.4 FSP2.4 and previous FSP versions have different FSP-T UPD parameter settings. Change-Id: I48384944ac69636cca2acd8169d3dd15f90362ec Signed-off-by: Li, Jincheng <jincheng.li(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81313 Reviewed-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/xeon_sp/bootblock.c 1 file changed, 27 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved diff --git a/src/soc/intel/xeon_sp/bootblock.c b/src/soc/intel/xeon_sp/bootblock.c index 62ca48f..3e9922f6 100644 --- a/src/soc/intel/xeon_sp/bootblock.c +++ b/src/soc/intel/xeon_sp/bootblock.c @@ -14,6 +14,32 @@ #include <soc/iomap.h> #include <soc/pci_devs.h> +#if (CONFIG(PLATFORM_USES_FSP2_4)) +const FSPT_UPD temp_ram_init_params = { + .FspUpdHeader = { + .Signature = FSPT_UPD_SIGNATURE, + .Revision = 2, + .Reserved = {0}, + }, + .FsptArchUpd = { + .Revision = 2, + .Length = 32, + .FspDebugHandler = 0, + .Reserved1 = {0}, + }, + .FsptCoreUpd = { + .MicrocodeRegionBase = 0, + .MicrocodeRegionLength = 0, + .CodeRegionBase = (UINT64)CACHE_ROM_BASE, + .CodeRegionLength = (UINT64)CACHE_ROM_SIZE, + }, + .FsptConfig = { + .FsptPort80RouteDisable = 0, + .ReservedTempRamInitUpd = {0}, + }, + .UpdTerminator = 0x55AA, +}; +#else const FSPT_UPD temp_ram_init_params = { .FspUpdHeader = { .Signature = FSPT_UPD_SIGNATURE, @@ -34,6 +60,7 @@ .UnusedUpdSpace0 = {0}, .UpdTerminator = 0x55AA, }; +#endif //(!CONFIG(PLATFORM_USES_FSP2_4)) static uint64_t assembly_timestamp; static uint64_t bootblock_timestamp; -- To view, visit https://review.coreboot.org/c/coreboot/+/81313?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I48384944ac69636cca2acd8169d3dd15f90362ec Gerrit-Change-Number: 81313 Gerrit-PatchSet: 18 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[L] Change in coreboot[main]: soc/intel/xeon_sp: Share DDR codes across Xeon-SP platforms
by Lean Sheng Tan (Code Review) 26 Mar '24

26 Mar '24

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81219?usp=email ) Change subject: soc/intel/xeon_sp: Share DDR codes across Xeon-SP platforms ...................................................................... soc/intel/xeon_sp: Share DDR codes across Xeon-SP platforms DDR support codes across generations are similar. Share the codes to improve code reuse. TEST=intel/archercity CRB Change-Id: I237d561003671d70dfaaa9823a0cf16d6e1f50cf Signed-off-by: Jincheng Li <jincheng.li(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81219 Reviewed-by: Shuo Liu <shuo.liu(a)intel.com> Reviewed-by: Nico Huber <nico.h(a)gmx.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/intel/xeon_sp/Makefile.mk M src/soc/intel/xeon_sp/cpx/Makefile.mk D src/soc/intel/xeon_sp/cpx/ddr.c D src/soc/intel/xeon_sp/cpx/include/soc/ddr.h A src/soc/intel/xeon_sp/ddr.c A src/soc/intel/xeon_sp/include/soc/ddr.h M src/soc/intel/xeon_sp/spr/Makefile.mk D src/soc/intel/xeon_sp/spr/ddr.c D src/soc/intel/xeon_sp/spr/include/soc/ddr.h M src/soc/intel/xeon_sp/spr/romstage.c 10 files changed, 170 insertions(+), 300 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved Nico Huber: Looks good to me, but someone else must approve Shuo Liu: Looks good to me, approved diff --git a/src/soc/intel/xeon_sp/Makefile.mk b/src/soc/intel/xeon_sp/Makefile.mk index 5891544..1f96bb7 100644 --- a/src/soc/intel/xeon_sp/Makefile.mk +++ b/src/soc/intel/xeon_sp/Makefile.mk @@ -7,7 +7,7 @@ subdirs-$(CONFIG_SOC_INTEL_SAPPHIRERAPIDS_SP) += spr ebg bootblock-y += bootblock.c spi.c lpc.c pch.c report_platform.c -romstage-y += romstage.c reset.c util.c spi.c pmutil.c memmap.c +romstage-y += romstage.c reset.c util.c spi.c pmutil.c memmap.c ddr.c romstage-y += ../../../cpu/intel/car/romstage.c ramstage-y += uncore.c reset.c util.c lpc.c spi.c ramstage.c chip_common.c ramstage-y += memmap.c pch.c lockdown.c finalize.c diff --git a/src/soc/intel/xeon_sp/cpx/Makefile.mk b/src/soc/intel/xeon_sp/cpx/Makefile.mk index 911cf66..095ad59 100644 --- a/src/soc/intel/xeon_sp/cpx/Makefile.mk +++ b/src/soc/intel/xeon_sp/cpx/Makefile.mk @@ -5,7 +5,7 @@ subdirs-y += ../../../../cpu/intel/turbo subdirs-y += ../../../../cpu/intel/microcode -romstage-y += romstage.c ddr.c soc_util.c +romstage-y += romstage.c soc_util.c romstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c romstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c diff --git a/src/soc/intel/xeon_sp/cpx/ddr.c b/src/soc/intel/xeon_sp/cpx/ddr.c deleted file mode 100644 index 990711f..0000000 --- a/src/soc/intel/xeon_sp/cpx/ddr.c +++ /dev/null @@ -1,89 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#include <soc/ddr.h> - -uint32_t get_ddr_voltage(uint8_t DdrVoltage) -{ - /* SPD Byte 11: Module Nominal Voltage, currently DDR4 only supports 1.2V. - Either Bit 0 or Bit 1 is set, return 1.2V */ - if (DdrVoltage & 0x3) - return 1200; - return 0; -} - -uint16_t get_max_memory_speed(uint32_t commonTck) -{ - if (commonTck <= DDR_8400_TCK_MIN) - return 8400; - else if (commonTck <= DDR_6400_TCK_MIN) - return 6400; - else if (commonTck <= DDR_6000_TCK_MIN) - return 6000; - else if (commonTck <= DDR_5600_TCK_MIN) - return 5600; - else if (commonTck <= DDR_5200_TCK_MIN) - return 5200; - else if (commonTck <= DDR_4800_TCK_MIN) - return 4800; - else if (commonTck <= DDR_4400_TCK_MIN) - return 4400; - else if (commonTck <= DDR_4266_TCK_MIN) - return 4266; - else if (commonTck <= DDR_4200_TCK_MIN) - return 4200; - else if (commonTck <= DDR_4000_TCK_MIN) - return 4000; - else if (commonTck <= DDR_3800_TCK_MIN) - return 3800; - else if (commonTck <= DDR_3733_TCK_MIN) - return 3733; - else if (commonTck <= DDR_3600_TCK_MIN) - return 3600; - else if (commonTck <= DDR_3466_TCK_MIN) - return 3466; - else if (commonTck <= DDR_3400_TCK_MIN) - return 3400; - else if (commonTck <= DDR_3200_TCK_MIN) - return 3200; - else if (commonTck <= DDR_3000_TCK_MIN) - return 3000; - else if (commonTck <= DDR_2933_TCK_MIN) - return 2933; - else if (commonTck <= DDR_2800_TCK_MIN) - return 2800; - else if (commonTck <= DDR_2666_TCK_MIN) - return 2666; - else if (commonTck <= DDR_2600_TCK_MIN) - return 2600; - else if (commonTck <= DDR_2400_TCK_MIN) - return 2400; - else if (commonTck <= DDR_2200_TCK_MIN) - return 2200; - else if (commonTck <= DDR_2133_TCK_MIN) - return 2133; - else if (commonTck <= DDR_2000_TCK_MIN) - return 2000; - else if (commonTck <= DDR_1866_TCK_MIN) - return 1866; - else if (commonTck <= DDR_1800_TCK_MIN) - return 1800; - else if (commonTck <= DDR_1600_TCK_MIN) - return 1600; - else if (commonTck <= DDR_1400_TCK_MIN) - return 1400; - else if (commonTck <= DDR_1333_TCK_MIN) - return 1333; - else if (commonTck <= DDR_1200_TCK_MIN) - return 1200; - else if (commonTck <= DDR_1066_TCK_MIN) - return 1066; - else if (commonTck <= DDR_1000_TCK_MIN) - return 1000; - else - return 800; -} - -__weak bool mainboard_dimm_slot_exists(uint8_t socket, uint8_t channel, uint8_t slot) -{ - return false; -} diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/ddr.h b/src/soc/intel/xeon_sp/cpx/include/soc/ddr.h deleted file mode 100644 index 0ef6ded..0000000 --- a/src/soc/intel/xeon_sp/cpx/include/soc/ddr.h +++ /dev/null @@ -1,53 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#ifndef _CPX_DDR_H_ -#define _CPX_DDR_H_ - -#include <types.h> - -/* DDR_*_TCK_MIN are in picoseconds */ -#define DDR_800_TCK_MIN 2500 -#define DDR_1000_TCK_MIN 2000 -#define DDR_1066_TCK_MIN 1875 -#define DDR_1200_TCK_MIN 1667 -#define DDR_1333_TCK_MIN 1500 -#define DDR_1400_TCK_MIN 1429 -#define DDR_1600_TCK_MIN 1250 -#define DDR_1800_TCK_MIN 1110 -#define DDR_1866_TCK_MIN 1071 -#define DDR_2000_TCK_MIN 1000 -#define DDR_2133_TCK_MIN 938 -#define DDR_2200_TCK_MIN 909 -#define DDR_2400_TCK_MIN 833 -#define DDR_2600_TCK_MIN 769 -#define DDR_2666_TCK_MIN 750 -#define DDR_2800_TCK_MIN 714 -#define DDR_2933_TCK_MIN 682 -#define DDR_3000_TCK_MIN 667 -#define DDR_3200_TCK_MIN 625 -#define DDR_3400_TCK_MIN 589 -#define DDR_3466_TCK_MIN 577 -#define DDR_3600_TCK_MIN 556 -#define DDR_3733_TCK_MIN 536 -#define DDR_3800_TCK_MIN 527 -#define DDR_4000_TCK_MIN 500 -#define DDR_4200_TCK_MIN 477 -#define DDR_4266_TCK_MIN 469 -#define DDR_4400_TCK_MIN 455 -#define DDR_4800_TCK_MIN 417 -#define DDR_5200_TCK_MIN 385 -#define DDR_5600_TCK_MIN 358 -#define DDR_6000_TCK_MIN 334 -#define DDR_6400_TCK_MIN 313 -#define DDR_6800_TCK_MIN 295 -#define DDR_7200_TCK_MIN 278 -#define DDR_7600_TCK_MIN 264 -#define DDR_8000_TCK_MIN 250 -#define DDR_8400_TCK_MIN 239 - -uint16_t get_max_memory_speed(uint32_t commonTck); -uint32_t get_ddr_voltage(uint8_t DdrVoltage); - -bool mainboard_dimm_slot_exists(uint8_t socket, uint8_t channel, uint8_t slot); - -#endif /* _CPX_DDR_H_ */ diff --git a/src/soc/intel/xeon_sp/ddr.c b/src/soc/intel/xeon_sp/ddr.c new file mode 100644 index 0000000..de248ca --- /dev/null +++ b/src/soc/intel/xeon_sp/ddr.c @@ -0,0 +1,107 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <soc/ddr.h> + +uint32_t get_ddr_voltage(uint8_t ddr_voltage) +{ + /* SPD Byte 11: Module Nominal Voltage, currently DDR4 only supports 1.2V. + Either Bit 0 or Bit 1 is set, return 1.2V */ + if (ddr_voltage & 0x3) + return 1200; + return 0; +} + +unsigned int get_ddr_millivolt(unsigned int ddr_voltage) +{ + switch (ddr_voltage) { + case SPD_VDD_DDR4: + return 1200; + case SPD_VDD_DDR5: + return 1100; + default: + return 0; + } +} + +unsigned int get_max_memory_speed(unsigned int common_tck) +{ + if (common_tck <= DDR_8400_TCK_MIN) + return 8400; + else if (common_tck <= DDR_7600_TCK_MIN) + return 7600; + else if (common_tck <= DDR_7200_TCK_MIN) + return 7200; + else if (common_tck <= DDR_6800_TCK_MIN) + return 6800; + else if (common_tck <= DDR_6400_TCK_MIN) + return 6400; + else if (common_tck <= DDR_6000_TCK_MIN) + return 6000; + else if (common_tck <= DDR_5600_TCK_MIN) + return 5600; + else if (common_tck <= DDR_5200_TCK_MIN) + return 5200; + else if (common_tck <= DDR_4800_TCK_MIN) + return 4800; + else if (common_tck <= DDR_4400_TCK_MIN) + return 4400; + else if (common_tck <= DDR_4266_TCK_MIN) + return 4266; + else if (common_tck <= DDR_4200_TCK_MIN) + return 4200; + else if (common_tck <= DDR_4000_TCK_MIN) + return 4000; + else if (common_tck <= DDR_3800_TCK_MIN) + return 3800; + else if (common_tck <= DDR_3733_TCK_MIN) + return 3733; + else if (common_tck <= DDR_3600_TCK_MIN) + return 3600; + else if (common_tck <= DDR_3466_TCK_MIN) + return 3466; + else if (common_tck <= DDR_3400_TCK_MIN) + return 3400; + else if (common_tck <= DDR_3200_TCK_MIN) + return 3200; + else if (common_tck <= DDR_3000_TCK_MIN) + return 3000; + else if (common_tck <= DDR_2933_TCK_MIN) + return 2933; + else if (common_tck <= DDR_2800_TCK_MIN) + return 2800; + else if (common_tck <= DDR_2666_TCK_MIN) + return 2666; + else if (common_tck <= DDR_2600_TCK_MIN) + return 2600; + else if (common_tck <= DDR_2400_TCK_MIN) + return 2400; + else if (common_tck <= DDR_2200_TCK_MIN) + return 2200; + else if (common_tck <= DDR_2133_TCK_MIN) + return 2133; + else if (common_tck <= DDR_2000_TCK_MIN) + return 2000; + else if (common_tck <= DDR_1866_TCK_MIN) + return 1866; + else if (common_tck <= DDR_1800_TCK_MIN) + return 1800; + else if (common_tck <= DDR_1600_TCK_MIN) + return 1600; + else if (common_tck <= DDR_1400_TCK_MIN) + return 1400; + else if (common_tck <= DDR_1333_TCK_MIN) + return 1333; + else if (common_tck <= DDR_1200_TCK_MIN) + return 1200; + else if (common_tck <= DDR_1066_TCK_MIN) + return 1066; + else if (common_tck <= DDR_1000_TCK_MIN) + return 1000; + else + return 800; +} + +__weak bool mainboard_dimm_slot_exists(uint8_t socket, uint8_t channel, uint8_t slot) +{ + return false; +} diff --git a/src/soc/intel/xeon_sp/include/soc/ddr.h b/src/soc/intel/xeon_sp/include/soc/ddr.h new file mode 100644 index 0000000..bb10caa --- /dev/null +++ b/src/soc/intel/xeon_sp/include/soc/ddr.h @@ -0,0 +1,60 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef _SOC_DDR_H_ +#define _SOC_DDR_H_ + +#include <types.h> + +/* SPD Byte 11: Module Nominal Voltage + * currently DDR4 only supports 1.2V, DDR5 only supports 1.1V. */ +#define SPD_VDD_DDR4 3 +#define SPD_VDD_DDR5 0 +#define SPD_TYPE_DDR5 0x12 + +/* DDR_*_TCK_MIN are in picoseconds */ +#define DDR_800_TCK_MIN 2500 +#define DDR_1000_TCK_MIN 2000 +#define DDR_1066_TCK_MIN 1875 +#define DDR_1200_TCK_MIN 1667 +#define DDR_1333_TCK_MIN 1500 +#define DDR_1400_TCK_MIN 1429 +#define DDR_1600_TCK_MIN 1250 +#define DDR_1800_TCK_MIN 1110 +#define DDR_1866_TCK_MIN 1071 +#define DDR_2000_TCK_MIN 1000 +#define DDR_2133_TCK_MIN 938 +#define DDR_2200_TCK_MIN 909 +#define DDR_2400_TCK_MIN 833 +#define DDR_2600_TCK_MIN 769 +#define DDR_2666_TCK_MIN 750 +#define DDR_2800_TCK_MIN 714 +#define DDR_2933_TCK_MIN 682 +#define DDR_3000_TCK_MIN 667 +#define DDR_3200_TCK_MIN 625 +#define DDR_3400_TCK_MIN 589 +#define DDR_3466_TCK_MIN 577 +#define DDR_3600_TCK_MIN 556 +#define DDR_3733_TCK_MIN 536 +#define DDR_3800_TCK_MIN 527 +#define DDR_4000_TCK_MIN 500 +#define DDR_4200_TCK_MIN 477 +#define DDR_4266_TCK_MIN 469 +#define DDR_4400_TCK_MIN 455 +#define DDR_4800_TCK_MIN 417 +#define DDR_5200_TCK_MIN 385 +#define DDR_5600_TCK_MIN 358 +#define DDR_6000_TCK_MIN 334 +#define DDR_6400_TCK_MIN 313 +#define DDR_6800_TCK_MIN 295 +#define DDR_7200_TCK_MIN 278 +#define DDR_7600_TCK_MIN 264 +#define DDR_8000_TCK_MIN 250 +#define DDR_8400_TCK_MIN 239 + +unsigned int get_max_memory_speed(unsigned int commonTck); +unsigned int get_ddr_millivolt(unsigned int ddr_voltage); +uint32_t get_ddr_voltage(uint8_t DdrVoltage); + +bool mainboard_dimm_slot_exists(uint8_t socket, uint8_t channel, uint8_t slot); + +#endif /* _SOC_DDR_H_ */ diff --git a/src/soc/intel/xeon_sp/spr/Makefile.mk b/src/soc/intel/xeon_sp/spr/Makefile.mk index fc8ab17..d999f30 100644 --- a/src/soc/intel/xeon_sp/spr/Makefile.mk +++ b/src/soc/intel/xeon_sp/spr/Makefile.mk @@ -8,7 +8,7 @@ subdirs-y += ../../../../cpu/x86/tsc subdirs-y += ../../../../cpu/intel/microcode -romstage-y += romstage.c soc_util.c ddr.c +romstage-y += romstage.c soc_util.c romstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c romstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c diff --git a/src/soc/intel/xeon_sp/spr/ddr.c b/src/soc/intel/xeon_sp/spr/ddr.c deleted file mode 100644 index ff61a7e..0000000 --- a/src/soc/intel/xeon_sp/spr/ddr.c +++ /dev/null @@ -1,93 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#include <soc/ddr.h> - -unsigned int get_ddr_millivolt(unsigned int ddr_voltage) -{ - switch (ddr_voltage) { - case SPD_VDD_DDR4: - return 1200; - case SPD_VDD_DDR5: - return 1100; - default: - return 0; - } -} - -unsigned int get_max_memory_speed(unsigned int commonTck) -{ - if (commonTck <= DDR_8400_TCK_MIN) - return 8400; - else if (commonTck <= DDR_7600_TCK_MIN) - return 7600; - else if (commonTck <= DDR_7200_TCK_MIN) - return 7200; - else if (commonTck <= DDR_6800_TCK_MIN) - return 6800; - else if (commonTck <= DDR_6400_TCK_MIN) - return 6400; - else if (commonTck <= DDR_6000_TCK_MIN) - return 6000; - else if (commonTck <= DDR_5600_TCK_MIN) - return 5600; - else if (commonTck <= DDR_5200_TCK_MIN) - return 5200; - else if (commonTck <= DDR_4800_TCK_MIN) - return 4800; - else if (commonTck <= DDR_4400_TCK_MIN) - return 4400; - else if (commonTck <= DDR_4266_TCK_MIN) - return 4266; - else if (commonTck <= DDR_4200_TCK_MIN) - return 4200; - else if (commonTck <= DDR_4000_TCK_MIN) - return 4000; - else if (commonTck <= DDR_3800_TCK_MIN) - return 3800; - else if (commonTck <= DDR_3733_TCK_MIN) - return 3733; - else if (commonTck <= DDR_3600_TCK_MIN) - return 3600; - else if (commonTck <= DDR_3466_TCK_MIN) - return 3466; - else if (commonTck <= DDR_3400_TCK_MIN) - return 3400; - else if (commonTck <= DDR_3200_TCK_MIN) - return 3200; - else if (commonTck <= DDR_3000_TCK_MIN) - return 3000; - else if (commonTck <= DDR_2933_TCK_MIN) - return 2933; - else if (commonTck <= DDR_2800_TCK_MIN) - return 2800; - else if (commonTck <= DDR_2666_TCK_MIN) - return 2666; - else if (commonTck <= DDR_2600_TCK_MIN) - return 2600; - else if (commonTck <= DDR_2400_TCK_MIN) - return 2400; - else if (commonTck <= DDR_2200_TCK_MIN) - return 2200; - else if (commonTck <= DDR_2133_TCK_MIN) - return 2133; - else if (commonTck <= DDR_2000_TCK_MIN) - return 2000; - else if (commonTck <= DDR_1866_TCK_MIN) - return 1866; - else if (commonTck <= DDR_1800_TCK_MIN) - return 1800; - else if (commonTck <= DDR_1600_TCK_MIN) - return 1600; - else if (commonTck <= DDR_1400_TCK_MIN) - return 1400; - else if (commonTck <= DDR_1333_TCK_MIN) - return 1333; - else if (commonTck <= DDR_1200_TCK_MIN) - return 1200; - else if (commonTck <= DDR_1066_TCK_MIN) - return 1066; - else if (commonTck <= DDR_1000_TCK_MIN) - return 1000; - else - return 800; -} diff --git a/src/soc/intel/xeon_sp/spr/include/soc/ddr.h b/src/soc/intel/xeon_sp/spr/include/soc/ddr.h deleted file mode 100644 index f2dc5c8..0000000 --- a/src/soc/intel/xeon_sp/spr/include/soc/ddr.h +++ /dev/null @@ -1,57 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#ifndef _SPR_DDR_H_ -#define _SPR_DDR_H_ - -#include <types.h> - -/* SPD Byte 11: Module Nominal Voltage - * currently DDR4 only supports 1.2V, DDR5 only supports 1.1V. */ -#define SPD_VDD_DDR4 3 -#define SPD_VDD_DDR5 0 -#define SPD_TYPE_DDR5 0x12 - -/* DDR_*_TCK_MIN are in picoseconds */ -#define DDR_1000_TCK_MIN 2000 -#define DDR_1066_TCK_MIN 1875 -#define DDR_1200_TCK_MIN 1667 -#define DDR_1333_TCK_MIN 1500 -#define DDR_1400_TCK_MIN 1429 -#define DDR_1600_TCK_MIN 1250 -#define DDR_1800_TCK_MIN 1110 -#define DDR_1866_TCK_MIN 1071 -#define DDR_2000_TCK_MIN 1000 -#define DDR_2133_TCK_MIN 938 -#define DDR_2200_TCK_MIN 909 -#define DDR_2400_TCK_MIN 833 -#define DDR_2600_TCK_MIN 769 -#define DDR_2666_TCK_MIN 750 -#define DDR_2800_TCK_MIN 714 -#define DDR_2933_TCK_MIN 682 -#define DDR_3000_TCK_MIN 667 -#define DDR_3200_TCK_MIN 625 -#define DDR_3400_TCK_MIN 589 -#define DDR_3466_TCK_MIN 577 -#define DDR_3600_TCK_MIN 556 -#define DDR_3733_TCK_MIN 536 -#define DDR_3800_TCK_MIN 527 -#define DDR_4000_TCK_MIN 500 -#define DDR_4200_TCK_MIN 477 -#define DDR_4266_TCK_MIN 469 -#define DDR_4400_TCK_MIN 455 -#define DDR_4800_TCK_MIN 417 -#define DDR_5200_TCK_MIN 385 -#define DDR_5600_TCK_MIN 358 -#define DDR_6000_TCK_MIN 334 -#define DDR_6400_TCK_MIN 313 -#define DDR_6800_TCK_MIN 295 -#define DDR_7200_TCK_MIN 278 -#define DDR_7600_TCK_MIN 264 -#define DDR_8000_TCK_MIN 250 -#define DDR_8400_TCK_MIN 239 - -unsigned int get_max_memory_speed(unsigned int commonTck); -unsigned int get_ddr_millivolt(unsigned int ddr_voltage); -bool mainboard_dimm_slot_exists(uint8_t socket, uint8_t channel, uint8_t slot); - -#endif /* _SPR_DDR_H_ */ diff --git a/src/soc/intel/xeon_sp/spr/romstage.c b/src/soc/intel/xeon_sp/spr/romstage.c index 74976b3..3b38828 100644 --- a/src/soc/intel/xeon_sp/spr/romstage.c +++ b/src/soc/intel/xeon_sp/spr/romstage.c @@ -32,11 +32,6 @@ /* Default weak implementation */ } -bool __weak mainboard_dimm_slot_exists(uint8_t socket, uint8_t channel, uint8_t dimm) -{ - return false; -} - /* * Search from VPD_RW first then VPD_RO for UPD config variables, * overwrites them from VPD if it's found. -- To view, visit https://review.coreboot.org/c/coreboot/+/81219?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I237d561003671d70dfaaa9823a0cf16d6e1f50cf Gerrit-Change-Number: 81219 Gerrit-PatchSet: 17 Gerrit-Owner: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[main]: device/device_util: Use const qualifier
by Shuo Liu (Code Review) 26 Mar '24

26 Mar '24

Attention is currently required from: Christian Walter, Johnny Lin, Jonathan Zhang, Jérémy Compostella, Lean Sheng Tan, Patrick Rudolph, Tim Chu. Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81275?usp=email ) Change subject: device/device_util: Use const qualifier ...................................................................... Patch Set 9: (1 comment) File src/soc/intel/xeon_sp/include/soc/chip_common.h: https://review.coreboot.org/c/coreboot/+/81275/comment/c84e3bdd_33e1f287 : PS3, Line 79: int iio_pci_domain_stack_from_dev(struct device *dev); > I made an update and hope this is okay. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/81275?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iac04fe6931a43070f6638b399adbff2ce64829c9 Gerrit-Change-Number: 81275 Gerrit-PatchSet: 9 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Tue, 26 Mar 2024 10:09:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com> Gerrit-MessageType: comment

1 0

[S] Change in coreboot[main]: device/device_util: Use const qualifier
by Shuo Liu (Code Review) 26 Mar '24

26 Mar '24

Attention is currently required from: Christian Walter, Johnny Lin, Jonathan Zhang, Jérémy Compostella, Lean Sheng Tan, Patrick Rudolph, Tim Chu. Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81275?usp=email ) Change subject: device/device_util: Use const qualifier ...................................................................... Patch Set 9: (1 comment) File src/soc/intel/xeon_sp/include/soc/chip_common.h: https://review.coreboot.org/c/coreboot/+/81275/comment/5b7ba65c_224865c8 : PS3, Line 79: int iio_pci_domain_stack_from_dev(struct device *dev); > for these 2, suppose we also need to add const. I made an update and hope this is okay. -- To view, visit https://review.coreboot.org/c/coreboot/+/81275?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iac04fe6931a43070f6638b399adbff2ce64829c9 Gerrit-Change-Number: 81275 Gerrit-PatchSet: 9 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Tue, 26 Mar 2024 10:09:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com> Gerrit-MessageType: comment

1 0

[M] Change in coreboot[main]: soc/intel/xeon_sp: Add device to proximity domain map utils
by Shuo Liu (Code Review) 26 Mar '24

26 Mar '24

Attention is currently required from: Arthur Heymans, Chen, Gang C, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Shuo Liu, Tim Chu, Ziang Wang. Hello Arthur Heymans, Chen, Gang C, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Tim Chu, Ziang Wang, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81440?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/intel/xeon_sp: Add device to proximity domain map utils ...................................................................... soc/intel/xeon_sp: Add device to proximity domain map utils In NUMA architecture, all devices (cpu, memory and PCI device) belong to specific proximity domain. Add utils to map device instance to their proximity domain. Proximity domain ID is the index assigned at the creation of proximity domains. There is no hard relationship between proximity domain ID and the device identities (e.g. socket ID). Hence we need the map utils to explicitly link them. For now the SNC config isn't taken into account. TEST=intel/archercity CRB Change-Id: Icd14a98823491ccfc38473e44a26dddfbbcaa7c0 Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> Signed-off-by: Ziang Wang <ziang.wang(a)intel.com> Signed-off-by: Gang Chen <gang.c.chen(a)intel.com> --- M src/soc/intel/xeon_sp/include/soc/numa.h M src/soc/intel/xeon_sp/numa.c M src/soc/intel/xeon_sp/spr/soc_acpi.c M src/soc/intel/xeon_sp/uncore_acpi.c 4 files changed, 47 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/81440/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81440?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icd14a98823491ccfc38473e44a26dddfbbcaa7c0 Gerrit-Change-Number: 81440 Gerrit-PatchSet: 2 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Ziang Wang <ziang.wang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Ziang Wang <ziang.wang(a)intel.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit March 2024