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[M] Change in coreboot[main]: mb/amd/birman_plus: Update glinda DXIO descriptors per schematics
by Anand Vaikar (Code Review) 04 Mar '24

04 Mar '24

Attention is currently required from: Felix Held, Fred Reitberger, Martin L Roth. Hello Felix Held, Fred Reitberger, Martin L Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81036?usp=email to look at the new patch set (#2). Change subject: mb/amd/birman_plus: Update glinda DXIO descriptors per schematics ...................................................................... mb/amd/birman_plus: Update glinda DXIO descriptors per schematics glinda soc DXIO descriptors are updated for Birman+ mainboard Change-Id: If22e57fc57b4824550f2dfa8b843a7809c85dbb6 Signed-off-by: Anand Vaikar <a.vaikar2021(a)gmail.com> --- M src/mainboard/amd/birman_plus/port_descriptors_glinda.c 1 file changed, 103 insertions(+), 49 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/81036/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81036?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If22e57fc57b4824550f2dfa8b843a7809c85dbb6 Gerrit-Change-Number: 81036 Gerrit-PatchSet: 2 Gerrit-Owner: Anand Vaikar <a.vaikar2021(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[main]: mb/amd/birman_plus: Update glinda DXIO descriptors per schematics
by Anand Vaikar (Code Review) 04 Mar '24

04 Mar '24

Anand Vaikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81036?usp=email ) Change subject: mb/amd/birman_plus: Update glinda DXIO descriptors per schematics ...................................................................... mb/amd/birman_plus: Update glinda DXIO descriptors per schematics glinda soc DXIO descriptors are updated for Birman+ mainboard Signed-off-by: Anand Vaikar <a.vaikar2021(a)gmail.com> Change-Id: If22e57fc57b4824550f2dfa8b843a7809c85dbb6 Signed-off-by: Anand Vaikar <a.vaikar2021(a)gmail.com> --- M src/mainboard/amd/birman_plus/port_descriptors_glinda.c 1 file changed, 103 insertions(+), 49 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/81036/1 diff --git a/src/mainboard/amd/birman_plus/port_descriptors_glinda.c b/src/mainboard/amd/birman_plus/port_descriptors_glinda.c index d9bb7d5..ae6f668 100644 --- a/src/mainboard/amd/birman_plus/port_descriptors_glinda.c +++ b/src/mainboard/amd/birman_plus/port_descriptors_glinda.c @@ -6,52 +6,97 @@ #include <soc/platform_descriptors.h> #include <types.h> -/* TODO: Update for birmanplus */ -static const fsp_dxio_descriptor birman_dxio_descriptors[] = { - { - .engine_type = PCIE_ENGINE, - .port_present = true, - .start_logical_lane = 0, - .end_logical_lane = 0, - .device_number = 2, - .function_number = 1, - .link_speed_capability = GEN3, - .turn_off_unused_lanes = true, - .link_aspm = 2, - .link_hotplug = HOTPLUG_ENHANCED, - .clk_req = CLK_REQ3, - }, - { - .engine_type = PCIE_ENGINE, - .port_present = true, - .start_logical_lane = 1, - .end_logical_lane = 1, - .device_number = 2, - .function_number = 2, - .link_speed_capability = GEN3, - .turn_off_unused_lanes = true, - .link_aspm = 2, - .link_hotplug = HOTPLUG_ENHANCED, - .clk_req = CLK_REQ1, - }, - { - .engine_type = PCIE_ENGINE, - .port_present = true, - .start_logical_lane = 2, - .end_logical_lane = 3, - .device_number = 2, - .function_number = 3, - .link_speed_capability = GEN3, - .turn_off_unused_lanes = true, - .link_aspm = 2, - .link_hotplug = HOTPLUG_ENHANCED, - .gpio_group_id = GPIO_27, - .clk_req = CLK_REQ0, - }, -}; +#define glinda_mxm_dxio_descriptor { \ + .engine_type = PCIE_ENGINE, \ + .port_present = CONFIG(ENABLE_EVAL_CARD), \ + .start_logical_lane = 0, \ + .end_logical_lane = 7, \ + .device_number = 3, \ + .function_number = 1, \ + .link_speed_capability = GEN_MAX, \ + .turn_off_unused_lanes = true, \ + .link_aspm = ASPM_L1, \ + .link_hotplug = HOTPLUG_DISABLED, \ + .clk_req = CLK_REQ0, \ + .port_params = {PP_PSPP_AC, 0x144, PP_PSPP_DC, 0x133}, \ +} -static fsp_ddi_descriptor birman_ddi_descriptors[] = { +#define glinda_ssd0_dxio_descriptor { \ + .engine_type = PCIE_ENGINE, \ + .port_present = true, \ + .start_logical_lane = 16, \ + .end_logical_lane = 19, \ + .device_number = 2, \ + .function_number = 1, \ + .link_speed_capability = GEN_MAX, \ + .turn_off_unused_lanes = true, \ + .link_aspm = ASPM_L1, \ + .link_hotplug = HOTPLUG_DISABLED, \ + .clk_req = CLK_REQ2, \ + .port_params = {PP_PSPP_AC, 0x144, PP_PSPP_DC, 0x133}, \ +} + +#define glinda_wlan_dxio_descriptor { \ + .engine_type = PCIE_ENGINE, \ + .port_present = true, \ + .start_logical_lane = 15, \ + .end_logical_lane = 15, \ + .device_number = 2, \ + .function_number = 2, \ + .link_speed_capability = GEN_MAX, \ + .turn_off_unused_lanes = true, \ + .link_aspm = ASPM_L1, \ + .link_hotplug = HOTPLUG_DISABLED, \ + .clk_req = CLK_REQ3, \ +} + +#define glinda_wwan_dxio_descriptor { \ + .engine_type = PCIE_ENGINE, \ + .port_present = true, \ + .start_logical_lane = 12, \ + .end_logical_lane = 12, \ + .device_number = 2, \ + .function_number = 5, \ + .link_speed_capability = GEN_MAX, \ + .turn_off_unused_lanes = true, \ + .link_aspm = ASPM_L1, \ + .link_hotplug = HOTPLUG_DISABLED, \ + .clk_req = CLK_REQ4, \ + .port_params = {PP_PSPP_AC, 0x144, PP_PSPP_DC, 0x133}, \ +} + +#define glinda_gbe_dxio_descriptor { \ + .engine_type = PCIE_ENGINE, \ + .port_present = true, \ + .start_logical_lane = 13, \ + .end_logical_lane = 13, \ + .device_number = 2, \ + .function_number = 4, \ + .link_speed_capability = GEN_MAX, \ + .turn_off_unused_lanes = true, \ + .link_aspm = ASPM_L1, \ + .link_hotplug = HOTPLUG_DISABLED, \ + .clk_req = CLK_REQ6, \ + .port_params = {PP_PSPP_AC, 0x144, PP_PSPP_DC, 0x133}, \ +} + +#define glinda_sd_dxio_descriptor { \ + .engine_type = PCIE_ENGINE, \ + .port_present = true, \ + .start_logical_lane = 14, \ + .end_logical_lane = 14, \ + .device_number = 2, \ + .function_number = 2, \ + .link_speed_capability = GEN_MAX, \ + .turn_off_unused_lanes = true, \ + .link_aspm = ASPM_L1, \ + .link_hotplug = HOTPLUG_DISABLED, \ + .clk_req = CLK_REQ5, \ + .port_params = {PP_PSPP_AC, 0x144, PP_PSPP_DC, 0x133}, \ +} + +static fsp_ddi_descriptor birmanplus_glinda_ddi_descriptors[] = { { /* DDI0 - eDP */ .connector_type = DDI_EDP, .aux_index = DDI_AUX1, @@ -121,10 +166,19 @@ const fsp_dxio_descriptor **dxio_descs, size_t *dxio_num, const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num) { - birman_ddi_descriptors[1].connector_type = get_ddi1_type(); + birmanplus_glinda_ddi_descriptors[1].connector_type = get_ddi1_type(); - *dxio_descs = birman_dxio_descriptors; - *dxio_num = ARRAY_SIZE(birman_dxio_descriptors); - *ddi_descs = birman_ddi_descriptors; - *ddi_num = ARRAY_SIZE(birman_ddi_descriptors); + static const fsp_dxio_descriptor birmanplus_glinda_dxio_descriptors[] = { + glinda_mxm_dxio_descriptor, + glinda_ssd0_dxio_descriptor, + glinda_wlan_dxio_descriptor, + glinda_wwan_dxio_descriptor, + glinda_gbe_dxio_descriptor, + glinda_sd_dxio_descriptor, + }; + + *dxio_descs = birmanplus_glinda_dxio_descriptors; + *dxio_num = ARRAY_SIZE(birmanplus_glinda_dxio_descriptors); + *ddi_descs = birmanplus_glinda_ddi_descriptors; + *ddi_num = ARRAY_SIZE(birmanplus_glinda_ddi_descriptors); } -- To view, visit https://review.coreboot.org/c/coreboot/+/81036?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If22e57fc57b4824550f2dfa8b843a7809c85dbb6 Gerrit-Change-Number: 81036 Gerrit-PatchSet: 1 Gerrit-Owner: Anand Vaikar <a.vaikar2021(a)gmail.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[main]: mb/amd/birman_plus: Update glinda DXIO descriptors per schematics
by Anand Vaikar (Code Review) 04 Mar '24

04 Mar '24

Attention is currently required from: Anand Vaikar. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81035?usp=email to look at the new patch set (#2). Change subject: mb/amd/birman_plus: Update glinda DXIO descriptors per schematics ...................................................................... mb/amd/birman_plus: Update glinda DXIO descriptors per schematics glinda soc DXIO descriptors are updated for Birman+ mainboard Signed-off-by: Anand Vaikar <a.vaikar2021(a)gmail.com> Change-Id: If22e57fc57b4824550f2dfa8b843a7809c85dbb6 Signed-off-by: Anand Vaikar <a.vaikar2021(a)gmail.com> --- M src/mainboard/amd/birman_plus/port_descriptors_glinda.c 1 file changed, 183 insertions(+), 42 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/81035/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81035?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If22e57fc57b4824550f2dfa8b843a7809c85dbb6 Gerrit-Change-Number: 81035 Gerrit-PatchSet: 2 Gerrit-Owner: Anand Vaikar <a.vaikar2021(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Anand Vaikar <a.vaikar2021(a)gmail.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[main]: mb/amd/birman_plus: Update DXIO descriptors per schematics
by Anand Vaikar (Code Review) 04 Mar '24

04 Mar '24

Anand Vaikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81035?usp=email ) Change subject: mb/amd/birman_plus: Update DXIO descriptors per schematics ...................................................................... mb/amd/birman_plus: Update DXIO descriptors per schematics glinda soc descriptors are updated for birmanplus mainboard Signed-off-by: Anand Vaikar <a.vaikar2021(a)gmail.com> Change-Id: If22e57fc57b4824550f2dfa8b843a7809c85dbb6 --- M src/mainboard/amd/birman_plus/port_descriptors_glinda.c 1 file changed, 183 insertions(+), 42 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/81035/1 diff --git a/src/mainboard/amd/birman_plus/port_descriptors_glinda.c b/src/mainboard/amd/birman_plus/port_descriptors_glinda.c index d9bb7d5..220d792 100644 --- a/src/mainboard/amd/birman_plus/port_descriptors_glinda.c +++ b/src/mainboard/amd/birman_plus/port_descriptors_glinda.c @@ -6,52 +6,184 @@ #include <soc/platform_descriptors.h> #include <types.h> -/* TODO: Update for birmanplus */ -static const fsp_dxio_descriptor birman_dxio_descriptors[] = { +#define glinda_mxm_dxio_descriptor { \ + .engine_type = PCIE_ENGINE, \ + .port_present = CONFIG(ENABLE_EVAL_CARD), \ + .start_logical_lane = 0, \ + .end_logical_lane = 7, \ + .device_number = 3, \ + .function_number = 1, \ + .link_speed_capability = GEN_MAX, \ + .turn_off_unused_lanes = true, \ + .link_aspm = ASPM_L1, \ + .link_hotplug = HOTPLUG_DISABLED, \ + .clk_req = CLK_REQ0, \ + .port_params = {PP_PSPP_AC, 0x144, PP_PSPP_DC, 0x133}, \ +} + +#define glinda_ssd0_dxio_descriptor { \ + .engine_type = PCIE_ENGINE, \ + .port_present = true, \ + .start_logical_lane = 16, \ + .end_logical_lane = 19, \ + .device_number = 2, \ + .function_number = 1, \ + .link_speed_capability = GEN_MAX, \ + .turn_off_unused_lanes = true, \ + .link_aspm = ASPM_L1, \ + .link_hotplug = HOTPLUG_DISABLED, \ + .clk_req = CLK_REQ2, \ + .port_params = {PP_PSPP_AC, 0x144, PP_PSPP_DC, 0x133}, \ +} + +#define glinda_wlan_dxio_descriptor { \ + .engine_type = PCIE_ENGINE, \ + .port_present = true, \ + .start_logical_lane = 15, \ + .end_logical_lane = CONFIG(WLAN_LANE1) ? 14 : 15, \ + .device_number = 2, \ + .function_number = 2, \ + .link_speed_capability = GEN_MAX, \ + .turn_off_unused_lanes = true, \ + .link_aspm = ASPM_L1, \ + .link_hotplug = HOTPLUG_DISABLED, \ + .clk_req = CLK_REQ3, \ +} + +#define glinda_wwan_dxio_descriptor { \ + .engine_type = PCIE_ENGINE, \ + .port_present = true, \ + .start_logical_lane = 12, \ + .end_logical_lane = CONFIG(WWAN_LANE1) ? 13 : 12, \ + .device_number = 2, \ + .function_number = 5, \ + .link_speed_capability = GEN_MAX, \ + .turn_off_unused_lanes = true, \ + .link_aspm = ASPM_L1, \ + .link_hotplug = HOTPLUG_DISABLED, \ + .clk_req = CLK_REQ4, \ + .port_params = {PP_PSPP_AC, 0x144, PP_PSPP_DC, 0x133}, \ +} + +#define glinda_gbe_dxio_descriptor { \ + .engine_type = PCIE_ENGINE, \ + .port_present = CONFIG(GBE_ENABLE), \ + .start_logical_lane = 13, \ + .end_logical_lane = 13, \ + .device_number = 2, \ + .function_number = 4, \ + .link_speed_capability = GEN_MAX, \ + .turn_off_unused_lanes = true, \ + .link_aspm = ASPM_L1, \ + .link_hotplug = HOTPLUG_DISABLED, \ + .clk_req = CLK_REQ6, \ + .port_params = {PP_PSPP_AC, 0x144, PP_PSPP_DC, 0x133}, \ +} + +#define glinda_sd_dxio_descriptor { \ + .engine_type = PCIE_ENGINE, \ + .port_present = CONFIG(SD_CARD_ENABLE), \ + .start_logical_lane = 14, \ + .end_logical_lane = 14, \ + .device_number = 2, \ + .function_number = 2, \ + .link_speed_capability = GEN_MAX, \ + .turn_off_unused_lanes = true, \ + .link_aspm = ASPM_L1, \ + .link_hotplug = HOTPLUG_DISABLED, \ + .clk_req = CLK_REQ5, \ + .port_params = {PP_PSPP_AC, 0x144, PP_PSPP_DC, 0x133}, \ +} +/* +static const fsp_dxio_descriptor birmanplus_dxio_descriptors[] = { { - .engine_type = PCIE_ENGINE, - .port_present = true, - .start_logical_lane = 0, - .end_logical_lane = 0, - .device_number = 2, - .function_number = 1, - .link_speed_capability = GEN3, - .turn_off_unused_lanes = true, - .link_aspm = 2, - .link_hotplug = HOTPLUG_ENHANCED, - .clk_req = CLK_REQ3, + .engine_type = PCIE_ENGINE, \ + .port_present = CONFIG(ENABLE_EVAL_CARD), \ + .start_logical_lane = 0, \ + .end_logical_lane = 7, \ + .device_number = 3, \ + .function_number = 1, \ + .link_speed_capability = GEN_MAX, \ + .turn_off_unused_lanes = true, \ + .link_aspm = ASPM_L1, \ + .link_hotplug = HOTPLUG_DISABLED, \ + .clk_req = CLK_REQ0, \ + .port_params = {PP_PSPP_AC, 0x144, PP_PSPP_DC, 0x133}, }, { - .engine_type = PCIE_ENGINE, - .port_present = true, - .start_logical_lane = 1, - .end_logical_lane = 1, - .device_number = 2, - .function_number = 2, - .link_speed_capability = GEN3, - .turn_off_unused_lanes = true, - .link_aspm = 2, - .link_hotplug = HOTPLUG_ENHANCED, - .clk_req = CLK_REQ1, + .engine_type = PCIE_ENGINE, \ + .port_present = true, \ + .start_logical_lane = 16, \ + .end_logical_lane = 19, \ + .device_number = 2, \ + .function_number = 1, \ + .link_speed_capability = GEN_MAX, \ + .turn_off_unused_lanes = true, \ + .link_aspm = ASPM_L1, \ + .link_hotplug = HOTPLUG_DISABLED, \ + .clk_req = CLK_REQ2, \ + .port_params = {PP_PSPP_AC, 0x144, PP_PSPP_DC, 0x133}, \ }, { - .engine_type = PCIE_ENGINE, - .port_present = true, - .start_logical_lane = 2, - .end_logical_lane = 3, - .device_number = 2, - .function_number = 3, - .link_speed_capability = GEN3, - .turn_off_unused_lanes = true, - .link_aspm = 2, - .link_hotplug = HOTPLUG_ENHANCED, - .gpio_group_id = GPIO_27, - .clk_req = CLK_REQ0, + .engine_type = PCIE_ENGINE, \ + .port_present = true, \ + .start_logical_lane = 15, \ + .end_logical_lane = CONFIG(WLAN_LANE1) ? 14 : 15, \ + .device_number = 2, \ + .function_number = 2, \ + .link_speed_capability = GEN_MAX, \ + .turn_off_unused_lanes = true, \ + .link_aspm = ASPM_L1, \ + .link_hotplug = HOTPLUG_DISABLED, \ + .clk_req = CLK_REQ3, + }, + { + .engine_type = PCIE_ENGINE, \ + .port_present = true, \ + .start_logical_lane = 12, \ + .end_logical_lane = CONFIG(WWAN_LANE1) ? 13 : 12, \ + .device_number = 2, \ + .function_number = 5, \ + .link_speed_capability = GEN_MAX, \ + .turn_off_unused_lanes = true, \ + .link_aspm = ASPM_L1, \ + .link_hotplug = HOTPLUG_DISABLED, \ + .clk_req = CLK_REQ4, \ + .port_params = {PP_PSPP_AC, 0x144, PP_PSPP_DC, 0x133}, \ + }, + { + .engine_type = PCIE_ENGINE, \ + .port_present = CONFIG(GBE_ENABLE), \ + .start_logical_lane = 13, \ + .end_logical_lane = 13, \ + .device_number = 2, \ + .function_number = 4, \ + .link_speed_capability = GEN_MAX, \ + .turn_off_unused_lanes = true, \ + .link_aspm = ASPM_L1, \ + .link_hotplug = HOTPLUG_DISABLED, \ + .clk_req = CLK_REQ6, \ + .port_params = {PP_PSPP_AC, 0x144, PP_PSPP_DC, 0x133}, \ + }, + { + .engine_type = PCIE_ENGINE, \ + .port_present = CONFIG(SD_CARD_ENABLE), \ + .start_logical_lane = 14, \ + .end_logical_lane = 14, \ + .device_number = 2, \ + .function_number = 2, \ + .link_speed_capability = GEN_MAX, \ + .turn_off_unused_lanes = true, \ + .link_aspm = ASPM_L1, \ + .link_hotplug = HOTPLUG_DISABLED, \ + .clk_req = CLK_REQ5, \ + .port_params = {PP_PSPP_AC, 0x144, PP_PSPP_DC, 0x133}, \ }, }; +*/ -static fsp_ddi_descriptor birman_ddi_descriptors[] = { +static fsp_ddi_descriptor birmanplus_glinda_ddi_descriptors[] = { { /* DDI0 - eDP */ .connector_type = DDI_EDP, .aux_index = DDI_AUX1, @@ -121,10 +253,19 @@ const fsp_dxio_descriptor **dxio_descs, size_t *dxio_num, const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num) { - birman_ddi_descriptors[1].connector_type = get_ddi1_type(); + birmanplus_glinda_ddi_descriptors[1].connector_type = get_ddi1_type(); - *dxio_descs = birman_dxio_descriptors; - *dxio_num = ARRAY_SIZE(birman_dxio_descriptors); - *ddi_descs = birman_ddi_descriptors; - *ddi_num = ARRAY_SIZE(birman_ddi_descriptors); + static const fsp_dxio_descriptor birmanplus_glinda_dxio_descriptors[] = { + glinda_mxm_dxio_descriptor, + glinda_ssd0_dxio_descriptor, + glinda_wlan_dxio_descriptor, + glinda_wwan_dxio_descriptor, + glinda_gbe_dxio_descriptor, + glinda_sd_dxio_descriptor, + }; + + *dxio_descs = birmanplus_glinda_dxio_descriptors; + *dxio_num = ARRAY_SIZE(birmanplus_glinda_dxio_descriptors); + *ddi_descs = birmanplus_glinda_ddi_descriptors; + *ddi_num = ARRAY_SIZE(birmanplus_glinda_ddi_descriptors); } -- To view, visit https://review.coreboot.org/c/coreboot/+/81035?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If22e57fc57b4824550f2dfa8b843a7809c85dbb6 Gerrit-Change-Number: 81035 Gerrit-PatchSet: 1 Gerrit-Owner: Anand Vaikar <a.vaikar2021(a)gmail.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: soc/intel/meteorlake: Remove SOC_INTEL_GFX_MBUS_JOIN config
by Subrata Banik (Code Review) 04 Mar '24

04 Mar '24

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81034?usp=email ) Change subject: soc/intel/meteorlake: Remove SOC_INTEL_GFX_MBUS_JOIN config ...................................................................... soc/intel/meteorlake: Remove SOC_INTEL_GFX_MBUS_JOIN config This patch removes the SOC_INTEL_GFX_MBUS_JOIN configuration option. Support for fast modeset joining has been added to the mainline i915 kernel driver (https://patchwork.freedesktop.org/series/130480/), making this coreboot-specific workaround unnecessary. BUG=b:291885733 TEST=Successful build and boot of google/screebo with single and dual displays, no redundant boot splash. Change-Id: Ifb0416df53a453ce16815f9fd52ec6b53fade5e2 Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/soc/intel/meteorlake/Kconfig 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/81034/1 diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig index 43bb25e..74f7658 100644 --- a/src/soc/intel/meteorlake/Kconfig +++ b/src/soc/intel/meteorlake/Kconfig @@ -94,7 +94,6 @@ select SOC_INTEL_CSE_SEND_EOP_LATE if !MAINBOARD_HAS_CHROMEOS select SOC_INTEL_CSE_SET_EOP select SOC_INTEL_IOE_DIE_SUPPORT - select SOC_INTEL_GFX_MBUS_JOIN if MAINBOARD_HAS_CHROMEOS && BMP_LOGO select SOC_INTEL_GFX_NON_PREFETCHABLE_MMIO select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION select SSE2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81034?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifb0416df53a453ce16815f9fd52ec6b53fade5e2 Gerrit-Change-Number: 81034 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[main]: mb/google/brya/var/xol: Add VGPIO configurations for CPU PCIe RP
by SH Kim (Code Review) 04 Mar '24

04 Mar '24

Attention is currently required from: Dinesh Gehlot, Kapil Porwal, Nick Vaccaro, Subrata Banik. SH Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81033?usp=email ) Change subject: mb/google/brya/var/xol: Add VGPIO configurations for CPU PCIe RP ...................................................................... Patch Set 1: (2 comments) File src/mainboard/google/brya/variants/xol/gpio.c: https://review.coreboot.org/c/coreboot/+/81033/comment/300b2d55_1a5171a9 : PS1, Line 197: /*Add virtual GPIOs for CPU PCIe RP*/ > nit: […] I just copied this GPIO group from https://review.coreboot.org/c/coreboot/+/57875. I was able to get a hint from this comment, how about keep it? https://review.coreboot.org/c/coreboot/+/81033/comment/4d46a478_dbb4865a : PS1, Line 198: PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, PLTRST, NF1), > btw, wondering what was the value before and after your gpio programming. […] I just copied it from https://review.coreboot.org/c/coreboot/+/57875. NVME couldn't work properly without this CL, so the chipset default config should not be native function. I couldn't find the reference for vGPIOs, can you look at the bug - b:200886824? (Can I get access for this bug as well?) -- To view, visit https://review.coreboot.org/c/coreboot/+/81033?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5520dc2a4bf6e788701a774674d223b7e8ad5b44 Gerrit-Change-Number: 81033 Gerrit-PatchSet: 1 Gerrit-Owner: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Mon, 04 Mar 2024 06:49:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: mb/google/brya/var/omniknight: remove Implement touchscreen power seq...
by Derek Huang (Code Review) 04 Mar '24

04 Mar '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Ivan Chen, Jamie Chen, Kapil Porwal, Matt DeVillier, Nick Vaccaro, Paul Menzel. Derek Huang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80769?usp=email ) Change subject: mb/google/brya/var/omniknight: remove Implement touchscreen power sequencing ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/80769?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I66f4a7915f135927fbc0a16254dece202dfc23a2 Gerrit-Change-Number: 80769 Gerrit-PatchSet: 7 Gerrit-Owner: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Ivan Chen <yulunchen(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-CC: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Ivan Chen <yulunchen(a)google.com> Gerrit-Comment-Date: Mon, 04 Mar 2024 06:43:28 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: nb/intel/haswell: make IOMMU a runtime option
by Paul Menzel (Code Review) 04 Mar '24

04 Mar '24

Attention is currently required from: Alexander Couzens, Angel Pons, Leah Rowe. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81016?usp=email ) Change subject: nb/intel/haswell: make IOMMU a runtime option ...................................................................... Patch Set 1: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/81016/comment/3f7f36b3_3b1417dc : PS1, Line 9: When I tested graphics cards on a coreboot port for Dell : OptiPlex 9020 SFF, I could not use a graphics card unless : I set iommu=off on the Linux cmdline. Any idea why? What Linux version is that? https://review.coreboot.org/c/coreboot/+/81016/comment/6500f47b_6e36144a : PS1, Line 9: When I tested graphics cards on a coreboot port for Dell : OptiPlex 9020 SFF, I could not use a graphics card unless : I set iommu=off on the Linux cmdline. : : The current coreboot behaviour is to check whether the CPU : has vt-d support and, if it does, initialise the IOMMU. : : This patch maintains the current behaviour by default, but : allows the user to turn *off* the IOMMU, even if vt-d is : supported by the host CPU. : : If iommu=Disable is specified, the check will not be : performed, and the IOMMU will be left disabled. This option : has been added to all current Haswell boards, though it is : recommended to leave the IOMMU turned on in most setups. : Please try to use as many of the 72 characters per line as possible. -- To view, visit https://review.coreboot.org/c/coreboot/+/81016?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib743bd00a872c7d73cf9711d618811c7778f2ffb Gerrit-Change-Number: 81016 Gerrit-PatchSet: 1 Gerrit-Owner: Leah Rowe <leahleahrowerowe(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Leah Rowe <leahleahrowerowe(a)gmail.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Comment-Date: Mon, 04 Mar 2024 06:33:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: src/acpi: Modify ACPI revision
by Paul Menzel (Code Review) 04 Mar '24

04 Mar '24

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[XS] Change in coreboot[main]: src/acpi: Modify ACPI revision
by Paul Menzel (Code Review) 04 Mar '24

04 Mar '24

Attention is currently required from: Cliff Huang, Felix Singer, Lance Zhao, Tim Wawrzynczak, minyu li. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80781?usp=email ) Change subject: src/acpi: Modify ACPI revision ...................................................................... Patch Set 1: (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/80781/comment/001b8932_79ce01c8 : PS1, Line 2: E-wells <li.minyu(a)h3c.com> Please replace E-wells by your name. git config --global user.name "Your name" git commit --author="Your name <li.minyu(a)h3c.com>" --amend -s https://review.coreboot.org/c/coreboot/+/80781/comment/48e27d11_d554e5de : PS1, Line 7: src/acpi: Modify ACPI revision Please use: > acpi: Increase ACPI revision from 6.0 to 6.4 https://review.coreboot.org/c/coreboot/+/80781/comment/6d286a33_3442dfbf : PS1, Line 9: Modify ACPI revision from 6.0 to 6.4 > The ACPI PROCESSOR_OP has been deprecated in ACPI 6.0 and dropped in ACPI 6.4. […] Does the coreboot code need to be adapted? ``` $ git grep PROCESSOR_OP src/acpi/acpigen.c: acpigen_emit_ext_op(PROCESSOR_OP); src/include/acpi/acpigen.h: PROCESSOR_OP = 0x83, src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/AcpiAml.h:#define AML_EXT_PROCESSOR_OP 0x83 src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/IndustryStandard/AcpiAml.h:#define AML_EXT_PROCESSOR_OP 0x83 src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/AcpiAml.h:#define AML_EXT_PROCESSOR_OP 0x83 ``` https://review.coreboot.org/c/coreboot/+/80781/comment/60d74ef4_b53b4e16 : PS1, Line 12: Signed-off-by: liminyu <li.minyu(a)h3c.com> Ditto. -- To view, visit https://review.coreboot.org/c/coreboot/+/80781?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I77b978f07b296e55e67d4de5e981bd48fd28eb03 Gerrit-Change-Number: 80781 Gerrit-PatchSet: 1 Gerrit-Owner: minyu li <li.minyu(a)h3c.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: minyu li <li.minyu(a)h3c.com> Gerrit-Comment-Date: Mon, 04 Mar 2024 06:27:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Comment-In-Reply-To: minyu li <li.minyu(a)h3c.com> Gerrit-MessageType: comment

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