coreboot-gerrit March 2024

coreboot-gerrit@coreboot.org

1 participants
3668 discussions

[M] Change in coreboot[main]: soc/intel/xeon_sp: Add ACPI names
by Patrick Rudolph (Code Review) 04 Mar '24

04 Mar '24

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Lean Sheng Tan, Patrick Rudolph, Tim Chu. Hello Arthur Heymans, Christian Walter, Johnny Lin, Lean Sheng Tan, Shuo Liu, Tim Chu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/80792?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Code-Review+2 by Arthur Heymans, Verified+1 by build bot (Jenkins) The change is no longer submittable: Code-Review and Verified are unsatisfied now. Change subject: soc/intel/xeon_sp: Add ACPI names ...................................................................... soc/intel/xeon_sp: Add ACPI names Set the unused 'name' property of the domain device and store the ACPI name. Every IIO stack can have multiple domain devices, each owning a subset of the available bus range within the stack. The name will be used in future changes to generate ACPI names in SSDT code generation. It can also be used to identify the domain type by looking at the first two characters of the name. Change-Id: Ic4cc81d198fb88300394055682a3954bf22db570 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/intel/xeon_sp/acpi.c M src/soc/intel/xeon_sp/chip_common.c M src/soc/intel/xeon_sp/cpx/chip.c M src/soc/intel/xeon_sp/include/soc/acpi.h M src/soc/intel/xeon_sp/include/soc/chip_common.h M src/soc/intel/xeon_sp/skx/chip.c M src/soc/intel/xeon_sp/spr/chip.c M src/soc/intel/xeon_sp/spr/ioat.c 8 files changed, 85 insertions(+), 39 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/80792/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/80792?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic4cc81d198fb88300394055682a3954bf22db570 Gerrit-Change-Number: 80792 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: soc/intel/cmn/cse: Deprecate CONFIG_SOC_INTEL_CSE_RW_VERSION
by Subrata Banik (Code Review) 04 Mar '24

04 Mar '24

Attention is currently required from: Arthur Heymans, Kapil Porwal, Nick Vaccaro, Werner Zeh. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80924?usp=email ) Change subject: soc/intel/cmn/cse: Deprecate CONFIG_SOC_INTEL_CSE_RW_VERSION ...................................................................... Patch Set 1: (1 comment) File src/soc/intel/common/block/cse/Kconfig: https://review.coreboot.org/c/coreboot/+/80924/comment/759c9b23_6bce20be : PS1, Line 236: enabling automatic detection > > Is there an option which lets the user to enable it explicitly or is it available implicit with Meteor Lake and newer? > > not sure if you can access this [link](https://chromium-review.googlesource.com/c/chromiumos/overlays/chromi… where for CSE Lite FW update, we select two configs > > ``` > # Management Engine FW update > CONFIG_SOC_INTEL_CSE_RW_UPDATE=y > CONFIG_SOC_INTEL_CSE_RW_VERSION="18.0.5.2107" > ``` > > CONFIG_SOC_INTEL_CSE_RW_VERSION should match with the CSE FW blob otherwise it will cause boot loop with existing method. Now when we can land CB:80923 we don't need to explicitly mention the CSE RW FW version using yet another config. Therefore, we are planning to drop CONFIG_SOC_INTEL_CSE_RW_VERSION from all Meteor Lake device (which is so far the latest Intel SoC). > > Here `automatic` refers to the CB:80923 which parse the CSE partition and retrieve CSE FW version without any static entry like CONFIG_SOC_INTEL_CSE_RW_VERSION any feedback @werner ? -- To view, visit https://review.coreboot.org/c/coreboot/+/80924?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8c3e5c759e4d9a43c3bce3a0c032086f17592a67 Gerrit-Change-Number: 80924 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Mon, 04 Mar 2024 09:56:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: soc/intel/common/block: Add support for watchdog
by Subrata Banik (Code Review) 04 Mar '24

04 Mar '24

Attention is currently required from: Jakub Czapiga, Marek Maślanka, Michał Żygowski. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79909?usp=email ) Change subject: soc/intel/common/block: Add support for watchdog ...................................................................... Patch Set 14: (6 comments) File src/soc/intel/common/block/acpi/acpi.c: https://review.coreboot.org/c/coreboot/+/79909/comment/4c4030db_22e9436d : PS13, Line 396: rightmost_bit_offset > The only thing that comes to mind to make the name more descriptive is to change it to `find_rightmost_set_bit_offset` can you see if `__builtin_ctzll` is helpful for ur case? without need to implement find_rightmost_set_bit_offset? File src/soc/intel/common/block/acpi/acpi.c: https://review.coreboot.org/c/coreboot/+/79909/comment/494734dd_675e6f2e : PS14, Line 408: tcobase are we okay to go forward if tcobase is not even programmed ? like zero ? https://review.coreboot.org/c/coreboot/+/79909/comment/01ae329d_4b1632a9 : PS14, Line 423: tcobase same https://review.coreboot.org/c/coreboot/+/79909/comment/ec5b7dd3_c422ca80 : PS14, Line 430: 0x01 can we have a macro ? https://review.coreboot.org/c/coreboot/+/79909/comment/9b3b470e_102b7ea0 : PS14, Line 469: acpi_soc_fill_wdat do u have a caller of this function implemented already ? https://review.coreboot.org/c/coreboot/+/79909/comment/fad910dc_4c6ae3ba : PS14, Line 487: if (tcobase == 0) { : wdat->flags = ACPI_WDAT_FLAG_DISABLED; : return current; : } shouldn't we return this at line 474? -- To view, visit https://review.coreboot.org/c/coreboot/+/79909?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iaf7971f8407920a553fd91d2ed04193c882e08f1 Gerrit-Change-Number: 79909 Gerrit-PatchSet: 14 Gerrit-Owner: Marek Maślanka <mmaslanka(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Marek Maślanka <mmaslanka(a)google.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Comment-Date: Mon, 04 Mar 2024 09:53:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Marek Maślanka <mmaslanka(a)google.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: mb/amd/birman_plus: Update glinda DXIO descriptors per schematics
by Paul Menzel (Code Review) 04 Mar '24

04 Mar '24

Attention is currently required from: Anand Vaikar, Felix Held, Fred Reitberger, Martin L Roth. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81036?usp=email ) Change subject: mb/amd/birman_plus: Update glinda DXIO descriptors per schematics ...................................................................... Patch Set 2: Code-Review+1 (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/81036/comment/0c3ee7ca_3d2f4223 : PS2, Line 7: schematics What revision? https://review.coreboot.org/c/coreboot/+/81036/comment/a1b83172_fa2412da : PS2, Line 9: glinda soc DXIO descriptors are updated for Birman+ mainboard Please give a quick overview in the commit message. https://review.coreboot.org/c/coreboot/+/81036/comment/ca363dff_2a69c806 : PS2, Line 11: One blank line is enough. -- To view, visit https://review.coreboot.org/c/coreboot/+/81036?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If22e57fc57b4824550f2dfa8b843a7809c85dbb6 Gerrit-Change-Number: 81036 Gerrit-PatchSet: 2 Gerrit-Owner: Anand Vaikar <a.vaikar2021(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-CC: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Anand Vaikar <a.vaikar2021(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 04 Mar 2024 09:35:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[L] Change in coreboot[main]: mb/dell: Add OptiPlex 7020/9020 port
by Paul Menzel (Code Review) 04 Mar '24

04 Mar '24

Attention is currently required from: Arthur Heymans, Leah Rowe, Michael Büchler, Máté Kukri, Nicholas Chin, Nico Huber, ilikenwf, nat ✨. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55232?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: mb/dell: Add OptiPlex 7020/9020 port ...................................................................... Patch Set 33: Code-Review+1 (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/55232/comment/35256572_4b0a3dcc : PS33, Line 11: PWN > I don't think the iommu issue is specific to this machine, it might very well affect all of Haswell. […] As the typo is still there, I am removing the *Resolved* check, so nobody accidentally commits this. Patchset: PS33: Great work. Thank you Máté. -- To view, visit https://review.coreboot.org/c/coreboot/+/55232?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie7c7089f443aef9890711c4412209bceb1f1e96a Gerrit-Change-Number: 55232 Gerrit-PatchSet: 33 Gerrit-Owner: Máté Kukri <kukri.mate(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Michael Büchler <michael.buechler(a)posteo.net> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <rudolphpatrick05(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ben Westover <me(a)benthetechguy.net> Gerrit-CC: Leah Rowe <leahleahrowerowe(a)gmail.com> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: ilikenwf <mparnell(a)gmail.com> Gerrit-CC: nat ✨ <nat(a)nekopon.pl> Gerrit-Attention: Máté Kukri <kukri.mate(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: nat ✨ <nat(a)nekopon.pl> Gerrit-Attention: ilikenwf <mparnell(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Leah Rowe <leahleahrowerowe(a)gmail.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Attention: Michael Büchler <michael.buechler(a)posteo.net> Gerrit-Comment-Date: Mon, 04 Mar 2024 09:34:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Máté Kukri <kukri.mate(a)gmail.com> Comment-In-Reply-To: Leah Rowe <leahleahrowerowe(a)gmail.com> Comment-In-Reply-To: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: sb/intel/lynxpoint: Don't generate second SSDT
by Paul Menzel (Code Review) 04 Mar '24

04 Mar '24

Attention is currently required from: Arthur Heymans, Felix Singer. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76129?usp=email ) Change subject: sb/intel/lynxpoint: Don't generate second SSDT ...................................................................... Patch Set 12: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/76129?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie23d5b5b967de162ea9ac60a64bc92d0b3bee08e Gerrit-Change-Number: 76129 Gerrit-PatchSet: 12 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Mon, 04 Mar 2024 09:31:56 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[L] Change in coreboot[main]: mb/erying: Add Erying Polestar G613 Pro (TGL-H)
by Michał Żygowski (Code Review) 04 Mar '24

04 Mar '24

Attention is currently required from: Alicja Michalska. Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80853?usp=email ) Change subject: mb/erying: Add Erying Polestar G613 Pro (TGL-H) ...................................................................... Patch Set 1: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/80853/comment/c79afa2d_abb54554 : PS1, Line 25: even though I force-disabled it, I'm still getting AERs That's because AER is still enabled: `PcieRpAdvancedErrorReporting` Disabling ASPM won't stop AER errors from occurring AFAIK. https://review.coreboot.org/c/coreboot/+/80853/comment/1d8de382_b8eda4c0 : PS1, Line 39: : Likewise, I can't wrap my head around PCI-E AERs I'm getting if I boot : the machine without `pcie_aspm=off` parameter: : - BadTLP : - BadDLLP : - Timeout : - Rollover : : Adjusting LaneEq's didn't change anything, all settings are configured : in (mostly) the same way as they were on stock firmware. Without proper `PcieClkSrcClkReq` settings, the most you can get is ASPM L0s. ASPM L1 requires CLKREQ# signal to get the link back to L0. -- To view, visit https://review.coreboot.org/c/coreboot/+/80853?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iffb9e357da2eb686bdcd9a9837df8a60fa94011e Gerrit-Change-Number: 80853 Gerrit-PatchSet: 1 Gerrit-Owner: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Comment-Date: Mon, 04 Mar 2024 09:27:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: payload/external/edk2: Explicitly define the build arch
by Sean Rhodes (Code Review) 04 Mar '24

04 Mar '24

Attention is currently required from: Benjamin Doron, Lean Sheng Tan, Martin L Roth, Matt DeVillier, Nicholas Sudsgaard, Stefan Reinauer. Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80883?usp=email ) Change subject: payload/external/edk2: Explicitly define the build arch ...................................................................... Patch Set 2: (1 comment) Patchset: PS1: > The directory indeed seems to be the issue: […] Seems they broke it for RISC: https://github.com/tianocore/edk2/commit/11ad164bcea6b0ed3628d595090f84892c… Can coreboot be built with 32-bit/risc? If not, we'll just need to adjust the shimlayer stuff -- To view, visit https://review.coreboot.org/c/coreboot/+/80883?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icd942d0c15a99231d09f9cbdc5eb48333b6aa6e5 Gerrit-Change-Number: 80883 Gerrit-PatchSet: 2 Gerrit-Owner: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Mon, 04 Mar 2024 09:13:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sean Rhodes <sean(a)starlabs.systems> Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com> Comment-In-Reply-To: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/google/oak: Don't build the ChromeEC codebase by default
by Yu-Ping Wu (Code Review) 04 Mar '24

04 Mar '24

Attention is currently required from: Hung-Te Lin, Martin L Roth. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81023?usp=email ) Change subject: mb/google/oak: Don't build the ChromeEC codebase by default ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > but I'm fine ti merge this first. Note that ChromeOS doesn't build elm firmware on ToT anymore (we disabled `bootimage` USE flag for a few boards when implementing the Groot firmware UI due to insufficient flash space), so whatever the problem is, we probably don't need to fix it. -- To view, visit https://review.coreboot.org/c/coreboot/+/81023?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idd4fe45e52dbdd1c8dccf0d2c09d5cf6d61aa839 Gerrit-Change-Number: 81023 Gerrit-PatchSet: 2 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Comment-Date: Mon, 04 Mar 2024 08:59:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Hung-Te Lin <hungte(a)chromium.org> Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/google/oak: Don't build the ChromeEC codebase by default
by Hung-Te Lin (Code Review) 04 Mar '24

04 Mar '24

Attention is currently required from: Martin L Roth. Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81023?usp=email ) Change subject: mb/google/oak: Don't build the ChromeEC codebase by default ...................................................................... Patch Set 2: Code-Review+1 (2 comments) Patchset: PS2: having said PS2: > > emerge-elm -pv chromeos-bootimage […] but I'm fine ti merge this first. -- To view, visit https://review.coreboot.org/c/coreboot/+/81023?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idd4fe45e52dbdd1c8dccf0d2c09d5cf6d61aa839 Gerrit-Change-Number: 81023 Gerrit-PatchSet: 2 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Comment-Date: Mon, 04 Mar 2024 08:53:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Hung-Te Lin <hungte(a)chromium.org> Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com> Gerrit-MessageType: comment

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coreboot-gerrit March 2024