coreboot-gerrit March 2024

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[S] Change in coreboot[main]: soc/intel/xeon_sp: Add utils for VT-d BAR query
by Shuo Liu (Code Review) 04 Mar '24

04 Mar '24

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[S] Change in coreboot[main]: soc/intel/xeon_sp: Add dev_find_all_devices_on_socket
by Shuo Liu (Code Review) 04 Mar '24

04 Mar '24

1 0

[XS] Change in coreboot[main]: soc/intel/xeon_sp: Share numa.c among Xeon-SP platforms
by Shuo Liu (Code Review) 04 Mar '24

04 Mar '24

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[XS] Change in coreboot[main]: soc/intel/xeon_sp: Unshare UDK binding among Xeon-SP platforms
by Shuo Liu (Code Review) 04 Mar '24

04 Mar '24

Attention is currently required from: Arthur Heymans, Christian Walter, Jincheng Li, Johnny Lin, Lean Sheng Tan, Patrick Rudolph, Tim Chu. Hello Jincheng Li, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/81041?usp=email to review the following change. Change subject: soc/intel/xeon_sp: Unshare UDK binding among Xeon-SP platforms ...................................................................... soc/intel/xeon_sp: Unshare UDK binding among Xeon-SP platforms Change-Id: I285549daad87fe1ad6e8a94853e0a92cd5930e04 Signed-off-by: Li, Jincheng <jincheng.li(a)intel.com> --- M src/soc/intel/xeon_sp/Kconfig M src/soc/intel/xeon_sp/cpx/Kconfig M src/soc/intel/xeon_sp/skx/Kconfig M src/soc/intel/xeon_sp/spr/Kconfig 4 files changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/81041/1 diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig index 15d129a..a69d465 100644 --- a/src/soc/intel/xeon_sp/Kconfig +++ b/src/soc/intel/xeon_sp/Kconfig @@ -47,7 +47,6 @@ bool default y select PLATFORM_USES_FSP2_0 - select UDK_202005_BINDING select POSTCAR_STAGE config MAX_SOCKET diff --git a/src/soc/intel/xeon_sp/cpx/Kconfig b/src/soc/intel/xeon_sp/cpx/Kconfig index 1e89f21..ab1e16c 100644 --- a/src/soc/intel/xeon_sp/cpx/Kconfig +++ b/src/soc/intel/xeon_sp/cpx/Kconfig @@ -8,6 +8,7 @@ select NO_FSP_TEMP_RAM_EXIT select HAVE_INTEL_FSP_REPO select USE_COREBOOT_SPECIFIC_FSP_HEADERS + select UDK_202005_BINDING help Intel Cooper Lake-SP support diff --git a/src/soc/intel/xeon_sp/skx/Kconfig b/src/soc/intel/xeon_sp/skx/Kconfig index 52f4e62..4afc6a8 100644 --- a/src/soc/intel/xeon_sp/skx/Kconfig +++ b/src/soc/intel/xeon_sp/skx/Kconfig @@ -6,6 +6,7 @@ select PLATFORM_USES_FSP2_0 select NO_FSP_TEMP_RAM_EXIT select USE_COREBOOT_SPECIFIC_FSP_HEADERS + select UDK_202005_BINDING help Intel Skylake-SP support diff --git a/src/soc/intel/xeon_sp/spr/Kconfig b/src/soc/intel/xeon_sp/spr/Kconfig index ce170ad..c436b0b 100644 --- a/src/soc/intel/xeon_sp/spr/Kconfig +++ b/src/soc/intel/xeon_sp/spr/Kconfig @@ -14,6 +14,7 @@ select XEON_SP_COMMON_BASE select HAVE_IOAT_DOMAINS select USE_COREBOOT_SPECIFIC_FSP_HEADERS + select UDK_202005_BINDING help Intel Sapphire Rapids-SP support -- To view, visit https://review.coreboot.org/c/coreboot/+/81041?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I285549daad87fe1ad6e8a94853e0a92cd5930e04 Gerrit-Change-Number: 81041 Gerrit-PatchSet: 1 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[main]: soc/intel/xeon_sp: Redefine FSP data types for FSP2.4
by Shuo Liu (Code Review) 04 Mar '24

04 Mar '24

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Lean Sheng Tan, Patrick Rudolph, Tim Chu. Shuo Liu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81040?usp=email ) Change subject: soc/intel/xeon_sp: Redefine FSP data types for FSP2.4 ...................................................................... soc/intel/xeon_sp: Redefine FSP data types for FSP2.4 Intel server FSP2.4 introduces UDS_STACK_RES/UDS_SOCKET_RES and retires the usages of STACK_RES/IIO_RESOURCE_INSTANCE. Make redinitions to make Xeon-SP common codes to work for both FSP2.4 before and later. Change-Id: I28c948525cd6d7ac4b9c3fa67e3c99ec637ed38f Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> --- M src/soc/intel/xeon_sp/Makefile.mk M src/soc/intel/xeon_sp/acpi.c M src/soc/intel/xeon_sp/include/soc/chip_common.h A src/soc/intel/xeon_sp/include/soc/fsp_adoption.h D src/soc/intel/xeon_sp/include/soc/fsp_upd.h M src/soc/intel/xeon_sp/include/soc/util.h M src/soc/intel/xeon_sp/uncore_acpi.c 7 files changed, 38 insertions(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/81040/1 diff --git a/src/soc/intel/xeon_sp/Makefile.mk b/src/soc/intel/xeon_sp/Makefile.mk index a732c78..a1c8d79 100644 --- a/src/soc/intel/xeon_sp/Makefile.mk +++ b/src/soc/intel/xeon_sp/Makefile.mk @@ -21,6 +21,6 @@ subdirs-$(CONFIG_SOC_INTEL_XEON_RAS) += ras CPPFLAGS_common += -I$(src)/soc/intel/xeon_sp/include -CPPFLAGS_common += -include $(src)/soc/intel/xeon_sp/include/soc/fsp_upd.h +CPPFLAGS_common += -include $(src)/soc/intel/xeon_sp/include/soc/fsp_adoption.h endif ## XEON_SP_COMMON_BASE diff --git a/src/soc/intel/xeon_sp/acpi.c b/src/soc/intel/xeon_sp/acpi.c index 5eaa762..49a6e8a 100644 --- a/src/soc/intel/xeon_sp/acpi.c +++ b/src/soc/intel/xeon_sp/acpi.c @@ -102,7 +102,7 @@ continue; iio++; for (int stack = 0; stack < MAX_IIO_STACK; ++stack) { - const STACK_RES *ri = + const xSTACK_RES *ri = &hob->PlatformData.IIO_resource[socket].StackRes[stack]; uint32_t ioapic_base = ri->IoApicBase; if (ioapic_base == 0 || ioapic_base == 0xFFFFFFFF) diff --git a/src/soc/intel/xeon_sp/include/soc/chip_common.h b/src/soc/intel/xeon_sp/include/soc/chip_common.h index 847d95a..556e510 100644 --- a/src/soc/intel/xeon_sp/include/soc/chip_common.h +++ b/src/soc/intel/xeon_sp/include/soc/chip_common.h @@ -21,7 +21,7 @@ void iio_pci_domain_scan_bus(struct device *dev); void attach_iio_stacks(struct device *dev); -void soc_create_ioat_domains(union xeon_domain_path path, struct bus *bus, const STACK_RES *sr); +void soc_create_ioat_domains(union xeon_domain_path path, struct bus *bus, const xSTACK_RES *sr); struct device *dev_find_device_on_socket(uint8_t socket, u16 vendor, u16 device); int iio_pci_domain_socket_from_dev(struct device *dev); int iio_pci_domain_stack_from_dev(struct device *dev); diff --git a/src/soc/intel/xeon_sp/include/soc/fsp_adoption.h b/src/soc/intel/xeon_sp/include/soc/fsp_adoption.h new file mode 100644 index 0000000..90940c5 --- /dev/null +++ b/src/soc/intel/xeon_sp/include/soc/fsp_adoption.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef _FSP_UPD_H_ +#define _FSP_UPD_H_ + +/* + * Intel FSPs of XEON server platforms define FSPX_CONFIG + * instead of FSP_X_CONFIG, which is expected by coreboot. + */ +#define FSP_T_CONFIG FSPT_CONFIG +#define FSP_M_CONFIG FSPM_CONFIG +#define FSP_S_CONFIG FSPS_CONFIG + +/* + * Intel server FSP2.4 introduces UDS_STACK_RES/UDS_SOCKET_RES + * and retires the usages of STACK_RES/IIO_RESOURCE_INSTANCE. + * Make below redinitions to make Xeon-SP common codes to work + * for both FSP2.4 before and later. + */ +#if CONFIG(PLATFORM_USES_FSP2_4) +#define xSTACK_RES UDS_STACK_RES +#define xIIO_RESOURCE_INSTANCE UDS_SOCKET_RES +#else +#define xSTACK_RES STACK_RES +#define xIIO_RESOURCE_INSTANCE IIO_RESOURCE_INSTANCE +#endif + +#endif diff --git a/src/soc/intel/xeon_sp/include/soc/fsp_upd.h b/src/soc/intel/xeon_sp/include/soc/fsp_upd.h deleted file mode 100644 index 15ce96f..0000000 --- a/src/soc/intel/xeon_sp/include/soc/fsp_upd.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#ifndef _FSP_UPD_H_ -#define _FSP_UPD_H_ - -/* - * Intel FSPs of XEON server platforms define FSPX_CONFIG - * instead of FSP_X_CONFIG, which is expected by coreboot. - */ -#define FSP_T_CONFIG FSPT_CONFIG -#define FSP_M_CONFIG FSPM_CONFIG -#define FSP_S_CONFIG FSPS_CONFIG - -#endif diff --git a/src/soc/intel/xeon_sp/include/soc/util.h b/src/soc/intel/xeon_sp/include/soc/util.h index b881cb4..556781b 100644 --- a/src/soc/intel/xeon_sp/include/soc/util.h +++ b/src/soc/intel/xeon_sp/include/soc/util.h @@ -27,13 +27,13 @@ struct iiostack_resource { uint8_t no_of_stacks; - STACK_RES res[CONFIG_MAX_SOCKET * MAX_IIO_STACK]; + xSTACK_RES res[CONFIG_MAX_SOCKET * MAX_IIO_STACK]; }; void get_iiostack_info(struct iiostack_resource *info); -bool is_pcie_iio_stack_res(const STACK_RES *res); -bool is_ubox_stack_res(const STACK_RES *res); -bool is_ioat_iio_stack_res(const STACK_RES *res); +bool is_pcie_iio_stack_res(const xSTACK_RES *res); +bool is_ubox_stack_res(const xSTACK_RES *res); +bool is_ioat_iio_stack_res(const xSTACK_RES *res); void bios_done_msr(void *unused); #endif diff --git a/src/soc/intel/xeon_sp/uncore_acpi.c b/src/soc/intel/xeon_sp/uncore_acpi.c index b7c6640..3e86097 100644 --- a/src/soc/intel/xeon_sp/uncore_acpi.c +++ b/src/soc/intel/xeon_sp/uncore_acpi.c @@ -252,7 +252,7 @@ int stack, const IIO_UDS *hob) { unsigned long tmp = current; - const STACK_RES *ri = &hob->PlatformData.IIO_resource[socket].StackRes[stack]; + const xSTACK_RES *ri = &hob->PlatformData.IIO_resource[socket].StackRes[stack]; const uint32_t bus = ri->BusBase; const uint32_t pcie_seg = hob->PlatformData.CpuQpiInfo[socket].PcieSegment; const uint32_t reg_base = ri->VtdBarAddress; @@ -493,7 +493,7 @@ return current; } -static unsigned long xeonsp_create_satc_ioat(unsigned long current, const STACK_RES *ri) +static unsigned long xeonsp_create_satc_ioat(unsigned long current, const xSTACK_RES *ri) { for (int b = ri->BusBase; b <= ri->BusLimit; ++b) { struct device *dev = pcidev_path_on_bus(b, PCI_DEVFN(0, 0)); @@ -525,7 +525,7 @@ if (!soc_cpu_is_enabled(socket)) continue; for (int stack = (MAX_LOGIC_IIO_STACK - 1); stack >= 0; --stack) { - const STACK_RES *ri = &hob->PlatformData.IIO_resource[socket].StackRes[stack]; + const xSTACK_RES *ri = &hob->PlatformData.IIO_resource[socket].StackRes[stack]; // Add the IOAT ATS devices to the SATC if (CONFIG(HAVE_IOAT_DOMAINS) && is_ioat_iio_stack_res(ri)) current = xeonsp_create_satc_ioat(current, ri); -- To view, visit https://review.coreboot.org/c/coreboot/+/81040?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I28c948525cd6d7ac4b9c3fa67e3c99ec637ed38f Gerrit-Change-Number: 81040 Gerrit-PatchSet: 1 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[main]: soc/intel/xeon_sp: Add USE_COREBOOT_SPECIFIC_FSP_HEADERS
by Shuo Liu (Code Review) 04 Mar '24

04 Mar '24

Shuo Liu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81039?usp=email ) Change subject: soc/intel/xeon_sp: Add USE_COREBOOT_SPECIFIC_FSP_HEADERS ...................................................................... soc/intel/xeon_sp: Add USE_COREBOOT_SPECIFIC_FSP_HEADERS For SKX to SPR, there are 2 class of FSP headers. One class is common headers, like <IioUniversalDataHob.h> which is commonly used for all bootloaders, include UEFI and SlimBoot. Another class is coreboot extended FSP headers, like <hob_iiouds.h>. These extended headers are used in coreboot only and maintained in coreboot repo. In GNR and future generations, the generality of FSP headers is improved and these extended headers are not needed. Hence files like <hob_iiouds.h> will not be used. Accordingly, we need to remove the references of these headers from Xeon-SP common codes conditionally. Change-Id: Iefd45e8e0518e88529ae3edcdd8ed08a49f0e475 Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> --- M src/soc/intel/xeon_sp/Kconfig M src/soc/intel/xeon_sp/cpx/Kconfig M src/soc/intel/xeon_sp/include/soc/chip_common.h M src/soc/intel/xeon_sp/include/soc/util.h M src/soc/intel/xeon_sp/skx/Kconfig M src/soc/intel/xeon_sp/spr/Kconfig 6 files changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/81039/1 diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig index 18474ec..15d129a 100644 --- a/src/soc/intel/xeon_sp/Kconfig +++ b/src/soc/intel/xeon_sp/Kconfig @@ -107,4 +107,7 @@ config HAVE_IOAT_DOMAINS bool +config USE_COREBOOT_SPECIFIC_FSP_HEADERS + bool + endif ## SOC_INTEL_XEON_SP diff --git a/src/soc/intel/xeon_sp/cpx/Kconfig b/src/soc/intel/xeon_sp/cpx/Kconfig index ac166c3..1e89f21 100644 --- a/src/soc/intel/xeon_sp/cpx/Kconfig +++ b/src/soc/intel/xeon_sp/cpx/Kconfig @@ -7,6 +7,7 @@ select CACHE_MRC_SETTINGS select NO_FSP_TEMP_RAM_EXIT select HAVE_INTEL_FSP_REPO + select USE_COREBOOT_SPECIFIC_FSP_HEADERS help Intel Cooper Lake-SP support diff --git a/src/soc/intel/xeon_sp/include/soc/chip_common.h b/src/soc/intel/xeon_sp/include/soc/chip_common.h index 3727777..847d95a 100644 --- a/src/soc/intel/xeon_sp/include/soc/chip_common.h +++ b/src/soc/intel/xeon_sp/include/soc/chip_common.h @@ -3,7 +3,9 @@ #ifndef _CHIP_COMMON_H_ #define _CHIP_COMMON_H_ +#if CONFIG(USE_COREBOOT_SPECIFIC_FSP_HEADERS) #include <hob_iiouds.h> +#endif union xeon_domain_path { unsigned int domain_path; diff --git a/src/soc/intel/xeon_sp/include/soc/util.h b/src/soc/intel/xeon_sp/include/soc/util.h index a7d5dac..b881cb4 100644 --- a/src/soc/intel/xeon_sp/include/soc/util.h +++ b/src/soc/intel/xeon_sp/include/soc/util.h @@ -4,7 +4,9 @@ #define _XEON_SP_SOC_UTIL_H_ #include <cpu/x86/msr.h> +#if CONFIG(USE_COREBOOT_SPECIFIC_FSP_HEADERS) #include <hob_iiouds.h> +#endif #define MEM_ADDR_64MB_SHIFT_BITS 26 diff --git a/src/soc/intel/xeon_sp/skx/Kconfig b/src/soc/intel/xeon_sp/skx/Kconfig index 5d84387..52f4e62 100644 --- a/src/soc/intel/xeon_sp/skx/Kconfig +++ b/src/soc/intel/xeon_sp/skx/Kconfig @@ -5,6 +5,7 @@ select XEON_SP_COMMON_BASE select PLATFORM_USES_FSP2_0 select NO_FSP_TEMP_RAM_EXIT + select USE_COREBOOT_SPECIFIC_FSP_HEADERS help Intel Skylake-SP support diff --git a/src/soc/intel/xeon_sp/spr/Kconfig b/src/soc/intel/xeon_sp/spr/Kconfig index bb88bec..ce170ad 100644 --- a/src/soc/intel/xeon_sp/spr/Kconfig +++ b/src/soc/intel/xeon_sp/spr/Kconfig @@ -13,6 +13,7 @@ select SOC_INTEL_CSE_SERVER_SKU select XEON_SP_COMMON_BASE select HAVE_IOAT_DOMAINS + select USE_COREBOOT_SPECIFIC_FSP_HEADERS help Intel Sapphire Rapids-SP support -- To view, visit https://review.coreboot.org/c/coreboot/+/81039?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iefd45e8e0518e88529ae3edcdd8ed08a49f0e475 Gerrit-Change-Number: 81039 Gerrit-PatchSet: 1 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: mb/google/oak: Don't build the ChromeEC codebase by default
by Yidi Lin (Code Review) 04 Mar '24

04 Mar '24

Attention is currently required from: Hung-Te Lin, Martin L Roth. Yidi Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81023?usp=email ) Change subject: mb/google/oak: Don't build the ChromeEC codebase by default ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > In fact even depthcharge can't build for oak/hana/elm today because the driver for ANX7688 is alread […] I have a fix for depthcharge (crrev.com/c/5333904). The problem is that oak/hana/elm only has 4MB flash ROM. It does not have enough space for packing all bmp blocks(introduced by Groot). I can built the image only if the locale is specified. (`LOCALES=en emerge-elm chromeos-bootimage`) -- To view, visit https://review.coreboot.org/c/coreboot/+/81023?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idd4fe45e52dbdd1c8dccf0d2c09d5cf6d61aa839 Gerrit-Change-Number: 81023 Gerrit-PatchSet: 2 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Comment-Date: Mon, 04 Mar 2024 11:05:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Hung-Te Lin <hungte(a)chromium.org> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: arch/x86/Kconfig: Deduplicate SSE2 selection
by Nico Huber (Code Review) 04 Mar '24

04 Mar '24

Attention is currently required from: Elyes Haouas, Felix Singer, Jérémy Compostella. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81021?usp=email ) Change subject: arch/x86/Kconfig: Deduplicate SSE2 selection ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: Sorry, this seems wrong. The individual ARCH_<stage>_<arch> symbols should be individually selectable. Moving the SSE2 select away would remove SSE2 from platforms that don't select the ARCH_ALL_ version (probably currently none, but that's just the current state). -- To view, visit https://review.coreboot.org/c/coreboot/+/81021?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I78c9bb599303d3a249a2434dd38b7629e3f1ca86 Gerrit-Change-Number: 81021 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Mon, 04 Mar 2024 10:48:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: intel/alderlake/Kconfig: select Kconfig MRC_CACHE_USING_MRC_VERSION
by Ronak Kanabar (Code Review) 04 Mar '24

04 Mar '24

Attention is currently required from: Dinesh Gehlot, Kapil Porwal, Nick Vaccaro, Subrata Banik. Ronak Kanabar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81038?usp=email ) Change subject: intel/alderlake/Kconfig: select Kconfig MRC_CACHE_USING_MRC_VERSION ...................................................................... Patch Set 2: (1 comment) File src/soc/intel/alderlake/Kconfig: https://review.coreboot.org/c/coreboot/+/81038/comment/4cb6f281_5e96825c : PS1, Line 113: select MRC_CACHE_USING_MRC_VERSION > i thought ADL-N will also use this ? currently ADL-N use FSP headers from 3rdpart repo. which dose not have FspProducerDataHeader.h file. without that ADL-N can't select this Kconfig. We will select this under SOC_INTEL_ALDERLAKE_PCH_N, once header is available in 3rdpart repo. -- To view, visit https://review.coreboot.org/c/coreboot/+/81038?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icc7e4ecd84a7d2818d54acc6ac5d0592544bb9ce Gerrit-Change-Number: 81038 Gerrit-PatchSet: 2 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Mon, 04 Mar 2024 10:47:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: soc/intel/alderlake: select UDK_202111_BINDING for ADL-N
by Ronak Kanabar (Code Review) 04 Mar '24

04 Mar '24

Attention is currently required from: Dinesh Gehlot, Kapil Porwal, Nick Vaccaro, Subrata Banik. Hello Dinesh Gehlot, Kapil Porwal, Nick Vaccaro, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/80274?usp=email to look at the new patch set (#4). Change subject: soc/intel/alderlake: select UDK_202111_BINDING for ADL-N ...................................................................... soc/intel/alderlake: select UDK_202111_BINDING for ADL-N ADL-N FSP uses 202111 Edk2. select UDK_202111_BINDING Kconfig for ADL-N SoC. This patch select edk2-stable202111 for ADL-N and add CFLAGS -fshort-wchar for ADL-N to fix STATIC_ASSERT while compilation. BUG=b:296433836 TEST=Able to build google/crassk. Change-Id: If277ede4307515035389cd0e9d34c15cc80f278c Signed-off-by: Ronak Kanabar <ronak.kanabar(a)intel.com> --- M src/soc/intel/alderlake/Kconfig M src/soc/intel/alderlake/Makefile.mk 2 files changed, 6 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/80274/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/80274?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If277ede4307515035389cd0e9d34c15cc80f278c Gerrit-Change-Number: 80274 Gerrit-PatchSet: 4 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-MessageType: newpatchset

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coreboot-gerrit March 2024