coreboot-gerrit March 2024

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[S] Change in coreboot[main]: intel/common/block: Use fixed BDF for IBL
by Arthur Heymans (Code Review) 17 Mar '24

17 Mar '24

Attention is currently required from: David Hendricks, Jonathan Zhang, Shuo Liu, TangYiwei. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81321?usp=email ) Change subject: intel/common/block: Use fixed BDF for IBL ...................................................................... Patch Set 1: Code-Review-1 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/81321/comment/aeddf57c_1128ee69 : PS1, Line 9: IBL codes doesn't support bootloader controlled P2SB hidden and : unhidden. What does this mean? Is there even a P2SB? If you cannot use P2SB code because of that you should simply not use this code rather than leaking awkward soc specific details in the common code. -- To view, visit https://review.coreboot.org/c/coreboot/+/81321?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3975cb00e215c4984c63bb8510e8aef7d4cc85a4 Gerrit-Change-Number: 81321 Gerrit-PatchSet: 1 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: TangYiwei Gerrit-Comment-Date: Sun, 17 Mar 2024 13:29:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: mainboard: Introduce BIOS_SIZE
by Arthur Heymans (Code Review) 17 Mar '24

17 Mar '24

Attention is currently required from: Chen, Gang C, David Hendricks, Jincheng Li, Shuo Liu, TangYiwei. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81320?usp=email ) Change subject: mainboard: Introduce BIOS_SIZE ...................................................................... Patch Set 1: (1 comment) File src/mainboard/intel/avenuecity_crb/romstage.c: https://review.coreboot.org/c/coreboot/+/81320/comment/9d3bff9c_b88aea50 : PS1, Line 22: mupd->FspmConfig.BiosRegionBase = BASE_4GB - CONFIG_BIOS_SIZE; : mupd->FspmConfig.BiosRegionSize = CONFIG_BIOS_SIZE; Why in the mainboard dir and not SOC? -- To view, visit https://review.coreboot.org/c/coreboot/+/81320?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5bf8fde9fdc30507ce8eb809f636d02cfa2baf0e Gerrit-Change-Number: 81320 Gerrit-PatchSet: 1 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: TangYiwei Gerrit-Comment-Date: Sun, 17 Mar 2024 13:25:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[main]: mainboard: Introduce BIOS_SIZE
by Arthur Heymans (Code Review) 17 Mar '24

17 Mar '24

Attention is currently required from: Chen, Gang C, David Hendricks, Jincheng Li, Shuo Liu, TangYiwei. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81320?usp=email ) Change subject: mainboard: Introduce BIOS_SIZE ...................................................................... Patch Set 1: Code-Review-2 (1 comment) File src/mainboard/Kconfig: https://review.coreboot.org/c/coreboot/+/81320/comment/a5b08d6b_7fc77143 : PS1, Line 257: config BIOS_SIZE_KB_16384 : bool "16384 KB (16 MB)" : help : Choose this option if your BIOS region is 16384 KB (16 MB). : : config BIOS_SIZE_KB_32768 : bool "32768 KB (32 MB)" : help : Choose this option if your BIOS region is 32768 KB (32 MB). : : config BIOS_SIZE_KB_49512 : bool "49512 KB (48 MB)" : help : Choose this option if your BIOS region is 49512 KB (48 MB). : : # Map the config names to the value : config BIOS_SIZE : hex : default 0x01000000 if BIOS_SIZE_KB_16384 : default 0x02000000 if BIOS_SIZE_KB_32768 : default 0x03000000 if BIOS_SIZE_KB_49512 : default 0x01000000 Drop the Kconfig variables. The FMAP should have all the information needed about the size of the BIOS region. Besides this is intel specific stuff in the generic mainboard dir... -- To view, visit https://review.coreboot.org/c/coreboot/+/81320?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5bf8fde9fdc30507ce8eb809f636d02cfa2baf0e Gerrit-Change-Number: 81320 Gerrit-PatchSet: 1 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: TangYiwei Gerrit-Comment-Date: Sun, 17 Mar 2024 13:24:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[main]: soc/intel/xeon_sp: Redefine data types for FSP2.4 adoption
by Shuo Liu (Code Review) 17 Mar '24

17 Mar '24

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Lean Sheng Tan, Patrick Rudolph, Tim Chu. Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81040?usp=email ) Change subject: soc/intel/xeon_sp: Redefine data types for FSP2.4 adoption ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/81040?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I28c948525cd6d7ac4b9c3fa67e3c99ec637ed38f Gerrit-Change-Number: 81040 Gerrit-PatchSet: 3 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Sun, 17 Mar 2024 13:07:08 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XL] Change in coreboot[main]: vc/intel/fsp/fsp2_0: Add GNR N-1 FSP headers
by Shuo Liu (Code Review) 17 Mar '24

17 Mar '24

Attention is currently required from: Jincheng Li. Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80633?usp=email ) Change subject: vc/intel/fsp/fsp2_0: Add GNR N-1 FSP headers ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/80633?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1c8125dd64e5a9619073c2f17aeade1d33607870 Gerrit-Change-Number: 80633 Gerrit-PatchSet: 3 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Comment-Date: Sun, 17 Mar 2024 13:06:53 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[L] Change in coreboot[main]: mainboard/intel: Add Beechnut City CRB initial support
by Shuo Liu (Code Review) 17 Mar '24

17 Mar '24

Attention is currently required from: Chen, Gang C. Hello Chen, Gang C, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/81322?usp=email to review the following change. Change subject: mainboard/intel: Add Beechnut City CRB initial support ...................................................................... mainboard/intel: Add Beechnut City CRB initial support configs/builder/config.intel.crb.bnc is introduced as the defconfig file for the new board target. Change-Id: I3f6a0fb97b62baadb438fb9f11fdd78fccb3f89a Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> Signed-off-by: Gang Chen <gang.c.chen(a)intel.com> --- A configs/builder/config.intel.crb.bnc A src/mainboard/intel/beechnutcity_crb/Kconfig A src/mainboard/intel/beechnutcity_crb/Kconfig.name A src/mainboard/intel/beechnutcity_crb/Makefile.inc A src/mainboard/intel/beechnutcity_crb/board.fmd A src/mainboard/intel/beechnutcity_crb/board_info.txt A src/mainboard/intel/beechnutcity_crb/bootblock.c A src/mainboard/intel/beechnutcity_crb/devicetree.cb A src/mainboard/intel/beechnutcity_crb/dsdt.asl A src/mainboard/intel/beechnutcity_crb/include/config/iio.h A src/mainboard/intel/beechnutcity_crb/ramstage.c A src/mainboard/intel/beechnutcity_crb/romstage.c 12 files changed, 279 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/81322/1 diff --git a/configs/builder/config.intel.crb.bnc b/configs/builder/config.intel.crb.bnc new file mode 100644 index 0000000..8b82d1c --- /dev/null +++ b/configs/builder/config.intel.crb.bnc @@ -0,0 +1,51 @@ +# Type this in coreboot root directory to get a working .config: +# make defconfig KBUILD_DEFCONFIG=configs/builder/config.intel.crb.bnc + +# +# [RO] Board Configurations +# +CONFIG_VENDOR_INTEL=y +CONFIG_BOARD_INTEL_BEECHNUTCITY_CRB=y + +CONFIG_HAVE_CONFIGURABLE_RAMSTAGE=y +CONFIG_CONFIGURABLE_RAMSTAGE=y + +CONFIG_NO_GFX_INIT=y + +CONFIG_HAVE_IFD_BIN=y +CONFIG_VALIDATE_INTEL_DESCRIPTOR=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_ADD_FSP_BINARIES=y +CONFIG_PAYLOAD_LINUX=y + +CONFIG_UART_FOR_CONSOLE=0 +CONFIG_CONSOLE_SERIAL_115200=y + +# +# [RW] IFWI Ingredients +# +CONFIG_IFD_BIN_PATH="site-local/beechnutcity/descriptor.bin" +CONFIG_CPU_UCODE_BINARIES="site-local/beechnutcity/ucode.mcb" +CONFIG_FSP_T_FILE="site-local/beechnutcity/Server_T.fd" +CONFIG_FSP_M_FILE="site-local/beechnutcity/Server_M.fd" +CONFIG_FSP_S_FILE="site-local/beechnutcity/Server_S.fd" +CONFIG_FSP_HEADER_PATH="src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/" + +CONFIG_PAYLOAD_FILE="site-local/beechnutcity/linuxboot_bzImage" +CONFIG_LINUX_COMMAND_LINE="loglevel=7 earlyprintk=serial,ttyS0,115200 console=ttyS0,115200" + +# +# [RW] Debug Settings +# +CONFIG_CONSOLE_POST=y +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y + +CONFIG_VERIFY_HOBS=y +CONFIG_DISPLAY_MTRRS=y + +CONFIG_DISPLAY_FSP_CALLS_AND_STATUS=y +CONFIG_DISPLAY_FSP_HEADER=y + +CONFIG_HAVE_DEBUG_GPIO=y +CONFIG_DEBUG_GPIO=y diff --git a/src/mainboard/intel/beechnutcity_crb/Kconfig b/src/mainboard/intel/beechnutcity_crb/Kconfig new file mode 100644 index 0000000..f71a1c1 --- /dev/null +++ b/src/mainboard/intel/beechnutcity_crb/Kconfig @@ -0,0 +1,35 @@ +if BOARD_INTEL_BEECHNUTCITY_CRB + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_65536 + select MAINBOARD_USES_FSP2_0 + select SOC_INTEL_GRANITERAPIDS + select SUPERIO_ASPEED_AST2400 + select HAVE_ACPI_TABLES + select IPMI_KCS + select IPMI_KCS_ROMSTAGE + select VPD + select MEMORY_MAPPED_TPM + +config MAINBOARD_DIR + string + default "intel/beechnutcity_crb" + +config MAINBOARD_PART_NUMBER + string + default "Beechnut City CRB" + +config FMDFILE + string + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/board.fmd" + +config ASPEED_SIO_PORT + hex + default 0x2E + +config DIMM_MAX + int + default 1 + +endif diff --git a/src/mainboard/intel/beechnutcity_crb/Kconfig.name b/src/mainboard/intel/beechnutcity_crb/Kconfig.name new file mode 100644 index 0000000..895d160 --- /dev/null +++ b/src/mainboard/intel/beechnutcity_crb/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_INTEL_BEECHNUTCITY_CRB + bool "Beechnut City CRB" diff --git a/src/mainboard/intel/beechnutcity_crb/Makefile.inc b/src/mainboard/intel/beechnutcity_crb/Makefile.inc new file mode 100644 index 0000000..4c7a7be --- /dev/null +++ b/src/mainboard/intel/beechnutcity_crb/Makefile.inc @@ -0,0 +1,6 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += bootblock.c +romstage-y += romstage.c +ramstage-y += ramstage.c +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include diff --git a/src/mainboard/intel/beechnutcity_crb/board.fmd b/src/mainboard/intel/beechnutcity_crb/board.fmd new file mode 100644 index 0000000..435bda3 --- /dev/null +++ b/src/mainboard/intel/beechnutcity_crb/board.fmd @@ -0,0 +1,11 @@ +FLASH@0xfc000000 64M { + SI_ALL@0x0 0x03000000 { + SI_DESC@0x0 0x1000 + } + + RW_MRC_CACHE@0x3000000 0x10000 + FMAP 0x800 + RW_VPD(PRESERVE) 0x4000 + RO_VPD(PRESERVE) 0x4000 + COREBOOT(CBFS) +} diff --git a/src/mainboard/intel/beechnutcity_crb/board_info.txt b/src/mainboard/intel/beechnutcity_crb/board_info.txt new file mode 100644 index 0000000..1de903e --- /dev/null +++ b/src/mainboard/intel/beechnutcity_crb/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Intel +Board name: Beechnut City CRB +Category: eval +ROM protocol: SPI +ROM socketed: y +Flashrom support: y diff --git a/src/mainboard/intel/beechnutcity_crb/bootblock.c b/src/mainboard/intel/beechnutcity_crb/bootblock.c new file mode 100644 index 0000000..966f33d --- /dev/null +++ b/src/mainboard/intel/beechnutcity_crb/bootblock.c @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootblock_common.h> +#include <console/console.h> +#include <device/pci_def.h> +#include <device/pci_ops.h> +#include <intelblocks/lpc_lib.h> +#include <soc/intel/common/block/lpc/lpc_def.h> +#include <soc/pci_devs.h> +#include <superio/aspeed/ast2400/ast2400.h> +#include <superio/aspeed/common/aspeed.h> + +void bootblock_mainboard_early_init(void) +{ + /* Enable eSPI decoding for com1 (0x3f8), com2 (02f8) and superio (0x2e) */ + lpc_io_setup_comm_a_b(); + lpc_enable_fixed_io_ranges(LPC_IOE_SUPERIO_2E_2F); + + if (CONFIG_UART_FOR_CONSOLE == 0) { + /* Setup superio com1 */ + const pnp_devfn_t serial_dev = PNP_DEV(CONFIG_ASPEED_SIO_PORT, AST2400_SUART1); + aspeed_enable_serial(serial_dev, CONFIG_TTYS0_BASE); + } else + die("COMs other than COM1 not supported\n"); +} diff --git a/src/mainboard/intel/beechnutcity_crb/devicetree.cb b/src/mainboard/intel/beechnutcity_crb/devicetree.cb new file mode 100644 index 0000000..b1c75de --- /dev/null +++ b/src/mainboard/intel/beechnutcity_crb/devicetree.cb @@ -0,0 +1,54 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +chip soc/intel/xeon_sp/gnr + + # configure VT-d + register "vtd_support" = "1" + register "x2apic" = "1" + + # configure LPC generic IO decode ranges + # [bits 31..24: reserved] + # [bits 23..18: io decode address mask <7..2>] + # [bits 17..16: reserved] + # [bits 15..2 : io decode dword aligned address <15..2>] + # [bit 1 : reserved] + # [bit 0 : enabled] + register "gen1_dec" = "0x00000CA1" # IPMI KCS + register "gen2_dec" = "0x0" + register "gen3_dec" = "0x0" + register "gen4_dec" = "0x0" + + # configure FSP debug settings + register "serial_io_uart_debug_io_base" = "0x3F8" + + # configure BIOS lockdown + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_FSP, + }" + + # configure devices + device cpu_cluster 0 on end + + device domain 0 on + device pci 00.0 mandatory end # MMAP/VT-d + device gpio 0 alias ibl_gpio_communities on end # GPIO + device mmio 0xfed00000 on end # HEPT + chip superio/common + device pnp 2e.0 on + chip superio/aspeed/ast2400 + register "use_espi" = "1" + device pnp 2e.2 on # SUART1 + io 0x60 = 0x3f8 # PNP_IDX_IO0 + irq 0x70 = 4 # PNP_IDX_IRQ0 + end + end + end + end + chip drivers/ipmi + device pnp ca2.0 on end # BMC KCS + register "wait_for_bmc" = "1" + register "bmc_boot_timeout" = "60" + end + end + +end diff --git a/src/mainboard/intel/beechnutcity_crb/dsdt.asl b/src/mainboard/intel/beechnutcity_crb/dsdt.asl new file mode 100644 index 0000000..246dc99 --- /dev/null +++ b/src/mainboard/intel/beechnutcity_crb/dsdt.asl @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <acpi/acpi.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 // OEM revision +) +{ + #include <acpi/dsdt_top.asl> + #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> + #include <soc/intel/xeon_sp/gnr/acpi/gpe.asl> + #include <soc/intel/xeon_sp/gnr/acpi/platform.asl> + #include <commonlib/include/commonlib/console/post_codes.h> + #include <arch/x86/acpi/post.asl> + #include <arch/x86/acpi/debug.asl> +} diff --git a/src/mainboard/intel/beechnutcity_crb/include/config/iio.h b/src/mainboard/intel/beechnutcity_crb/include/config/iio.h new file mode 100644 index 0000000..8a52f56 --- /dev/null +++ b/src/mainboard/intel/beechnutcity_crb/include/config/iio.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef _BOARD_CONFIG_IIO_H_ +#define _BOARD_CONFIG_IIO_H_ + +#include <soc/iio.h> + +static const iio_pe_config bnc_iio_config_table[] = { + _IIO_PE_CFG_STRUCT_BEGIN(0x0, PE0, IIO_BIFURCATE_x2x2x2x2x8, PE_TYPE_PCIE) { + _IIO_PORT_CFG_STRUCT(0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x4B, 0x1), + _IIO_PORT_CFG_STRUCT(0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0), + _IIO_PORT_CFG_STRUCT(0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0), + _IIO_PORT_CFG_STRUCT(0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0), + _IIO_PORT_CFG_STRUCT(0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x4B, 0x2), + _IIO_PORT_CFG_STRUCT(0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x4B, 0x3), + _IIO_PORT_CFG_STRUCT(0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x4B, 0x4), + _IIO_PORT_CFG_STRUCT(0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x4B, 0x5) + } _IIO_PE_CFG_STRUCT_END, +}; + +#endif /* _BOARD_CONFIG_IIO_H_ */ diff --git a/src/mainboard/intel/beechnutcity_crb/ramstage.c b/src/mainboard/intel/beechnutcity_crb/ramstage.c new file mode 100644 index 0000000..8d31628 --- /dev/null +++ b/src/mainboard/intel/beechnutcity_crb/ramstage.c @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/ramstage.h> + +void mainboard_silicon_init_params(FSPS_UPD *params) +{ + return; +} diff --git a/src/mainboard/intel/beechnutcity_crb/romstage.c b/src/mainboard/intel/beechnutcity_crb/romstage.c new file mode 100644 index 0000000..8e65af4 --- /dev/null +++ b/src/mainboard/intel/beechnutcity_crb/romstage.c @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <string.h> +#include <console/console.h> +#include <drivers/ipmi/ipmi_if.h> +#include <drivers/vpd/vpd.h> +#include <soc/iio.h> +#include <soc/ddr.h> +#include <soc/romstage.h> + +#include "config/iio.h" + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + /* Early connect BMC, e.g. to query configuration parameters */ + if (ipmi_premem_init(CONFIG_BMC_KCS_BASE, 0) == CB_SUCCESS) + printk(BIOS_INFO, "IPMI at 0x%04x initialized successfully\n", + CONFIG_BMC_KCS_BASE); + + /* Set BIOS regeion UPD, otherwise MTRR might set incorrectly during TempRamExit API */ + if (CONFIG_BIOS_SIZE) { + mupd->FspmConfig.BiosRegionBase = BASE_4GB - CONFIG_BIOS_SIZE; + mupd->FspmConfig.BiosRegionSize = CONFIG_BIOS_SIZE; + printk(BIOS_INFO, "BiosRegionBase is set to %x\n", mupd->FspmConfig.BiosRegionBase); + printk(BIOS_INFO, "BiosRegionSize is set to %x\n", mupd->FspmConfig.BiosRegionSize); + } else { + printk(BIOS_ERR, "BIOS_SIZE is not set!!!\n"); + } + + /* IIO init */ + soc_config_iio_pe_ports(mupd, bnc_iio_config_table, + sizeof(bnc_iio_config_table)/sizeof(iio_pe_config)); + +} + +bool mainboard_dimm_slot_exists(uint8_t socket, uint8_t channel, uint8_t dimm) +{ + return false; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/81322?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3f6a0fb97b62baadb438fb9f11fdd78fccb3f89a Gerrit-Change-Number: 81322 Gerrit-PatchSet: 1 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-MessageType: newchange

1 0

[S] Change in coreboot[main]: intel/common/block: Use fixed BDF for IBL
by Shuo Liu (Code Review) 17 Mar '24

17 Mar '24

Shuo Liu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81321?usp=email ) Change subject: intel/common/block: Use fixed BDF for IBL ...................................................................... intel/common/block: Use fixed BDF for IBL IBL codes doesn't support bootloader controlled P2SB hidden and unhidden. Hence, dyanmically read IBL HPET/IOAPIC BDF by bootloader is not supported, because when P2SB is hidden the register access is denied. Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> Change-Id: I3975cb00e215c4984c63bb8510e8aef7d4cc85a4 --- M src/soc/intel/common/block/p2sb/p2sb.c 1 file changed, 26 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/81321/1 diff --git a/src/soc/intel/common/block/p2sb/p2sb.c b/src/soc/intel/common/block/p2sb/p2sb.c index 04318c8..72df827 100644 --- a/src/soc/intel/common/block/p2sb/p2sb.c +++ b/src/soc/intel/common/block/p2sb/p2sb.c @@ -39,16 +39,22 @@ union p2sb_bdf p2sb_get_hpet_bdf(void) { - const bool was_hidden = p2sb_dev_is_hidden(PCH_DEV_P2SB); - if (was_hidden) - p2sb_unhide(); + if (CONFIG(SOC_INTEL_COMMON_IBL_BASE)) { + union p2sb_bdf bdf = {.bus = HPET_BUS_NUM, .dev = HPET_DEV_NUM, .fn = HPET0_FUNC_NUM}; + return bdf; + } else { + const bool was_hidden = p2sb_dev_is_hidden(PCH_DEV_P2SB); - union p2sb_bdf bdf = { .raw = pci_read_config16(PCH_DEV_P2SB, PCH_P2SB_HBDF) }; + if (was_hidden) + p2sb_unhide(); - if (was_hidden) - p2sb_hide(); + union p2sb_bdf bdf = { .raw = pci_read_config16(PCH_DEV_P2SB, PCH_P2SB_HBDF) }; - return bdf; + if (was_hidden) + p2sb_hide(); + + return bdf; + } } void p2sb_set_hpet_bdf(union p2sb_bdf bdf) @@ -58,16 +64,22 @@ union p2sb_bdf p2sb_get_ioapic_bdf(void) { - const bool was_hidden = p2sb_dev_is_hidden(PCH_DEV_P2SB); - if (was_hidden) - p2sb_unhide(); + if (CONFIG(SOC_INTEL_COMMON_IBL_BASE)) { + union p2sb_bdf bdf = {.bus = PCH_IOAPIC_BUS_NUMBER, .dev = PCH_IOAPIC_DEV_NUM, .fn = PCH_IOAPIC_FUNC_NUM}; + return bdf; + } else { + const bool was_hidden = p2sb_dev_is_hidden(PCH_DEV_P2SB); - union p2sb_bdf bdf = { .raw = pci_read_config16(PCH_DEV_P2SB, PCH_P2SB_IBDF) }; + if (was_hidden) + p2sb_unhide(); - if (was_hidden) - p2sb_hide(); + union p2sb_bdf bdf = { .raw = pci_read_config16(PCH_DEV_P2SB, PCH_P2SB_IBDF) }; - return bdf; + if (was_hidden) + p2sb_hide(); + + return bdf; + } } void p2sb_set_ioapic_bdf(union p2sb_bdf bdf) -- To view, visit https://review.coreboot.org/c/coreboot/+/81321?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3975cb00e215c4984c63bb8510e8aef7d4cc85a4 Gerrit-Change-Number: 81321 Gerrit-PatchSet: 1 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-MessageType: newchange

1 0

[S] Change in coreboot[main]: mainboard: Introduce BIOS_SIZE
by Shuo Liu (Code Review) 17 Mar '24

17 Mar '24

1 0

[L] Change in coreboot[main]: mainboard/intel: Add initial support for Avenue City CRB
by Shuo Liu (Code Review) 17 Mar '24

17 Mar '24

Attention is currently required from: Chen, Gang C, Jincheng Li. Hello Chen, Gang C, Jincheng Li, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/81319?usp=email to review the following change. Change subject: mainboard/intel: Add initial support for Avenue City CRB ...................................................................... mainboard/intel: Add initial support for Avenue City CRB configs/builder/config.intel.crb.avc is introduced as the defconfig file for the new board target. Change-Id: I64fdd5388aadf7732f6d3daa600c1455d3672a46 Signed-off-by: Gang Chen <gang.c.chen(a)intel.com> Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> Signed-off-by: Jincheng Li <jincheng.li(a)intel.com> --- A configs/builder/config.intel.crb.avc A src/mainboard/intel/avenuecity_crb/Kconfig A src/mainboard/intel/avenuecity_crb/Kconfig.name A src/mainboard/intel/avenuecity_crb/Makefile.inc A src/mainboard/intel/avenuecity_crb/board.fmd A src/mainboard/intel/avenuecity_crb/board_info.txt A src/mainboard/intel/avenuecity_crb/bootblock.c A src/mainboard/intel/avenuecity_crb/devicetree.cb A src/mainboard/intel/avenuecity_crb/dsdt.asl A src/mainboard/intel/avenuecity_crb/include/config/iio.h A src/mainboard/intel/avenuecity_crb/ramstage.c A src/mainboard/intel/avenuecity_crb/romstage.c 12 files changed, 272 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/81319/1 diff --git a/configs/builder/config.intel.crb.avc b/configs/builder/config.intel.crb.avc new file mode 100644 index 0000000..e3b8f47 --- /dev/null +++ b/configs/builder/config.intel.crb.avc @@ -0,0 +1,51 @@ +# Type this in coreboot root directory to get a working .config: +# make defconfig KBUILD_DEFCONFIG=configs/builder/config.intel.crb.avc + +# +# [RO] Board Configurations +# +CONFIG_VENDOR_INTEL=y +CONFIG_BOARD_INTEL_AVENUECITY_CRB=y + +CONFIG_HAVE_CONFIGURABLE_RAMSTAGE=y +CONFIG_CONFIGURABLE_RAMSTAGE=y + +CONFIG_NO_GFX_INIT=y + +CONFIG_HAVE_IFD_BIN=y +CONFIG_VALIDATE_INTEL_DESCRIPTOR=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_ADD_FSP_BINARIES=y +CONFIG_PAYLOAD_LINUX=y + +CONFIG_UART_FOR_CONSOLE=0 +CONFIG_CONSOLE_SERIAL_115200=y + +# +# [RW] IFWI Ingredients +# +CONFIG_IFD_BIN_PATH="site-local/avenuecity/descriptor.bin" +CONFIG_CPU_UCODE_BINARIES="site-local/avenuecity/ucode.mcb" +CONFIG_FSP_T_FILE="site-local/avenuecity/Server_T.fd" +CONFIG_FSP_M_FILE="site-local/avenuecity/Server_M.fd" +CONFIG_FSP_S_FILE="site-local/avenuecity/Server_S.fd" +CONFIG_FSP_HEADER_PATH="src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/" + +CONFIG_PAYLOAD_FILE="site-local/avenuecity/linuxboot_bzImage" +CONFIG_LINUX_COMMAND_LINE="loglevel=7 earlyprintk=serial,ttyS0,115200 console=ttyS0,115200" + +# +# [RW] Debug Settings +# +CONFIG_CONSOLE_POST=y +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y + +CONFIG_VERIFY_HOBS=y +CONFIG_DISPLAY_MTRRS=y + +CONFIG_DISPLAY_FSP_CALLS_AND_STATUS=y +CONFIG_DISPLAY_FSP_HEADER=y + +CONFIG_HAVE_DEBUG_GPIO=y +CONFIG_DEBUG_GPIO=y diff --git a/src/mainboard/intel/avenuecity_crb/Kconfig b/src/mainboard/intel/avenuecity_crb/Kconfig new file mode 100644 index 0000000..d9163e2 --- /dev/null +++ b/src/mainboard/intel/avenuecity_crb/Kconfig @@ -0,0 +1,39 @@ +if BOARD_INTEL_AVENUECITY_CRB + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_65536 + select MAINBOARD_USES_FSP2_0 + select SOC_INTEL_GRANITERAPIDS + select SUPERIO_ASPEED_AST2400 + select HAVE_ACPI_TABLES + select IPMI_KCS + select IPMI_KCS_ROMSTAGE + select VPD + select MEMORY_MAPPED_TPM + +config CARDBUS_PLUGIN_SUPPORT + bool + default n + +config MAINBOARD_DIR + string + default "intel/avenuecity_crb" + +config MAINBOARD_PART_NUMBER + string + default "Avenue City CRB" + +config FMDFILE + string + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/board.fmd" + +config ASPEED_SIO_PORT + hex + default 0x2E + +config DIMM_MAX + int + default 1 + +endif diff --git a/src/mainboard/intel/avenuecity_crb/Kconfig.name b/src/mainboard/intel/avenuecity_crb/Kconfig.name new file mode 100644 index 0000000..7d5a7fb --- /dev/null +++ b/src/mainboard/intel/avenuecity_crb/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_INTEL_AVENUECITY_CRB + bool "Avenue City CRB" diff --git a/src/mainboard/intel/avenuecity_crb/Makefile.inc b/src/mainboard/intel/avenuecity_crb/Makefile.inc new file mode 100644 index 0000000..4c7a7be --- /dev/null +++ b/src/mainboard/intel/avenuecity_crb/Makefile.inc @@ -0,0 +1,6 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += bootblock.c +romstage-y += romstage.c +ramstage-y += ramstage.c +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include diff --git a/src/mainboard/intel/avenuecity_crb/board.fmd b/src/mainboard/intel/avenuecity_crb/board.fmd new file mode 100644 index 0000000..435bda3 --- /dev/null +++ b/src/mainboard/intel/avenuecity_crb/board.fmd @@ -0,0 +1,11 @@ +FLASH@0xfc000000 64M { + SI_ALL@0x0 0x03000000 { + SI_DESC@0x0 0x1000 + } + + RW_MRC_CACHE@0x3000000 0x10000 + FMAP 0x800 + RW_VPD(PRESERVE) 0x4000 + RO_VPD(PRESERVE) 0x4000 + COREBOOT(CBFS) +} diff --git a/src/mainboard/intel/avenuecity_crb/board_info.txt b/src/mainboard/intel/avenuecity_crb/board_info.txt new file mode 100644 index 0000000..2c502cf --- /dev/null +++ b/src/mainboard/intel/avenuecity_crb/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Intel +Board name: Avenue City CRB +Category: eval +ROM protocol: SPI +ROM socketed: y +Flashrom support: y diff --git a/src/mainboard/intel/avenuecity_crb/bootblock.c b/src/mainboard/intel/avenuecity_crb/bootblock.c new file mode 100644 index 0000000..966f33d --- /dev/null +++ b/src/mainboard/intel/avenuecity_crb/bootblock.c @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootblock_common.h> +#include <console/console.h> +#include <device/pci_def.h> +#include <device/pci_ops.h> +#include <intelblocks/lpc_lib.h> +#include <soc/intel/common/block/lpc/lpc_def.h> +#include <soc/pci_devs.h> +#include <superio/aspeed/ast2400/ast2400.h> +#include <superio/aspeed/common/aspeed.h> + +void bootblock_mainboard_early_init(void) +{ + /* Enable eSPI decoding for com1 (0x3f8), com2 (02f8) and superio (0x2e) */ + lpc_io_setup_comm_a_b(); + lpc_enable_fixed_io_ranges(LPC_IOE_SUPERIO_2E_2F); + + if (CONFIG_UART_FOR_CONSOLE == 0) { + /* Setup superio com1 */ + const pnp_devfn_t serial_dev = PNP_DEV(CONFIG_ASPEED_SIO_PORT, AST2400_SUART1); + aspeed_enable_serial(serial_dev, CONFIG_TTYS0_BASE); + } else + die("COMs other than COM1 not supported\n"); +} diff --git a/src/mainboard/intel/avenuecity_crb/devicetree.cb b/src/mainboard/intel/avenuecity_crb/devicetree.cb new file mode 100644 index 0000000..b1c75de --- /dev/null +++ b/src/mainboard/intel/avenuecity_crb/devicetree.cb @@ -0,0 +1,54 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +chip soc/intel/xeon_sp/gnr + + # configure VT-d + register "vtd_support" = "1" + register "x2apic" = "1" + + # configure LPC generic IO decode ranges + # [bits 31..24: reserved] + # [bits 23..18: io decode address mask <7..2>] + # [bits 17..16: reserved] + # [bits 15..2 : io decode dword aligned address <15..2>] + # [bit 1 : reserved] + # [bit 0 : enabled] + register "gen1_dec" = "0x00000CA1" # IPMI KCS + register "gen2_dec" = "0x0" + register "gen3_dec" = "0x0" + register "gen4_dec" = "0x0" + + # configure FSP debug settings + register "serial_io_uart_debug_io_base" = "0x3F8" + + # configure BIOS lockdown + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_FSP, + }" + + # configure devices + device cpu_cluster 0 on end + + device domain 0 on + device pci 00.0 mandatory end # MMAP/VT-d + device gpio 0 alias ibl_gpio_communities on end # GPIO + device mmio 0xfed00000 on end # HEPT + chip superio/common + device pnp 2e.0 on + chip superio/aspeed/ast2400 + register "use_espi" = "1" + device pnp 2e.2 on # SUART1 + io 0x60 = 0x3f8 # PNP_IDX_IO0 + irq 0x70 = 4 # PNP_IDX_IRQ0 + end + end + end + end + chip drivers/ipmi + device pnp ca2.0 on end # BMC KCS + register "wait_for_bmc" = "1" + register "bmc_boot_timeout" = "60" + end + end + +end diff --git a/src/mainboard/intel/avenuecity_crb/dsdt.asl b/src/mainboard/intel/avenuecity_crb/dsdt.asl new file mode 100644 index 0000000..246dc99 --- /dev/null +++ b/src/mainboard/intel/avenuecity_crb/dsdt.asl @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <acpi/acpi.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 // OEM revision +) +{ + #include <acpi/dsdt_top.asl> + #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> + #include <soc/intel/xeon_sp/gnr/acpi/gpe.asl> + #include <soc/intel/xeon_sp/gnr/acpi/platform.asl> + #include <commonlib/include/commonlib/console/post_codes.h> + #include <arch/x86/acpi/post.asl> + #include <arch/x86/acpi/debug.asl> +} diff --git a/src/mainboard/intel/avenuecity_crb/include/config/iio.h b/src/mainboard/intel/avenuecity_crb/include/config/iio.h new file mode 100644 index 0000000..c8a0f21 --- /dev/null +++ b/src/mainboard/intel/avenuecity_crb/include/config/iio.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef _BOARD_CONFIG_IIO_H_ +#define _BOARD_CONFIG_IIO_H_ + +#include <soc/iio.h> + +static const iio_pe_config avc_iio_config_table[] = { + _IIO_PE_CFG_STRUCT_BEGIN(0x0, PE0, IIO_BIFURCATE_x2x2x2x2x8, PE_TYPE_PCIE) { + _IIO_PORT_CFG_STRUCT(0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x4B, 0x1), + _IIO_PORT_CFG_STRUCT(0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0), + _IIO_PORT_CFG_STRUCT(0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0), + _IIO_PORT_CFG_STRUCT(0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0), + _IIO_PORT_CFG_STRUCT(0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x4B, 0x2), + _IIO_PORT_CFG_STRUCT(0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x4B, 0x3), + _IIO_PORT_CFG_STRUCT(0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x4B, 0x4), + _IIO_PORT_CFG_STRUCT(0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x4B, 0x5) + } _IIO_PE_CFG_STRUCT_END, +}; + +#endif /* _BOARD_CONFIG_IIO_H_ */ diff --git a/src/mainboard/intel/avenuecity_crb/ramstage.c b/src/mainboard/intel/avenuecity_crb/ramstage.c new file mode 100644 index 0000000..8d31628 --- /dev/null +++ b/src/mainboard/intel/avenuecity_crb/ramstage.c @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/ramstage.h> + +void mainboard_silicon_init_params(FSPS_UPD *params) +{ + return; +} diff --git a/src/mainboard/intel/avenuecity_crb/romstage.c b/src/mainboard/intel/avenuecity_crb/romstage.c new file mode 100644 index 0000000..b1a2e28 --- /dev/null +++ b/src/mainboard/intel/avenuecity_crb/romstage.c @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <drivers/ipmi/ipmi_if.h> +#include <drivers/vpd/vpd.h> +#include <soc/ddr.h> +#include <soc/iio.h> +#include <soc/romstage.h> +#include <string.h> + +#include "config/iio.h" + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + /* Early connect BMC, e.g. to query configuration parameters */ + if (ipmi_premem_init(CONFIG_BMC_KCS_BASE, 0) == CB_SUCCESS) + printk(BIOS_INFO, "IPMI at 0x%04x initialized successfully\n", + CONFIG_BMC_KCS_BASE); + + /* IIO init */ + soc_config_iio_pe_ports(mupd, avc_iio_config_table, + sizeof(avc_iio_config_table)/sizeof(iio_pe_config)); +} + +bool mainboard_dimm_slot_exists(uint8_t socket, uint8_t channel, uint8_t dimm) +{ + return false; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/81319?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I64fdd5388aadf7732f6d3daa600c1455d3672a46 Gerrit-Change-Number: 81319 Gerrit-PatchSet: 1 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[main]: soc/intel/xeon_sp/gnr: Add IIO config utils
by Shuo Liu (Code Review) 17 Mar '24

17 Mar '24

Attention is currently required from: Arthur Heymans, Chen, Gang C, Christian Walter, Johnny Lin, Lean Sheng Tan, Patrick Rudolph, Tim Chu. Hello Chen, Gang C, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/81318?usp=email to review the following change. Change subject: soc/intel/xeon_sp/gnr: Add IIO config utils ...................................................................... soc/intel/xeon_sp/gnr: Add IIO config utils GraniteRapids boards should use _IIO_PE_CFG_STRUCT_BEGIN() to define IIO configurations and invokes soc_config_iio() to apply the settings. Change-Id: If7146761db6f73a0c4b0d31b010c0d30a42bf690 Signed-off-by: Gang Chen <gang.c.chen(a)intel.com> Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> --- M src/soc/intel/xeon_sp/gnr/Makefile.inc A src/soc/intel/xeon_sp/gnr/include/soc/iio.h A src/soc/intel/xeon_sp/gnr/soc_iio.c 3 files changed, 176 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/81318/1 diff --git a/src/soc/intel/xeon_sp/gnr/Makefile.inc b/src/soc/intel/xeon_sp/gnr/Makefile.inc index 3d1880d..7246d7e 100644 --- a/src/soc/intel/xeon_sp/gnr/Makefile.inc +++ b/src/soc/intel/xeon_sp/gnr/Makefile.inc @@ -9,7 +9,7 @@ subdirs-y += ../../../../cpu/x86/tsc subdirs-y += ../../../../cpu/intel/microcode -romstage-y += romstage.c soc_util.c soc_pmutil.c +romstage-y += romstage.c soc_util.c soc_pmutil.c soc_iio.c romstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c ramstage-y += chip.c cpu.c soc_util.c ramstage.c soc_acpi.c soc_pmutil.c diff --git a/src/soc/intel/xeon_sp/gnr/include/soc/iio.h b/src/soc/intel/xeon_sp/gnr/include/soc/iio.h new file mode 100644 index 0000000..c7fed3d --- /dev/null +++ b/src/soc/intel/xeon_sp/gnr/include/soc/iio.h @@ -0,0 +1,110 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef _SOC_IIO_H_ +#define _SOC_IIO_H_ + +#include <soc/soc_util.h> + +#include <fsp/util.h> +#include <IioPcieConfigUpd.h> + +typedef struct { + // + // setting ups for PCIE_PORT_ENTERPRISE_CONFIG + // + uint8_t vpp_address; // SMBUS address of IO expander which provides VPP register + uint8_t vpp_port; // Port or bank on IoExpander which provides VPP register + uint8_t vpp_mux_address; // SMBUS address of MUX used to access VPP + uint8_t vpp_mux_channel; // Channel of the MUX used to access VPP + + uint8_t slot_eip:1; // Electromechanical Interlock Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B17) + uint8_t slot_hps:1; // Hot Plug surprise supported - Slot Capabilities (D0-10 / F0 / R0xA4 / B5) + uint8_t slot_pind:1; // Power Indicator Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B4) + uint8_t slot_aind:1; // Attention Inductor Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B3) + uint8_t slot_pctl:1; // Power Controller Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B1) + uint8_t slot_abtn:1; // Attention Button Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B0) + uint8_t slot_rsvd:2; // Reserved + + uint8_t vpp_enabled:1; // If VPP is supported on given port + uint8_t vpp_exp_type:1; // IO Expander type used for VPP (see IIO_VPP_EXPANDER_TYPE for values definitions) + + // + // setting ups for IIO_PCIE_PORT_CONFIG + // + uint8_t slot_implemented:1; + uint8_t reserved:4; + + // + // setting ups for PCIE_PORT_COMMON_CONFIG + // + uint16_t hot_plug:1; // If hotplug is supported on slot connected to this port + uint16_t mrl_sensor_present:1; // If MRL is present on slot connected to this port + uint16_t slot_power_limit_scale:2; // Slot Power Scale for slot connected to this port + uint16_t slot_power_limit_value:12; // Slot Power Value for slot connected to this port + + uint16_t physical_slot_number; // Slot number for slot connected to this port +} iio_port_config; + +typedef struct { + uint8_t socket; + IIO_PACKAGE_PE pe; + IIO_BIFURCATION bifurcation; + uint8_t cxl_support:1; + uint8_t reserved:7; + iio_port_config port_config[MAX_IIO_PORTS_PER_STACK]; +} iio_pe_config; + +/* + * _IIO_PE_CFG_STRUCT_BEGIN(socket, pe, bif, cxl) { + * _IIO_PORT_CFG_STRUCT(vaddr vport vmuxa vmuxc + * slteip slthpss sltpip sltaip sltpcp sltabp + * vppen vppex sltimp hotp mrlsp sltpls sltplv phys) + * _IIO_PORT_CFG_STRUCT(..) + * ... + * _IIO_PORT_CFG_STRUCT(..) //MAX_IIO_PORTS_PER_STACK port configs + * } + */ + +#define PE_TYPE_CXL 1 +#define PE_TYPE_PCIE 0 + +#define _IIO_PE_CFG_STRUCT_BEGIN(s, p, bif, cxl) {\ + .socket = s,\ + .pe = p,\ + .bifurcation = bif,\ + .cxl_support = cxl,\ + .reserved = 0,\ + .port_config = + +#define _IIO_PE_CFG_STRUCT_END } + +#define _IIO_PORT_CFG_STRUCT(vaddr, vport, vmuxa, vmuxc,\ + rsv1, rsv2, rsv3, rsv4,\ + slteip, slthpss, sltpip, sltaip, sltpcp, sltabp,\ + vppen, vppex,\ + rsv5, sltimp, hotp, mrlsp, sltpls, sltplv, phys) {\ + .vpp_address = vaddr,\ + .vpp_port = vport,\ + .vpp_mux_address = vmuxa,\ + .vpp_mux_channel = vmuxc,\ + .slot_eip = slteip,\ + .slot_hps = slthpss,\ + .slot_pind = sltpip,\ + .slot_aind = sltaip,\ + .slot_pctl = sltpcp,\ + .slot_abtn = sltabp,\ + .slot_rsvd = 0,\ + .vpp_enabled = vppen,\ + .vpp_exp_type = vppex,\ + .slot_implemented = sltimp,\ + .reserved = 0,\ + .hot_plug = hotp,\ + .mrl_sensor_present = mrlsp,\ + .slot_power_limit_scale = sltpls,\ + .slot_power_limit_value = sltplv,\ + .physical_slot_number = phys\ +} + +void soc_config_iio_pe_ports(FSPM_UPD *mupd, const iio_pe_config *config_table, int num_entries); + +#endif /* _SOC_IIO_H_ */ diff --git a/src/soc/intel/xeon_sp/gnr/soc_iio.c b/src/soc/intel/xeon_sp/gnr/soc_iio.c new file mode 100644 index 0000000..3954366 --- /dev/null +++ b/src/soc/intel/xeon_sp/gnr/soc_iio.c @@ -0,0 +1,65 @@ + /* SPDX-License-Identifier: GPL-2.0-only */ + +#include <fsp/soc_binding.h> +#include <soc/iio.h> +#include <string.h> + +static IIO_BOARD_SETTINGS_HOB iio_upd_hob; + +void soc_config_iio_pe_ports(FSPM_UPD *mupd, const iio_pe_config *config_table, int num_entries) +{ + int i; + uint8_t socket, pe, port; + + const iio_pe_config *board_pe_config; + const iio_port_config *board_port_config; + + IIO_BOARD_SETTINGS_PER_PE *upd_pe_config; + IIO_BOARD_SETTINGS_PER_PORT *upd_port_config; + + memset(&iio_upd_hob, 0, sizeof(iio_upd_hob)); + + for (i = 0; i < num_entries; i++) { + board_pe_config = &config_table[i]; + socket = board_pe_config->socket; + pe = board_pe_config->pe; + + upd_pe_config = &(iio_upd_hob.Socket[socket].Pe[pe]); + + if ((socket >= MAX_SOCKET) || (pe >= MAX_IIO_PCIE_PER_SOCKET)) + continue; + + for (port = 0; port < MAX_IIO_PORTS_PER_STACK; port++) { + upd_port_config = &(upd_pe_config->Port[port]); + board_port_config = &(board_pe_config->port_config[port]); + + upd_pe_config->Bifurcation = board_pe_config->bifurcation; + upd_pe_config->CxlSupportInUba = board_pe_config->cxl_support; + + upd_port_config->Vpp.Address = board_port_config->vpp_address; + upd_port_config->Vpp.Port = board_port_config->vpp_port; + upd_port_config->Vpp.MuxAddress = board_port_config->vpp_mux_address; + upd_port_config->Vpp.MuxChannel = board_port_config->vpp_mux_channel; + + upd_port_config->Slot.Eip = board_port_config->slot_eip; + upd_port_config->Slot.HotPlugSurprise = board_port_config->slot_hps; + upd_port_config->Slot.PowerInd = board_port_config->slot_pind; + upd_port_config->Slot.AttentionInd = board_port_config->slot_aind; + upd_port_config->Slot.PowerCtrl = board_port_config->slot_pctl; + upd_port_config->Slot.AttentionBtn = board_port_config->slot_abtn; + + upd_port_config->VppEnabled = board_port_config->vpp_enabled; + upd_port_config->VppExpType = board_port_config->vpp_exp_type; + + upd_port_config->SlotImplemented = board_port_config->slot_implemented; + upd_port_config->HotPlug = board_port_config->hot_plug; + upd_port_config->MrlSensorPresent = board_port_config->mrl_sensor_present; + upd_port_config->SlotPowerLimitScale = board_port_config->slot_power_limit_scale; + upd_port_config->SlotPowerLimitValue = board_port_config->slot_power_limit_value; + upd_port_config->PhysicalSlotNumber = board_port_config->physical_slot_number; + } + } + + mupd->FspmConfig.IioBoardSettingsHobPtr = (UINT32)&iio_upd_hob; + mupd->FspmConfig.IioBoardSettingsHobLength = sizeof(iio_upd_hob); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/81318?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If7146761db6f73a0c4b0d31b010c0d30a42bf690 Gerrit-Change-Number: 81318 Gerrit-PatchSet: 1 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newchange

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