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Change subject: vc/amd/opensil: add site-local path for phoenix source
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
Since this depends on site-local being present, and no default is set unless we're using genoa, it might be better to set this in site-local instead of the public coreboot code.
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Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81189?usp=email )
(
1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
)Change subject: vc/amd/opensil: don't use source path when using stub
......................................................................
vc/amd/opensil: don't use source path when using stub
Add a 'depends on' statement so that path/to/opensil/source is only
active when the stub is not built.
Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com>
Change-Id: Ic050ff0fa3f428e6adff3357f476fcd8a88cdf7e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81189
Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de>
Reviewed-by: Varshit Pandya <pandyavarshit(a)gmail.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M src/vendorcode/amd/opensil/Kconfig
1 file changed, 2 insertions(+), 1 deletion(-)
Approvals:
build bot (Jenkins): Verified
Felix Held: Looks good to me, approved
Varshit Pandya: Looks good to me, approved
diff --git a/src/vendorcode/amd/opensil/Kconfig b/src/vendorcode/amd/opensil/Kconfig
index f0a303c..00f373f 100644
--- a/src/vendorcode/amd/opensil/Kconfig
+++ b/src/vendorcode/amd/opensil/Kconfig
@@ -16,7 +16,8 @@
openSIL.
config AMD_OPENSIL_PATH
- string
+ string "Path to openSIL source"
+ depends on !SOC_AMD_OPENSIL_STUB
default "$(top)/src/vendorcode/amd/opensil/genoa_poc/opensil" if SOC_AMD_OPENSIL_GENOA_POC
help
Set to the path of the openSIL directory containing meson.build.
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Change subject: soc/amd/phoenix: make openSIL stub optional
......................................................................
soc/amd/phoenix: make openSIL stub optional
Convert the 'select SOC_AMD_OPENSIL_STUB' statement to a config option
and give it a prompt. This allows for internal development of openSIL
and corresponding coreboot source, and controllable using a defconfig.
Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com>
Change-Id: I2b48e2bbf71cd94ac7ecec13834ba36aa6c241ce
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81188
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
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---
M src/soc/amd/phoenix/Kconfig
1 file changed, 8 insertions(+), 1 deletion(-)
Approvals:
Martin L Roth: Looks good to me, approved
Varshit Pandya: Looks good to me, but someone else must approve
build bot (Jenkins): Verified
Fred Reitberger: Looks good to me, but someone else must approve
diff --git a/src/soc/amd/phoenix/Kconfig b/src/soc/amd/phoenix/Kconfig
index 9d45b76..75777dc 100644
--- a/src/soc/amd/phoenix/Kconfig
+++ b/src/soc/amd/phoenix/Kconfig
@@ -104,7 +104,6 @@
bool
select SOC_AMD_PHOENIX_BASE
select SOC_AMD_OPENSIL
- select SOC_AMD_OPENSIL_STUB
if SOC_AMD_PHOENIX_BASE
@@ -468,3 +467,11 @@
The amount of coreboot-allocated heap and stack usage by the FSP.
endif # SOC_AMD_PHOENIX_FSP
+
+if SOC_AMD_PHOENIX_OPENSIL
+
+config SOC_AMD_OPENSIL_STUB
+ prompt "Build with openSIL stub"
+ default y
+
+endif # SOC_AMD_PHOENIX_OPENSIL
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Change subject: soc/amd/phoenix: make openSIL stub optional
......................................................................
Patch Set 2: Code-Review+2
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Change subject: soc/intel/xeon_sp: Unshare Xeon-SP chip common codes
......................................................................
Patch Set 1:
(1 comment)
File src/soc/intel/xeon_sp/chip_fsp20.c:
https://review.coreboot.org/c/coreboot/+/81312/comment/cd917dc3_7ade4c01 :
PS1, Line 185: #endif //CONFIG(SOC_INTEL_HAS_CXL)
> `adding a line without newline at end of file`
Please fix. This is causing all of the following patches to fail.
Check that files end with a single newline (lint-extended-015-final-newlines): src/soc/intel/xeon_sp/chip_fsp20.c has no final newline.
test failed
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Change subject: Docs/tutorial: Do not install Ada compiler by default
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
Thanks for your comment.
> Can you provide more information about the environment where you still see this?
Sure, please find the details below:
$ lsb_release -a
No LSB modules are available.
Distributor ID: Ubuntu
Description: Ubuntu 22.10
Release: 22.10
Codename: kinetic
$ gcc --version
gcc (Ubuntu 12.3.0-1ubuntu1~22.04) 12.3.0
Copyright (C) 2022 Free Software Foundation, Inc.
This is free software; see the source for copying conditions. There is NO
warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
$ ldd --version
ldd (Ubuntu GLIBC 2.36-0ubuntu4) 2.36
Copyright (C) 2022 Free Software Foundation, Inc.
This is free software; see the source for copying conditions. There is NO
warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
Written by Roland McGrath and Ulrich Drepper.
$ uname -a
Linux ubnri 6.2.0-33-generic #33~22.04.1-Ubuntu SMP PREEMPT_DYNAMIC Thu Sep 7 10:33:52 UTC 2 x86_64 x86_64 x86_64 GNU/Linux
Can you please try the steps on Ubuntu 22.10 with gcc 12.2 and gcc 12.3?
> Correct me if I'm wrong, but isn't apt-get install ... gcc still asking them to up-/downgrade their GCC in case they have a special version installed?
I only included that for consistency with the instructions for other distros (they had gcc listed explicitly). I could remove that in my change if you say so.
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Shuo Liu has uploaded a new patch set (#5) to the change originally created by Jincheng Li. ( https://review.coreboot.org/c/coreboot/+/81260?usp=email )
Change subject: arch/x86: Fix typo for macro CPUID_FEATURE_HTT
......................................................................
arch/x86: Fix typo for macro CPUID_FEATURE_HTT
Also use BIT macro to replace the original manual bit shift
Change-Id: I9b29233e75483cda6bf7723cf79632f6b04233b0
Signed-off-by: Jincheng Li <jincheng.li(a)intel.com>
---
M src/arch/x86/include/arch/cpu.h
M src/cpu/intel/common/hyperthreading.c
2 files changed, 4 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/81260/5
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Change subject: soc/intel/xeon_sp: Unshare SMM related Kconfigs
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS1:
> Also, I looked at the FSP EAS v2.4 to find out when FSP-I wants to be called, and I couldn't get any information
It's in Figure 4 API Mode Boot Flow right after the MultiPhaseInit. To coreboot
that'd be one block of things to call without coreboot doing anything in between
(SiliconInit, MultiPhaseInit, SmmInit).
For the API mode, "8.2 Model 2 – FSP owns SMRAM" seems to be the only option.
This would really be a big change for coreboot. So I don't think Gerrit is the
right place to discuss it.
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Change subject: mainboard: Introduce BIOS_SIZE
......................................................................
Patch Set 1:
(2 comments)
Patchset:
PS1:
Shuo, can you provide a memory map for this? This seems very different
to all prior Intel silicon. For instance where are your APICs when you
can have >16MiB cacheable directly below 4G?
File src/mainboard/Kconfig:
https://review.coreboot.org/c/coreboot/+/81320/comment/2681bd8b_77bde4a7 :
PS1, Line 257: config BIOS_SIZE_KB_16384
: bool "16384 KB (16 MB)"
: help
: Choose this option if your BIOS region is 16384 KB (16 MB).
:
: config BIOS_SIZE_KB_32768
: bool "32768 KB (32 MB)"
: help
: Choose this option if your BIOS region is 32768 KB (32 MB).
:
: config BIOS_SIZE_KB_49512
: bool "49512 KB (48 MB)"
: help
: Choose this option if your BIOS region is 49512 KB (48 MB).
:
: # Map the config names to the value
: config BIOS_SIZE
: hex
: default 0x01000000 if BIOS_SIZE_KB_16384
: default 0x02000000 if BIOS_SIZE_KB_32768
: default 0x03000000 if BIOS_SIZE_KB_49512
: default 0x01000000
> Drop the Kconfig variables. […]
I believe this is actually a case for `CACHE_ROM_BASE`/`CACHE_ROM_SIZE`
from `include/cpu/x86/mtrr.h`.
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Change subject: Docs/tutorial: Do not install Ada compiler by default
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
I have tested some newer OS/package combinations with the tutorial instructions:
* Ubuntu 23.10 with gcc-9 / gcc-12 / no gcc pre-installed and various update-alternatives settings.
* Fedora 39 / 40 (testing)
* Alma Linux 9
On Ubuntu, when I either installed gcc, build-essentials or gnat, it overwrote any
link set by update-alternatives (not using it, just running the pointer down /o\).
The Redhat-based ones didn't work because `cmp` was missing (should probably add
`diffutils` to the tutorial).
Alma needed `epel` to be installed ahead. But I expect enterprise users to know this.
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