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Change subject: soc/intel/xeon_sp: Add memory type check utils
......................................................................
Patch Set 4:
(1 comment)
File src/soc/intel/xeon_sp/util.c:
https://review.coreboot.org/c/coreboot/+/80632/comment/7b3f376d_9240144e :
PS3, Line 126: __weak bool is_memtype_processor_attached(UINT16 mem_type)
: {
: return true;
: }
:
> > For this case, if we only inline but not add static, the optimization out will not happen. […]
good catch! updated
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Hello Arthur Heymans, Christian Walter, Felix Held, Jincheng Li, Johnny Lin, Lean Sheng Tan, Nico Huber, Patrick Rudolph, Tim Chu, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/80632?usp=email
to look at the new patch set (#4).
The following approvals got outdated and were removed:
Code-Review+1 by Lean Sheng Tan, Verified+1 by build bot (Jenkins)
Change subject: soc/intel/xeon_sp: Add memory type check utils
......................................................................
soc/intel/xeon_sp: Add memory type check utils
FSP memory type representations change across Xeon-SP SoCs.
This patch adds type check utils to abstract the differences.
TEST=intel/archercity CRB
Change-Id: I2f5f3c0f16dc50bc739146e46afce2e5fbf4f62c
Signed-off-by: Shuo Liu <shuo.liu(a)intel.com>
Signed-off-by: Jincheng Li <jincheng.li(a)intel.com>
---
M src/soc/intel/xeon_sp/include/soc/util.h
M src/soc/intel/xeon_sp/spr/soc_util.c
M src/soc/intel/xeon_sp/uncore_acpi.c
M src/soc/intel/xeon_sp/util.c
4 files changed, 30 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/80632/4
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Change subject: Documentation: Add 24.05 release notes template
......................................................................
Patch Set 1: Code-Review+2
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Change subject: Docs/releases: Finalize 24.02 release notes
......................................................................
Patch Set 1: Code-Review+2
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Change subject: Docs/releases: Finalize 24.02 release notes
......................................................................
Docs/releases: Finalize 24.02 release notes
Change-Id: I5ba6619ee7ed408a33548ab5b6f7d2a2143e88e7
Signed-off-by: Martin Roth <gaumless(a)gmail.com>
---
M Documentation/releases/coreboot-24.02-relnotes.md
1 file changed, 20 insertions(+), 20 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/80751/1
diff --git a/Documentation/releases/coreboot-24.02-relnotes.md b/Documentation/releases/coreboot-24.02-relnotes.md
index d941e2c..eb5349e 100644
--- a/Documentation/releases/coreboot-24.02-relnotes.md
+++ b/Documentation/releases/coreboot-24.02-relnotes.md
@@ -1,10 +1,7 @@
-Upcoming release - coreboot 24.02
+coreboot 24.02 release
========================================================================
-The 24.02 release is scheduled for February 19, 2024. The next release,
-which will be 24.05, is scheduled for mid-May.
-
-The coreboot project is happy to announce our next release for February
+The coreboot project is happy to announce our release for February
2024. Over the past three months, our contributors have focused on
refining the coreboot codebase, generally prioritizing cleanup and
quality enhancements. We extend our gratitude to all the contributors
@@ -12,6 +9,8 @@
invaluable contributions to this vital phase of maintenance and
optimization.
+The next release is scheduled for mid-May.
+
### Release number format update
@@ -127,9 +126,9 @@
### Toolchain updates
* Add buildgcc support for Apple M1/M2 devices
-* crossgcc: Upgrade GCC from 11.4.0 to 13.2.0
-* util/crossgcc: Update CMake from 3.26.4 to 3.27.7
-* util/kconfig: Uprev to Linux 6.7 kconfig
+* Upgrade GCC from 11.4.0 to 13.2.0
+* Update CMake from 3.26.4 to 3.27.7
+* Uprev to Kconfig from Linux 6.7
### Git submodule pointers
@@ -140,9 +139,9 @@
17bef2248d (701 commits)
* /3rdparty/fsp: Update from commit id 481ea7cf0b to 507ef01cce (16 commits)
* /3rdparty/intel-microcode: Update from commit id 6788bb07eb to
- ece0d294a2 (1 commits)
-* /3rdparty/vboot: Update from commit id 24cb127a5e to 3d37d2aafe (121
- commits)
+ ece0d294a2 (1 commit)
+* /3rdparty/vboot: Update from commit id 24cb127a5e to 3d37d2aafe
+ (121 commits)
### External payloads
@@ -168,15 +167,15 @@
Statistics from the 4.22 to the 24.02 release
--------------------------------------------
-* Total Commits: 814
-* Average Commits per day: 8.65
-* Total lines added: 105203
-* Average lines added per commit: 129.24
-* Number of patches adding more than 100 lines: 46
+* Total Commits: 815
+* Average Commits per day: 8.63
+* Total lines added: 105433
+* Average lines added per commit: 129.37
+* Number of patches adding more than 100 lines: 47
* Average lines added per small commit: 41.34
-* Total lines removed: 16505
-* Average lines removed per commit: 20.28
-* Total difference between added and removed: 88698
+* Total lines removed: 16534
+* Average lines removed per commit: 20.29
+* Total difference between added and removed: 88899
* Total authors: 111
* New authors: 19
@@ -185,7 +184,8 @@
Significant Known and Open Issues
---------------------------------
-* AMD chromebooks will not currently work with the signed vboot image.
+* AMD chromebooks will not work with the signed PSP_verstage images and
+ the version of verstage used in coreboot 24.02.
## Issues from the coreboot bugtracker: https://ticket.coreboot.org/
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Change subject: util/crossgcc: Use ninja to build llvm/clang
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
I did 4 measurements (2 each) with 8 jobs on a machine that did nothing besides building the toolchain (no graphical enviroment etc):
```
ninja:
First round: 38:05
Second round: 38:15
make:
First round: 38:24
Second round: 38:57
```
So I guess ninja is a few seconds faster.
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Change subject: include/device: Merge enums from azalia_device.h and azalia.h
......................................................................
Patch Set 5:
(1 comment)
File src/include/device/azalia_device.h:
https://review.coreboot.org/c/coreboot/+/80695/comment/3ba1e0ac_b81812ce :
PS5, Line 60: AZALIA_LOCATION_UNKNOWN
> Would something like AZALIA_LOCATION_NOT_APPLICABLE make more […]
I chose "unknown" for consistency with the others. I think you have a point here though. Maybe, we could `s/UNKNOWN/NOT_APPLICABLE/` since I feel like this also makes sense for `COLOR_UNKNOWN` and `TYPE_UNKNOWN` and this would also keep the consistency as well.
I would highly discourage anyone from using this value in mainboard configurations after the merge locations patch. However, I would still prefer to keep this value.
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Change subject: mb/purism/librem_cnl/var/librem_mini: Set RTC register defaults
......................................................................
Abandoned
CB:80750 is a better solution and avoids breaking the RTC
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Change subject: soc/intel/common/lpc_lib: Demote printk for IO base value 0
......................................................................
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Change subject: soc/intel/common/lpc: Don't open a window for unassigned resources
......................................................................
soc/intel/common/lpc: Don't open a window for unassigned resources
Don't attempt to open a PMIO window for a resource which doesn't have
the IORESOURCE_ASSIGNED flag set, since there is no point in doing so
and there's a high likelihood that the base address is 0, which will
throw an error.
TEST=build/boot purism/librem_cnl (Mini v2), ensure no errors in cbmem
log for attempting to open a PMIO window for unaassigned resources with
base address 0.
Change-Id: Ifba14a8f134ba12d5f5e9fdbac775d4f82b4c4de
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
---
M src/soc/intel/common/block/lpc/lpc.c
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/80750/1
diff --git a/src/soc/intel/common/block/lpc/lpc.c b/src/soc/intel/common/block/lpc/lpc.c
index b27e09e9..e805035 100644
--- a/src/soc/intel/common/block/lpc/lpc.c
+++ b/src/soc/intel/common/block/lpc/lpc.c
@@ -91,7 +91,7 @@
return;
for (res = dev->resource_list; res; res = res->next) {
- if (res->flags & IORESOURCE_IO)
+ if ((res->flags & IORESOURCE_IO) && (res->flags & IORESOURCE_ASSIGNED))
lpc_open_pmio_window(res->base, res->size);
}
pch_lpc_set_child_resources(dev);
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