coreboot-gerrit February 2024

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[M] Change in coreboot[main]: device/pciexp_device.c: Fix setting Max Payload Size
by Michał Żygowski (Code Review) 26 Feb '24

26 Feb '24

Attention is currently required from: Angel Pons, Arthur Heymans, Felix Held, Krystian Hebel, Kyösti Mälkki, Nico Huber. Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77338?usp=email ) Change subject: device/pciexp_device.c: Fix setting Max Payload Size ...................................................................... Patch Set 21: (1 comment) File src/device/pciexp_device.c: https://review.coreboot.org/c/coreboot/+/77338/comment/d22e4edd_5d5017d0 : PS20, Line 603: devctl |= max_payload << 5; > Please either mask it with `PCI_EXP_DEVCTL_PAYLOAD` or add a comment that […] Added a comment -- To view, visit https://review.coreboot.org/c/coreboot/+/77338?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I24386dc208363b7d94fea46dec25c231a3968225 Gerrit-Change-Number: 77338 Gerrit-PatchSet: 21 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Angel Pons <angel.pons(a)9elements.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 26 Feb 2024 14:25:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: device/pciexp_device.c: Fix setting Max Payload Size
by Michał Żygowski (Code Review) 26 Feb '24

26 Feb '24

Attention is currently required from: Angel Pons, Arthur Heymans, Felix Held, Kyösti Mälkki, Michał Żygowski, Nico Huber. Hello Angel Pons, Arthur Heymans, Felix Held, Kyösti Mälkki, Nico Huber, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/77338?usp=email to look at the new patch set (#21). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: device/pciexp_device.c: Fix setting Max Payload Size ...................................................................... device/pciexp_device.c: Fix setting Max Payload Size Current implementation assumes that the endpoint device is connected directly to the PCIe Root Port, which does not always have to be true. In a case where there is a PCIe switch between the endpoint and the root port, the Max Payload Size capability may differ across the devices in the chain and coreboot will not set a correct Max Payload Size. This results in a PCIe device malfunction in pre-OS environment, e.g. if the Ethernet NICs are connected behind a PCIe switch, the iPXE fails to obtain the DHCP configuration. Fix this by traversing the topology and programming the highest common Max Payload Size in the given PCIe device chain during enumeration. Once finished, the root port has the highest common Max Payload Size supported by all the devices in the chain. So at the end of root port bus scan, propagate the root port's Max Payload Size to all downstream devices to keep Max Payload Size in sync within the whole chain. TEST=Perform successful dhcp command in iPXE on the NIC connected to the PCIe root port via ASMedia ASM1806 PCIe switch and again on the NIC connected directly to the PCIe root port. Change-Id: I24386dc208363b7d94fea46dec25c231a3968225 Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> --- M src/device/pciexp_device.c 1 file changed, 134 insertions(+), 29 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/77338/21 -- To view, visit https://review.coreboot.org/c/coreboot/+/77338?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I24386dc208363b7d94fea46dec25c231a3968225 Gerrit-Change-Number: 77338 Gerrit-PatchSet: 21 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Angel Pons <angel.pons(a)9elements.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: mb/google/nissa/var/glassway: Add memory config
by Eric Lai (Code Review) 26 Feb '24

26 Feb '24

Attention is currently required from: Daniel Peng, Kapil Porwal, Nick Vaccaro, Shawn Ku. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80763?usp=email ) Change subject: mb/google/nissa/var/glassway: Add memory config ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: You don't need this CL, since same gpio setting as baseboard. -- To view, visit https://review.coreboot.org/c/coreboot/+/80763?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id85d590ed55997690e4c279ae83544b78fe72eec Gerrit-Change-Number: 80763 Gerrit-PatchSet: 2 Gerrit-Owner: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Shawn Ku <shawnku(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Shawn Ku <shawnku(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-Comment-Date: Mon, 26 Feb 2024 14:12:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[L] Change in coreboot[main]: mb/google/nissa/var/glassway: Initialize devicetree setting
by Eric Lai (Code Review) 26 Feb '24

26 Feb '24

Attention is currently required from: Daniel Peng, Kapil Porwal, Nick Vaccaro, Shawn Ku. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80742?usp=email ) Change subject: mb/google/nissa/var/glassway: Initialize devicetree setting ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/80742?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibbb10a373bd5fa52a0833b81133517d2a088536b Gerrit-Change-Number: 80742 Gerrit-PatchSet: 3 Gerrit-Owner: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Shawn Ku <shawnku(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Shawn Ku <shawnku(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-Comment-Date: Mon, 26 Feb 2024 14:09:38 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: soc/intel/xeon_sp: Add memory type check utils
by Shuo Liu (Code Review) 26 Feb '24

26 Feb '24

Attention is currently required from: Arthur Heymans, Christian Walter, Felix Held, Jincheng Li, Johnny Lin, Lean Sheng Tan, Nico Huber, Patrick Rudolph, Tim Chu. Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80632?usp=email ) Change subject: soc/intel/xeon_sp: Add memory type check utils ...................................................................... Patch Set 4: (1 comment) File src/soc/intel/xeon_sp/spr/soc_util.c: https://review.coreboot.org/c/coreboot/+/80632/comment/91e54dee_0f09e23f : PS4, Line 187: MemTypeCxlAccVolatileMem > hmm, this relies on the order of the enum values; not sure how good of an idea it is to do that. […] Sure, agree that this check needs to be further clarified. Will have a separate patch on this. Thanks for pointing out this. -- To view, visit https://review.coreboot.org/c/coreboot/+/80632?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2f5f3c0f16dc50bc739146e46afce2e5fbf4f62c Gerrit-Change-Number: 80632 Gerrit-PatchSet: 4 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Mon, 26 Feb 2024 13:55:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: soc/intel/xeon_sp: Add memory type check utils
by Felix Held (Code Review) 26 Feb '24

26 Feb '24

Attention is currently required from: Arthur Heymans, Christian Walter, Jincheng Li, Johnny Lin, Lean Sheng Tan, Nico Huber, Patrick Rudolph, Shuo Liu, Tim Chu. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80632?usp=email ) Change subject: soc/intel/xeon_sp: Add memory type check utils ...................................................................... Patch Set 4: (1 comment) File src/soc/intel/xeon_sp/spr/soc_util.c: https://review.coreboot.org/c/coreboot/+/80632/comment/39aecdfb_3aa43f3c : PS4, Line 187: MemTypeCxlAccVolatileMem hmm, this relies on the order of the enum values; not sure how good of an idea it is to do that. this patch just moves the code around, so it's probably something for a separate patch, but this smells like potential trouble to me -- To view, visit https://review.coreboot.org/c/coreboot/+/80632?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2f5f3c0f16dc50bc739146e46afce2e5fbf4f62c Gerrit-Change-Number: 80632 Gerrit-PatchSet: 4 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Mon, 26 Feb 2024 13:14:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[main]: mb/hp/snb_ivb_desktops: Make baseboard more generic
by Felix Held (Code Review) 26 Feb '24

26 Feb '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79543?usp=email ) Change subject: mb/hp/snb_ivb_desktops: Make baseboard more generic ...................................................................... mb/hp/snb_ivb_desktops: Make baseboard more generic In preparation to merging all the other HP sandy/ivy desktops in here as variants. Move hda_verb.c, early_init.c, gma-mainboard.ads and data.vbt into variant directories. Kconfig: Move options not common to the others under the variants instead. devicetree: Move XHCI to variant overridetrees (8200 gen has no USB 3) board_info.txt: Make it more generic. It seems to be copied from 8200 SFF and inaccurate to Z220 anyway. TEST: BUILD_TIMELESS=1 & Don't include .config in ROM image. CMT and SFF ROMs are (SHA1) same as before. Change-Id: Icce22efb8d353359781db3f03c67058d8fbe11b8 Signed-off-by: Riku Viitanen <riku.viitanen(a)protonmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79543 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nicholas Chin <nic.c3.14(a)gmail.com> --- M src/mainboard/hp/snb_ivb_desktops/Kconfig M src/mainboard/hp/snb_ivb_desktops/Makefile.mk M src/mainboard/hp/snb_ivb_desktops/board_info.txt M src/mainboard/hp/snb_ivb_desktops/devicetree.cb R src/mainboard/hp/snb_ivb_desktops/variants/z220_cmt_workstation/data.vbt R src/mainboard/hp/snb_ivb_desktops/variants/z220_cmt_workstation/early_init.c R src/mainboard/hp/snb_ivb_desktops/variants/z220_cmt_workstation/gma-mainboard.ads R src/mainboard/hp/snb_ivb_desktops/variants/z220_cmt_workstation/hda_verb.c M src/mainboard/hp/snb_ivb_desktops/variants/z220_cmt_workstation/overridetree.cb C src/mainboard/hp/snb_ivb_desktops/variants/z220_sff_workstation/data.vbt C src/mainboard/hp/snb_ivb_desktops/variants/z220_sff_workstation/early_init.c C src/mainboard/hp/snb_ivb_desktops/variants/z220_sff_workstation/gma-mainboard.ads C src/mainboard/hp/snb_ivb_desktops/variants/z220_sff_workstation/hda_verb.c M src/mainboard/hp/snb_ivb_desktops/variants/z220_sff_workstation/overridetree.cb 14 files changed, 22 insertions(+), 18 deletions(-) Approvals: Nicholas Chin: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/hp/snb_ivb_desktops/Kconfig b/src/mainboard/hp/snb_ivb_desktops/Kconfig index 8791686..b79f748 100644 --- a/src/mainboard/hp/snb_ivb_desktops/Kconfig +++ b/src/mainboard/hp/snb_ivb_desktops/Kconfig @@ -2,8 +2,6 @@ config BOARD_HP_SNB_IVB_DESKTOPS_COMMON def_bool n - select BOARD_ROMSIZE_KB_16384 - select GFX_GMA_ANALOG_I2C_HDMI_B select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select HAVE_CMOS_DEFAULT @@ -16,15 +14,20 @@ select MEMORY_MAPPED_TPM select NORTHBRIDGE_INTEL_SANDYBRIDGE select SERIRQ_CONTINUOUS_MODE - select SOUTHBRIDGE_INTEL_BD82X6X select SUPERIO_NUVOTON_NPCD378 select USE_NATIVE_RAMINIT config BOARD_HP_Z220_CMT_WORKSTATION select BOARD_HP_SNB_IVB_DESKTOPS_COMMON + select BOARD_ROMSIZE_KB_16384 + select GFX_GMA_ANALOG_I2C_HDMI_B + select SOUTHBRIDGE_INTEL_BD82X6X config BOARD_HP_Z220_SFF_WORKSTATION select BOARD_HP_SNB_IVB_DESKTOPS_COMMON + select BOARD_ROMSIZE_KB_16384 + select GFX_GMA_ANALOG_I2C_HDMI_B + select SOUTHBRIDGE_INTEL_BD82X6X if BOARD_HP_SNB_IVB_DESKTOPS_COMMON @@ -54,7 +57,7 @@ default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" config INTEL_GMA_VBT_FILE - default "src/mainboard/\$(MAINBOARDDIR)/data.vbt" + default "src/mainboard/\$(MAINBOARDDIR)/variants/\$(CONFIG_VARIANT_DIR)/data.vbt" config DRAM_RESET_GATE_GPIO int diff --git a/src/mainboard/hp/snb_ivb_desktops/Makefile.mk b/src/mainboard/hp/snb_ivb_desktops/Makefile.mk index 69ef088..4b44049 100644 --- a/src/mainboard/hp/snb_ivb_desktops/Makefile.mk +++ b/src/mainboard/hp/snb_ivb_desktops/Makefile.mk @@ -2,6 +2,7 @@ bootblock-y += variants/$(VARIANT_DIR)/gpio.c romstage-y += variants/$(VARIANT_DIR)/gpio.c -ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads -bootblock-y += early_init.c -romstage-y += early_init.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainboard.ads +bootblock-y += variants/$(VARIANT_DIR)/early_init.c +romstage-y += variants/$(VARIANT_DIR)/early_init.c +ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c diff --git a/src/mainboard/hp/snb_ivb_desktops/board_info.txt b/src/mainboard/hp/snb_ivb_desktops/board_info.txt index 4d6f6f9..813c1c9 100644 --- a/src/mainboard/hp/snb_ivb_desktops/board_info.txt +++ b/src/mainboard/hp/snb_ivb_desktops/board_info.txt @@ -1,7 +1,5 @@ Category: desktop -Board URL: https://support.hp.com/de-de/product/HP-Compaq-8200-Elite-Small-Form-Factor… -ROM IC: MX25L6405 -ROM package: SOIC-8 +ROM package: SOIC-8 or SOIC-16 ROM socketed: no Flashrom support: yes -Release year: 2013 +Release year: 2011-2012 diff --git a/src/mainboard/hp/snb_ivb_desktops/devicetree.cb b/src/mainboard/hp/snb_ivb_desktops/devicetree.cb index d1aa576..113b555 100644 --- a/src/mainboard/hp/snb_ivb_desktops/devicetree.cb +++ b/src/mainboard/hp/snb_ivb_desktops/devicetree.cb @@ -9,8 +9,6 @@ register "spd_addresses" = "{0x53, 0x52, 0x51, 0x50}" device domain 0 on - subsystemid 0x103c 0x1791 inherit - device ref host_bridge on end device ref peg10 on end device ref igd on end @@ -25,11 +23,7 @@ register "sata_interface_speed_support" = "0x3" register "spi_lvscc" = "0x2005" register "spi_uvscc" = "0x2005" - register "superspeed_capable_ports" = "0x0000000f" - register "xhci_switchable_ports" = "0x0000000f" - register "xhci_overcurrent_mapping" = "0x0000000f" - device ref xhci on end device ref mei1 on end device ref mei2 off end device ref me_ide_r off end diff --git a/src/mainboard/hp/snb_ivb_desktops/data.vbt b/src/mainboard/hp/snb_ivb_desktops/variants/z220_cmt_workstation/data.vbt similarity index 100% rename from src/mainboard/hp/snb_ivb_desktops/data.vbt rename to src/mainboard/hp/snb_ivb_desktops/variants/z220_cmt_workstation/data.vbt Binary files differ diff --git a/src/mainboard/hp/snb_ivb_desktops/early_init.c b/src/mainboard/hp/snb_ivb_desktops/variants/z220_cmt_workstation/early_init.c similarity index 100% rename from src/mainboard/hp/snb_ivb_desktops/early_init.c rename to src/mainboard/hp/snb_ivb_desktops/variants/z220_cmt_workstation/early_init.c diff --git a/src/mainboard/hp/snb_ivb_desktops/gma-mainboard.ads b/src/mainboard/hp/snb_ivb_desktops/variants/z220_cmt_workstation/gma-mainboard.ads similarity index 100% rename from src/mainboard/hp/snb_ivb_desktops/gma-mainboard.ads rename to src/mainboard/hp/snb_ivb_desktops/variants/z220_cmt_workstation/gma-mainboard.ads diff --git a/src/mainboard/hp/snb_ivb_desktops/hda_verb.c b/src/mainboard/hp/snb_ivb_desktops/variants/z220_cmt_workstation/hda_verb.c similarity index 100% rename from src/mainboard/hp/snb_ivb_desktops/hda_verb.c rename to src/mainboard/hp/snb_ivb_desktops/variants/z220_cmt_workstation/hda_verb.c diff --git a/src/mainboard/hp/snb_ivb_desktops/variants/z220_cmt_workstation/overridetree.cb b/src/mainboard/hp/snb_ivb_desktops/variants/z220_cmt_workstation/overridetree.cb index b82ff8a..1867d3a 100644 --- a/src/mainboard/hp/snb_ivb_desktops/variants/z220_cmt_workstation/overridetree.cb +++ b/src/mainboard/hp/snb_ivb_desktops/variants/z220_cmt_workstation/overridetree.cb @@ -6,7 +6,11 @@ device ref peg60 on end chip southbridge/intel/bd82x6x register "sata_port_map" = "0x3f" + register "superspeed_capable_ports" = "0x0000000f" + register "xhci_switchable_ports" = "0x0000000f" + register "xhci_overcurrent_mapping" = "0x0000000f" + device ref xhci on end device ref pcie_rp2 on end device ref pcie_rp3 on end device ref pcie_rp4 on end diff --git a/src/mainboard/hp/snb_ivb_desktops/data.vbt b/src/mainboard/hp/snb_ivb_desktops/variants/z220_sff_workstation/data.vbt similarity index 100% copy from src/mainboard/hp/snb_ivb_desktops/data.vbt copy to src/mainboard/hp/snb_ivb_desktops/variants/z220_sff_workstation/data.vbt Binary files differ diff --git a/src/mainboard/hp/snb_ivb_desktops/early_init.c b/src/mainboard/hp/snb_ivb_desktops/variants/z220_sff_workstation/early_init.c similarity index 100% copy from src/mainboard/hp/snb_ivb_desktops/early_init.c copy to src/mainboard/hp/snb_ivb_desktops/variants/z220_sff_workstation/early_init.c diff --git a/src/mainboard/hp/snb_ivb_desktops/gma-mainboard.ads b/src/mainboard/hp/snb_ivb_desktops/variants/z220_sff_workstation/gma-mainboard.ads similarity index 100% copy from src/mainboard/hp/snb_ivb_desktops/gma-mainboard.ads copy to src/mainboard/hp/snb_ivb_desktops/variants/z220_sff_workstation/gma-mainboard.ads diff --git a/src/mainboard/hp/snb_ivb_desktops/hda_verb.c b/src/mainboard/hp/snb_ivb_desktops/variants/z220_sff_workstation/hda_verb.c similarity index 100% copy from src/mainboard/hp/snb_ivb_desktops/hda_verb.c copy to src/mainboard/hp/snb_ivb_desktops/variants/z220_sff_workstation/hda_verb.c diff --git a/src/mainboard/hp/snb_ivb_desktops/variants/z220_sff_workstation/overridetree.cb b/src/mainboard/hp/snb_ivb_desktops/variants/z220_sff_workstation/overridetree.cb index 8b827f8..560b407 100644 --- a/src/mainboard/hp/snb_ivb_desktops/variants/z220_sff_workstation/overridetree.cb +++ b/src/mainboard/hp/snb_ivb_desktops/variants/z220_sff_workstation/overridetree.cb @@ -6,7 +6,11 @@ chip southbridge/intel/bd82x6x register "sata_port_map" = "0xf" - device ref pcie_rp5 on end # dummy setting + register "superspeed_capable_ports" = "0x0000000f" + register "xhci_switchable_ports" = "0x0000000f" + register "xhci_overcurrent_mapping" = "0x0000000f" + + device ref xhci on end end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/79543?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icce22efb8d353359781db3f03c67058d8fbe11b8 Gerrit-Change-Number: 79543 Gerrit-PatchSet: 11 Gerrit-Owner: Riku Viitanen <riku.viitanen(a)protonmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[main]: vc/google/chromeos: Implement dynamic ChromeOS boot logo selection
by Subrata Banik (Code Review) 26 Feb '24

26 Feb '24

Attention is currently required from: Kapil Porwal, Paul Menzel, Paz Zcharya, Shelley Chen. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80738?usp=email ) Change subject: vc/google/chromeos: Implement dynamic ChromeOS boot logo selection ...................................................................... Patch Set 7: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/80738/comment/0bc8a10c_67aa9321 : PS7, Line 11: Chromebook-Plus > Just a note, that on [1] it’s written with a space: Chromebook Plus. > > But not important, please feel free to mark as resolved. > > [1]: https://www.google.com/intl/de_de/chromebook/discover/chromebookplus/ this is "brand string/logo" what u have shared (where `plus` is bold). not necessarily we need to follow exact same "brand string/logo" in commit. -- To view, visit https://review.coreboot.org/c/coreboot/+/80738?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9bb1e868764738333977bd8c990bea4253c9d37b Gerrit-Change-Number: 80738 Gerrit-PatchSet: 7 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Paz Zcharya <pazz(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Paz Zcharya <pazz(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Mon, 26 Feb 2024 13:05:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

1 0

[XS] Change in coreboot[main]: lib: Explicitly declare heap as NOLOAD
by Felix Held (Code Review) 26 Feb '24

26 Feb '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80735?usp=email ) Change subject: lib: Explicitly declare heap as NOLOAD ...................................................................... lib: Explicitly declare heap as NOLOAD The GNU BFD linker makes a good guess that this section should not be loaded, however other linkers like LLVM LD need this to be made explicit in order for the section to have the NOBITS, rather than PROGBITS attribute set. Change-Id: I3ca7221d10f144f608823e0b9624533780fbf335 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80735 Reviewed-by: Maximilian Brune <maximilian.brune(a)9elements.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- M src/lib/program.ld 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Julius Werner: Looks good to me, approved Maximilian Brune: Looks good to me, approved diff --git a/src/lib/program.ld b/src/lib/program.ld index 21f4be8..6d72d9e 100644 --- a/src/lib/program.ld +++ b/src/lib/program.ld @@ -131,7 +131,7 @@ #endif #if ENV_HAS_HEAP_SECTION -.heap . : { +.heap . (NOLOAD) : { . = ALIGN(ARCH_POINTER_ALIGN_SIZE); _heap = .; . += CONFIG_HEAP_SIZE; -- To view, visit https://review.coreboot.org/c/coreboot/+/80735?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3ca7221d10f144f608823e0b9624533780fbf335 Gerrit-Change-Number: 80735 Gerrit-PatchSet: 5 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[M] Change in coreboot[main]: soc/mediatek: Add `MEDIATEK_DRAM_ADAPTIVE` config to support dram ada...
by Felix Held (Code Review) 26 Feb '24

26 Feb '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80687?usp=email ) Change subject: soc/mediatek: Add `MEDIATEK_DRAM_ADAPTIVE` config to support dram adaptive ...................................................................... soc/mediatek: Add `MEDIATEK_DRAM_ADAPTIVE` config to support dram adaptive Starting from MT8195, MediaTek platform supports "dram adaptive" to automatically detect dram information, including channel, rank, die size..., and can automatically configure EMI settings. So we can just pass a placeholder param blob to `mt_mem_init_run` by enabling this option. Platforms (MT8173, MT8183, MT8192) which do not support "dram adaptive" need to implement `get_sdram_config` to get onboard DRAM configuration info. TEST=emerge-geralt coreboot && emerge-asurada coreboot TEST=CONFIG_MEDIATEK_DRAM_ADAPTIVE is set to y on geralt TEST=CONFIG_MEDIATEK_DRAM_ADAPTIVE is no set on asurada Change-Id: I05a01b1ab13fbf19b2a908c48a540a5c2e1ccbdc Signed-off-by: Yidi Lin <yidilin(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80687 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/mainboard/google/cherry/Makefile.mk D src/mainboard/google/cherry/sdram_configs.c M src/mainboard/google/corsola/Makefile.mk D src/mainboard/google/corsola/sdram_configs.c M src/mainboard/google/geralt/Makefile.mk D src/mainboard/google/geralt/sdram_configs.c M src/soc/mediatek/common/Kconfig M src/soc/mediatek/common/include/soc/dramc_param_common.h M src/soc/mediatek/common/memory.c M src/soc/mediatek/mt8186/include/soc/dramc_param.h M src/soc/mediatek/mt8188/include/soc/dramc_param.h M src/soc/mediatek/mt8192/include/soc/dramc_param.h M src/soc/mediatek/mt8195/include/soc/dramc_param.h 13 files changed, 24 insertions(+), 53 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved diff --git a/src/mainboard/google/cherry/Makefile.mk b/src/mainboard/google/cherry/Makefile.mk index 5fe1339..41ec839 100644 --- a/src/mainboard/google/cherry/Makefile.mk +++ b/src/mainboard/google/cherry/Makefile.mk @@ -14,7 +14,6 @@ romstage-y += regulator.c romstage-y += reset.c romstage-y += romstage.c -romstage-y += sdram_configs.c ramstage-y += memlayout.ld ramstage-y += boardid.c diff --git a/src/mainboard/google/cherry/sdram_configs.c b/src/mainboard/google/cherry/sdram_configs.c deleted file mode 100644 index de6bdd1..0000000 --- a/src/mainboard/google/cherry/sdram_configs.c +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <soc/dramc_param.h> - -const struct sdram_info *get_sdram_config(void) -{ - /* - * The MT8195 platform supports "dram adaptive" feature to - * automatically detect dram information, including channel, rank, die size..., - * and can automatically configure EMI settings. - * So we will be passing a placeholder param blob. - */ - static struct sdram_info params; - return &params; -} diff --git a/src/mainboard/google/corsola/Makefile.mk b/src/mainboard/google/corsola/Makefile.mk index 5483167..1442f33 100644 --- a/src/mainboard/google/corsola/Makefile.mk +++ b/src/mainboard/google/corsola/Makefile.mk @@ -14,7 +14,6 @@ romstage-y += regulator.c romstage-y += reset.c romstage-y += romstage.c -romstage-y += sdram_configs.c ramstage-y += memlayout.ld ramstage-y += boardid.c diff --git a/src/mainboard/google/corsola/sdram_configs.c b/src/mainboard/google/corsola/sdram_configs.c deleted file mode 100644 index f565f53..0000000 --- a/src/mainboard/google/corsola/sdram_configs.c +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <soc/dramc_param.h> - -const struct sdram_info *get_sdram_config(void) -{ - /* - * The MT8186 platform supports "dram adaptive" feature to - * automatically detect dram information, including channel, rank, die size..., - * and can automatically configure EMI settings. - * So we will be passing a placeholder param blob. - */ - static struct sdram_info params; - return &params; -} diff --git a/src/mainboard/google/geralt/Makefile.mk b/src/mainboard/google/geralt/Makefile.mk index b1af289..0975c5c 100644 --- a/src/mainboard/google/geralt/Makefile.mk +++ b/src/mainboard/google/geralt/Makefile.mk @@ -15,7 +15,6 @@ romstage-y += regulator.c romstage-y += reset.c romstage-y += romstage.c -romstage-y += sdram_configs.c ramstage-y += memlayout.ld ramstage-y += boardid.c diff --git a/src/mainboard/google/geralt/sdram_configs.c b/src/mainboard/google/geralt/sdram_configs.c deleted file mode 100644 index c4766be..0000000 --- a/src/mainboard/google/geralt/sdram_configs.c +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <soc/dramc_param.h> - -const struct sdram_info *get_sdram_config(void) -{ - /* - * The MT8188 platform supports "dram adaptive" feature to automatically - * detect dram information, including channel, rank, die size..., and - * can automatically configure EMI settings. Therefore, we will be - * passing a placeholder param blob. - */ - static struct sdram_info params; - return &params; -} diff --git a/src/soc/mediatek/common/Kconfig b/src/soc/mediatek/common/Kconfig index 898918a..55ea5ec 100644 --- a/src/soc/mediatek/common/Kconfig +++ b/src/soc/mediatek/common/Kconfig @@ -8,6 +8,21 @@ if SOC_MEDIATEK_COMMON +config MEDIATEK_DRAM_ADAPTIVE + bool + default n if SOC_MEDIATEK_MT8173 + default n if SOC_MEDIATEK_MT8183 + default n if SOC_MEDIATEK_MT8192 + default y + help + Starting from MT8195, MediaTek platform supports "dram adaptive" to + automatically detect dram information, including channel, rank, die + size..., and can automatically configure EMI settings. So we can just + pass a placeholder param blob to `mt_mem_init_run` by enabling this + option. + Platforms (MT8173, MT8183, MT8192) which do not support "dram adaptive" + need to implement `get_sdram_config` to get the DRAM configuration info. + config MEDIATEK_DRAM_DVFS bool default n diff --git a/src/soc/mediatek/common/include/soc/dramc_param_common.h b/src/soc/mediatek/common/include/soc/dramc_param_common.h index 429f3c6..7dd8bba 100644 --- a/src/soc/mediatek/common/include/soc/dramc_param_common.h +++ b/src/soc/mediatek/common/include/soc/dramc_param_common.h @@ -101,4 +101,6 @@ u32 data_rate; }; +const struct sdram_info *get_sdram_config(void); + #endif diff --git a/src/soc/mediatek/common/memory.c b/src/soc/mediatek/common/memory.c index be72023..72ea37e 100644 --- a/src/soc/mediatek/common/memory.c +++ b/src/soc/mediatek/common/memory.c @@ -313,7 +313,13 @@ void mt_mem_init(struct dramc_param *dparam) { - const struct sdram_info *sdram_param = get_sdram_config(); + const struct sdram_info *sdram_param = NULL; + static struct sdram_info fake_sdram_param; + + if (CONFIG(MEDIATEK_DRAM_ADAPTIVE)) + sdram_param = &fake_sdram_param; + else + sdram_param = get_sdram_config(); mt_mem_init_run(dparam, sdram_param); } diff --git a/src/soc/mediatek/mt8186/include/soc/dramc_param.h b/src/soc/mediatek/mt8186/include/soc/dramc_param.h index 2d6212b..29380c2 100644 --- a/src/soc/mediatek/mt8186/include/soc/dramc_param.h +++ b/src/soc/mediatek/mt8186/include/soc/dramc_param.h @@ -78,7 +78,6 @@ struct dramc_data dramc_datas; }; -const struct sdram_info *get_sdram_config(void); struct dramc_param *get_dramc_param_from_blob(void *blob); void dump_param_header(const void *blob); int initialize_dramc_param(void *blob); diff --git a/src/soc/mediatek/mt8188/include/soc/dramc_param.h b/src/soc/mediatek/mt8188/include/soc/dramc_param.h index 88e2a90..740e27b 100644 --- a/src/soc/mediatek/mt8188/include/soc/dramc_param.h +++ b/src/soc/mediatek/mt8188/include/soc/dramc_param.h @@ -98,7 +98,6 @@ struct dramc_data dramc_datas; }; -const struct sdram_info *get_sdram_config(void); struct dramc_param *get_dramc_param_from_blob(void *blob); void dump_param_header(const void *blob); int validate_dramc_param(const void *blob); diff --git a/src/soc/mediatek/mt8192/include/soc/dramc_param.h b/src/soc/mediatek/mt8192/include/soc/dramc_param.h index c4f1293..fca82be 100644 --- a/src/soc/mediatek/mt8192/include/soc/dramc_param.h +++ b/src/soc/mediatek/mt8192/include/soc/dramc_param.h @@ -73,7 +73,6 @@ struct dramc_data dramc_datas; }; -const struct sdram_info *get_sdram_config(void); struct dramc_param *get_dramc_param_from_blob(void *blob); void dump_param_header(const void *blob); int validate_dramc_param(const void *blob); diff --git a/src/soc/mediatek/mt8195/include/soc/dramc_param.h b/src/soc/mediatek/mt8195/include/soc/dramc_param.h index 7c66b70..0885ee0 100644 --- a/src/soc/mediatek/mt8195/include/soc/dramc_param.h +++ b/src/soc/mediatek/mt8195/include/soc/dramc_param.h @@ -73,7 +73,6 @@ struct dramc_data dramc_datas; }; -const struct sdram_info *get_sdram_config(void); struct dramc_param *get_dramc_param_from_blob(void *blob); void dump_param_header(const void *blob); int validate_dramc_param(const void *blob); -- To view, visit https://review.coreboot.org/c/coreboot/+/80687?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I05a01b1ab13fbf19b2a908c48a540a5c2e1ccbdc Gerrit-Change-Number: 80687 Gerrit-PatchSet: 5 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Crystal Guo <crystal.guo(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Xixi Chen <xixi.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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coreboot-gerrit February 2024