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Change subject: cpu/x86: Link page tables in stage if possible
......................................................................
Patch Set 9: Code-Review+2
(1 comment)
File src/mainboard/emulation/qemu-q35/Kconfig:
https://review.coreboot.org/c/coreboot/+/80337/comment/29b865b4_cc5dc7e5 :
PS8, Line 35: PAGE_TABLES_IN_CBFS
> not mentioned in commit message why emulated targets need page tables in CBFS
Done
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Hello Felix Held, Fred Reitberger, Jason Glenesk, Jérémy Compostella, Matt DeVillier, Patrick Rudolph, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: cpu/x86: Link page tables in stage if possible
......................................................................
cpu/x86: Link page tables in stage if possible
When switching back and forward from 32 to 64, for example to call a
32bit FSP or toe call the payload, a new page tables in the respective
stage will be linked.
The advantages of this approach are:
- No need to determine a good place for page tables in cbfs that does
not overlap.
- Works with non memory mapped flash (however all coreboot targets
currently do support this)
- If later stages can use their own page tables which fits better with
the vboot RO/RW flow
A disadvantage is that it increases the stage size. This could be
improved upon by used 1G pages and generating the pages at runtime.
Note: qemu cannot have the page tables in the RO boot medium and needs
to relocate them at runtime. This is why keeping the existing code with
page tables in cbfs is done for now.
TESTED on google/vilbox and qemu/q35: boots to payload
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
Change-Id: Ied54b66b930187cba5fbc578a81ed5859a616562
---
M src/arch/x86/Kconfig
M src/cpu/intel/car/core2/cache_as_ram.S
M src/cpu/intel/car/non-evict/cache_as_ram.S
M src/cpu/intel/car/p4-netburst/cache_as_ram.S
M src/cpu/x86/64bit/Makefile.mk
M src/cpu/x86/64bit/entry64.inc
M src/cpu/x86/64bit/mode_switch.S
M src/cpu/x86/64bit/mode_switch2.S
M src/cpu/x86/64bit/pt.S
M src/mainboard/emulation/qemu-i440fx/Kconfig
M src/mainboard/emulation/qemu-q35/Kconfig
M src/soc/amd/common/block/cpu/noncar/pre_c.S
M src/soc/intel/common/block/cpu/car/cache_as_ram.S
13 files changed, 25 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/80337/9
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Change subject: mb/google/brya/var/xol: Change clock source index for NVME
......................................................................
mb/google/brya/var/xol: Change clock source index for NVME
Change ClkSrc index for NVME to 0 from 1 by referring to proto2
schematics.
BUG=b:326481458
BRANCH=firmware-brya-14505.B
TEST=FW_NAME=xol emerge-brya coreboot chromeos-bootimage
Change-Id: I7ea1cd7d8e16d4cee953e931d2f1829eae7d1978
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---
M src/mainboard/google/brya/variants/xol/overridetree.cb
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git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/80768/2
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Change subject: cpu/x86: Link page tables in stage if possible
......................................................................
Patch Set 8: Code-Review+2
(1 comment)
File src/mainboard/emulation/qemu-q35/Kconfig:
https://review.coreboot.org/c/coreboot/+/80337/comment/fbca334a_cb5b80b0 :
PS8, Line 35: PAGE_TABLES_IN_CBFS
not mentioned in commit message why emulated targets need page tables in CBFS
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Change subject: cpu/x86/(sipi|smm): Pass on CR3 from ramstage
......................................................................
Patch Set 5:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/80335/comment/e788e7cd_2156a143 :
PS5, Line 8:
Some motivation for the engineers not to deep into the topic why this change is beneficial would be nice.
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Patch Set 5: Code-Review+2
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Change subject: mb/google/brya/var/xol: Add storage option in FW_CONFIG
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Patch Set 1: Code-Review+2
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