coreboot-gerrit February 2024

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[M] Change in coreboot[main]: device/pciexp_device.c: Fix setting Max Payload Size
by Matt DeVillier (Code Review) 27 Feb '24

27 Feb '24

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/77338?usp=email ) Change subject: device/pciexp_device.c: Fix setting Max Payload Size ...................................................................... device/pciexp_device.c: Fix setting Max Payload Size Current implementation assumes that the endpoint device is connected directly to the PCIe Root Port, which does not always have to be true. In a case where there is a PCIe switch between the endpoint and the root port, the Max Payload Size capability may differ across the devices in the chain and coreboot will not set a correct Max Payload Size. This results in a PCIe device malfunction in pre-OS environment, e.g. if the Ethernet NICs are connected behind a PCIe switch, the iPXE fails to obtain the DHCP configuration. Fix this by traversing the topology and programming the highest common Max Payload Size in the given PCIe device chain during enumeration. Once finished, the root port has the highest common Max Payload Size supported by all the devices in the chain. So at the end of root port bus scan, propagate the root port's Max Payload Size to all downstream devices to keep Max Payload Size in sync within the whole chain. TEST=Perform successful dhcp command in iPXE on the NIC connected to the PCIe root port via ASMedia ASM1806 PCIe switch and again on the NIC connected directly to the PCIe root port. Change-Id: I24386dc208363b7d94fea46dec25c231a3968225 Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77338 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Krystian Hebel <krystian.hebel(a)3mdeb.com> --- M src/device/pciexp_device.c 1 file changed, 134 insertions(+), 29 deletions(-) Approvals: build bot (Jenkins): Verified Krystian Hebel: Looks good to me, approved diff --git a/src/device/pciexp_device.c b/src/device/pciexp_device.c index 969dbb00..db351ef 100644 --- a/src/device/pciexp_device.c +++ b/src/device/pciexp_device.c @@ -144,6 +144,35 @@ return from; } +static bool pcie_is_root_port(struct device *dev) +{ + unsigned int pcie_pos, pcie_type; + + pcie_pos = pci_find_capability(dev, PCI_CAP_ID_PCIE); + if (!pcie_pos) + return false; + + pcie_type = pci_read_config16(dev, pcie_pos + PCI_EXP_FLAGS) & PCI_EXP_FLAGS_TYPE; + pcie_type >>= 4; + + return (pcie_type == PCI_EXP_TYPE_ROOT_PORT); +} + +static bool pcie_is_endpoint(struct device *dev) +{ + unsigned int pcie_pos, pcie_type; + + pcie_pos = pci_find_capability(dev, PCI_CAP_ID_PCIE); + if (!pcie_pos) + return false; + + pcie_type = pci_read_config16(dev, pcie_pos + PCI_EXP_FLAGS) & PCI_EXP_FLAGS_TYPE; + pcie_type >>= 4; + + return ((pcie_type == PCI_EXP_TYPE_ENDPOINT) || (pcie_type == PCI_EXP_TYPE_LEG_END)); +} + + /* * Re-train a PCIe link */ @@ -561,26 +590,63 @@ printk(BIOS_INFO, "ASPM: Enabled %s\n", aspm_type_str[apmc]); } -/* - * Set max payload size of endpoint in accordance with max payload size of root port. - */ -static void pciexp_set_max_payload_size(struct device *root, unsigned int root_cap, - struct device *endp, unsigned int endp_cap) +static void pciexp_dev_set_max_payload_size(struct device *dev, unsigned int max_payload) { - unsigned int endp_max_payload, root_max_payload, max_payload; - u16 endp_devctl, root_devctl; - u32 endp_devcap, root_devcap; + u16 devctl; + unsigned int pcie_cap = pci_find_capability(dev, PCI_CAP_ID_PCIE); - /* Get max payload size supported by endpoint */ - endp_devcap = pci_read_config32(endp, endp_cap + PCI_EXP_DEVCAP); - endp_max_payload = endp_devcap & PCI_EXP_DEVCAP_PAYLOAD; + if (!pcie_cap) + return; - /* Get max payload size supported by root port */ - root_devcap = pci_read_config32(root, root_cap + PCI_EXP_DEVCAP); - root_max_payload = root_devcap & PCI_EXP_DEVCAP_PAYLOAD; + devctl = pci_read_config16(dev, pcie_cap + PCI_EXP_DEVCTL); + devctl &= ~PCI_EXP_DEVCTL_PAYLOAD; + /* + * Should never overflow to higher bits, due to how max_payload is + * guarded in this file. + */ + devctl |= max_payload << 5; + pci_write_config16(dev, pcie_cap + PCI_EXP_DEVCTL, devctl); +} - /* Set max payload to smaller of the reported device capability. */ - max_payload = MIN(endp_max_payload, root_max_payload); +static unsigned int pciexp_dev_get_current_max_payload_size(struct device *dev) +{ + u16 devctl; + unsigned int pcie_cap = pci_find_capability(dev, PCI_CAP_ID_PCIE); + + if (!pcie_cap) + return 0; + + devctl = pci_read_config16(dev, pcie_cap + PCI_EXP_DEVCTL); + devctl &= PCI_EXP_DEVCTL_PAYLOAD; + return (devctl >> 5); +} + +static unsigned int pciexp_dev_get_max_payload_size_cap(struct device *dev) +{ + u16 devcap; + unsigned int pcie_cap = pci_find_capability(dev, PCI_CAP_ID_PCIE); + + if (!pcie_cap) + return 0; + + devcap = pci_read_config16(dev, pcie_cap + PCI_EXP_DEVCAP); + return (devcap & PCI_EXP_DEVCAP_PAYLOAD); +} + +/* + * Set max payload size of a parent based on max payload size capability of the child. + */ +static void pciexp_configure_max_payload_size(struct device *parent, struct device *child) +{ + unsigned int child_max_payload, parent_max_payload, max_payload; + + /* Get max payload size supported by child */ + child_max_payload = pciexp_dev_get_current_max_payload_size(child); + /* Get max payload size configured by parent */ + parent_max_payload = pciexp_dev_get_current_max_payload_size(parent); + /* Set max payload to smaller of the reported device capability or parent config. */ + max_payload = MIN(child_max_payload, parent_max_payload); + if (max_payload > 5) { /* Values 6 and 7 are reserved in PCIe 3.0 specs. */ printk(BIOS_ERR, "PCIe: Max_Payload_Size field restricted from %d to 5\n", @@ -588,17 +654,11 @@ max_payload = 5; } - endp_devctl = pci_read_config16(endp, endp_cap + PCI_EXP_DEVCTL); - endp_devctl &= ~PCI_EXP_DEVCTL_PAYLOAD; - endp_devctl |= max_payload << 5; - pci_write_config16(endp, endp_cap + PCI_EXP_DEVCTL, endp_devctl); - - root_devctl = pci_read_config16(root, root_cap + PCI_EXP_DEVCTL); - root_devctl &= ~PCI_EXP_DEVCTL_PAYLOAD; - root_devctl |= max_payload << 5; - pci_write_config16(root, root_cap + PCI_EXP_DEVCTL, root_devctl); - - printk(BIOS_INFO, "PCIe: Max_Payload_Size adjusted to %d\n", (1 << (max_payload + 7))); + if (max_payload != parent_max_payload) { + pciexp_dev_set_max_payload_size(parent, max_payload); + printk(BIOS_INFO, "%s: Max_Payload_Size adjusted to %d\n", dev_path(parent), + (1 << (max_payload + 7))); + } } /* @@ -658,19 +718,47 @@ if (CONFIG(PCIEXP_LANE_ERR_STAT_CLEAR)) clear_lane_error_status(root); - /* Adjust Max_Payload_Size of link ends. */ - pciexp_set_max_payload_size(root, root_cap, dev, cap); + /* Set the Max Payload Size to the maximum supported capability for this device */ + if (pcie_is_endpoint(dev)) + pciexp_dev_set_max_payload_size(dev, pciexp_dev_get_max_payload_size_cap(dev)); + + /* Limit the parent's Max Payload Size if needed */ + pciexp_configure_max_payload_size(root, dev); pciexp_configure_ltr(root, root_cap, dev, cap); } +static void pciexp_sync_max_payload_size(struct bus *bus, unsigned int max_payload) +{ + struct device *child; + + /* Set the max payload for children on the bus and their children, etc. */ + for (child = bus->children; child; child = child->sibling) { + if (!is_pci(child)) + continue; + + pciexp_dev_set_max_payload_size(child, max_payload); + + if (child->downstream) + pciexp_sync_max_payload_size(child->downstream, max_payload); + } +} + void pciexp_scan_bus(struct bus *bus, unsigned int min_devfn, unsigned int max_devfn) { struct device *child; + unsigned int max_payload; pciexp_enable_ltr(bus->dev); + /* + * Set the Max Payload Size to the maximum supported capability for this bridge. + * This value will be used in pciexp_tune_dev to limit the Max Payload size if needed. + */ + max_payload = pciexp_dev_get_max_payload_size_cap(bus->dev); + pciexp_dev_set_max_payload_size(bus->dev, max_payload); + pci_scan_bus(bus, min_devfn, max_devfn); for (child = bus->children; child; child = child->sibling) { @@ -682,6 +770,23 @@ } pciexp_tune_dev(child); } + + /* + * Now the root port's Max Payload Size should be set to the highest + * possible value supported by all devices under a given root port. + * Propagate that value down from root port to all devices, so the Max + * Payload Size is equal on all devices, as some devices may have + * different capabilities and the programmed value depends on the + * order of device population the in the subtree. + */ + if (pcie_is_root_port(bus->dev)) { + max_payload = pciexp_dev_get_current_max_payload_size(bus->dev); + + printk(BIOS_INFO, "%s: Setting Max_Payload_Size to %d for devices under this" + " root port\n", dev_path(bus->dev), 1 << (max_payload + 7)); + + pciexp_sync_max_payload_size(bus, max_payload); + } } void pciexp_scan_bridge(struct device *dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/77338?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I24386dc208363b7d94fea46dec25c231a3968225 Gerrit-Change-Number: 77338 Gerrit-PatchSet: 22 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: mb/qemu/fw_cfg: Use fw_cfg_read() to read SMBIOS data
by Matt DeVillier (Code Review) 27 Feb '24

27 Feb '24

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80367?usp=email ) Change subject: mb/qemu/fw_cfg: Use fw_cfg_read() to read SMBIOS data ...................................................................... mb/qemu/fw_cfg: Use fw_cfg_read() to read SMBIOS data The QEMU firmware configuration driver can help initialize SMBIOS tables using the table data that QEMU provides over the device. While doing so, it reads from the device "file" manually using port-based IO. Use the fw_cfg_read() helper function to read the SMBIOS-related file, so that the driver is easier to port the driver to other architectures. Change-Id: I18e60b8e9de34f2b0ff67af4113beec1d7467329 Signed-off-by: Alper Nebi Yasak <alpernebiyasak(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80367 Reviewed-by: Nico Huber <nico.h(a)gmx.de> Reviewed-by: Martin L Roth <gaumless(a)gmail.com> Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/emulation/qemu-i440fx/fw_cfg.c 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: Martin L Roth: Looks good to me, approved Matt DeVillier: Looks good to me, approved build bot (Jenkins): Verified Nico Huber: Looks good to me, but someone else must approve diff --git a/src/mainboard/emulation/qemu-i440fx/fw_cfg.c b/src/mainboard/emulation/qemu-i440fx/fw_cfg.c index 0f217cc..a15773c 100644 --- a/src/mainboard/emulation/qemu-i440fx/fw_cfg.c +++ b/src/mainboard/emulation/qemu-i440fx/fw_cfg.c @@ -362,9 +362,9 @@ fw_cfg_get(FW_CFG_SMBIOS_ENTRIES, &count, sizeof(count)); for (i = 0; i < count; i++) { - insb(FW_CFG_PORT_DATA, &entry, sizeof(entry)); + fw_cfg_read(&entry, sizeof(entry)); buf = malloc(entry.length - sizeof(entry)); - insb(FW_CFG_PORT_DATA, buf, entry.length - sizeof(entry)); + fw_cfg_read(buf, entry.length - sizeof(entry)); if (entry.headertype == SMBIOS_FIELD_ENTRY && entry.tabletype == 1) { switch (entry.fieldoffset) { -- To view, visit https://review.coreboot.org/c/coreboot/+/80367?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I18e60b8e9de34f2b0ff67af4113beec1d7467329 Gerrit-Change-Number: 80367 Gerrit-PatchSet: 2 Gerrit-Owner: Alper Nebi Yasak <alpernebiyasak(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: mb/qemu/fw_cfg: Use fw_cfg_read() to read SMBIOS data
by Matt DeVillier (Code Review) 27 Feb '24

27 Feb '24

Attention is currently required from: Alper Nebi Yasak. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80367?usp=email ) Change subject: mb/qemu/fw_cfg: Use fw_cfg_read() to read SMBIOS data ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/80367?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I18e60b8e9de34f2b0ff67af4113beec1d7467329 Gerrit-Change-Number: 80367 Gerrit-PatchSet: 1 Gerrit-Owner: Alper Nebi Yasak <alpernebiyasak(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Alper Nebi Yasak <alpernebiyasak(a)gmail.com> Gerrit-Comment-Date: Tue, 27 Feb 2024 20:22:14 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/qemu/fw_cfg: Fix build when not generating SMBIOS tables
by Matt DeVillier (Code Review) 27 Feb '24

27 Feb '24

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80366?usp=email ) Change subject: mb/qemu/fw_cfg: Fix build when not generating SMBIOS tables ...................................................................... mb/qemu/fw_cfg: Fix build when not generating SMBIOS tables Parts of the QEMU firmware configuration device driver refers to SMBIOS related kconfig values. These depend on GENERATE_SMBIOS_TABLES and are undefined if it isn't enabled, causing a build error. Cover the SMBIOS-related region in this driver with an #if directive checking the necessary config option. This is mostly to help port the driver to non-x86 architectures where support for generating SMBIOS tables isn't there yet. Change-Id: I3ff388d4574eb52686a5dda3dcbc3d64a7ce6f7b Signed-off-by: Alper Nebi Yasak <alpernebiyasak(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80366 Reviewed-by: Martin L Roth <gaumless(a)gmail.com> Reviewed-by: Nico Huber <nico.h(a)gmx.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/emulation/qemu-i440fx/fw_cfg.c 1 file changed, 2 insertions(+), 0 deletions(-) Approvals: Nico Huber: Looks good to me, but someone else must approve build bot (Jenkins): Verified Martin L Roth: Looks good to me, approved diff --git a/src/mainboard/emulation/qemu-i440fx/fw_cfg.c b/src/mainboard/emulation/qemu-i440fx/fw_cfg.c index 5c23988..0f217cc 100644 --- a/src/mainboard/emulation/qemu-i440fx/fw_cfg.c +++ b/src/mainboard/emulation/qemu-i440fx/fw_cfg.c @@ -341,6 +341,7 @@ /* ---------------------------------------------------------------------- */ /* pick up smbios information from fw_cfg */ +#if CONFIG(GENERATE_SMBIOS_TABLES) static const char *type1_manufacturer; static const char *type1_product_name; static const char *type1_version; @@ -504,6 +505,7 @@ fw_cfg_smbios_init(); memcpy(uuid, type1_uuid, 16); } +#endif /* CONFIG(GENERATE_SMBIOS_TABLES) */ /* * Configure DMA setup -- To view, visit https://review.coreboot.org/c/coreboot/+/80366?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3ff388d4574eb52686a5dda3dcbc3d64a7ce6f7b Gerrit-Change-Number: 80366 Gerrit-PatchSet: 2 Gerrit-Owner: Alper Nebi Yasak <alpernebiyasak(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[main]: Docs/releases: Finalize 24.02 release notes
by Matt DeVillier (Code Review) 27 Feb '24

27 Feb '24

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80751?usp=email ) Change subject: Docs/releases: Finalize 24.02 release notes ...................................................................... Docs/releases: Finalize 24.02 release notes Change-Id: I5ba6619ee7ed408a33548ab5b6f7d2a2143e88e7 Signed-off-by: Martin Roth <gaumless(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80751 Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M Documentation/releases/coreboot-24.02-relnotes.md 1 file changed, 20 insertions(+), 20 deletions(-) Approvals: Felix Singer: Looks good to me, approved build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved diff --git a/Documentation/releases/coreboot-24.02-relnotes.md b/Documentation/releases/coreboot-24.02-relnotes.md index d941e2c..eb5349e 100644 --- a/Documentation/releases/coreboot-24.02-relnotes.md +++ b/Documentation/releases/coreboot-24.02-relnotes.md @@ -1,10 +1,7 @@ -Upcoming release - coreboot 24.02 +coreboot 24.02 release ======================================================================== -The 24.02 release is scheduled for February 19, 2024. The next release, -which will be 24.05, is scheduled for mid-May. - -The coreboot project is happy to announce our next release for February +The coreboot project is happy to announce our release for February 2024. Over the past three months, our contributors have focused on refining the coreboot codebase, generally prioritizing cleanup and quality enhancements. We extend our gratitude to all the contributors @@ -12,6 +9,8 @@ invaluable contributions to this vital phase of maintenance and optimization. +The next release is scheduled for mid-May. + ### Release number format update @@ -127,9 +126,9 @@ ### Toolchain updates * Add buildgcc support for Apple M1/M2 devices -* crossgcc: Upgrade GCC from 11.4.0 to 13.2.0 -* util/crossgcc: Update CMake from 3.26.4 to 3.27.7 -* util/kconfig: Uprev to Linux 6.7 kconfig +* Upgrade GCC from 11.4.0 to 13.2.0 +* Update CMake from 3.26.4 to 3.27.7 +* Uprev to Kconfig from Linux 6.7 ### Git submodule pointers @@ -140,9 +139,9 @@ 17bef2248d (701 commits) * /3rdparty/fsp: Update from commit id 481ea7cf0b to 507ef01cce (16 commits) * /3rdparty/intel-microcode: Update from commit id 6788bb07eb to - ece0d294a2 (1 commits) -* /3rdparty/vboot: Update from commit id 24cb127a5e to 3d37d2aafe (121 - commits) + ece0d294a2 (1 commit) +* /3rdparty/vboot: Update from commit id 24cb127a5e to 3d37d2aafe + (121 commits) ### External payloads @@ -168,15 +167,15 @@ Statistics from the 4.22 to the 24.02 release -------------------------------------------- -* Total Commits: 814 -* Average Commits per day: 8.65 -* Total lines added: 105203 -* Average lines added per commit: 129.24 -* Number of patches adding more than 100 lines: 46 +* Total Commits: 815 +* Average Commits per day: 8.63 +* Total lines added: 105433 +* Average lines added per commit: 129.37 +* Number of patches adding more than 100 lines: 47 * Average lines added per small commit: 41.34 -* Total lines removed: 16505 -* Average lines removed per commit: 20.28 -* Total difference between added and removed: 88698 +* Total lines removed: 16534 +* Average lines removed per commit: 20.29 +* Total difference between added and removed: 88899 * Total authors: 111 * New authors: 19 @@ -185,7 +184,8 @@ Significant Known and Open Issues --------------------------------- -* AMD chromebooks will not currently work with the signed vboot image. +* AMD chromebooks will not work with the signed PSP_verstage images and + the version of verstage used in coreboot 24.02. ## Issues from the coreboot bugtracker: https://ticket.coreboot.org/ -- To view, visit https://review.coreboot.org/c/coreboot/+/80751?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5ba6619ee7ed408a33548ab5b6f7d2a2143e88e7 Gerrit-Change-Number: 80751 Gerrit-PatchSet: 2 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: device/pnp_device: Demote unassigned resource printk to NOTICE
by Matt DeVillier (Code Review) 27 Feb '24

27 Feb '24

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80645?usp=email ) Change subject: device/pnp_device: Demote unassigned resource printk to NOTICE ...................................................................... device/pnp_device: Demote unassigned resource printk to NOTICE Often times not all available resources are used on a PNP function, so those resources not being specified is intentional, not an error. Keep the printk but demote it so it doesn't pollute a normal cbmem log. TEST=build/boot purism/librem_cnl (Mini v2), verify errors in cbmem related to RTC IO/IRQ not being assigned are no longer present. Change-Id: I3d9f22a06088596e14680190aede2d69880001fa Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80645 Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nico Huber <nico.h(a)gmx.de> --- M src/device/pnp_device.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: Felix Singer: Looks good to me, approved Nico Huber: Looks good to me, but someone else must approve build bot (Jenkins): Verified diff --git a/src/device/pnp_device.c b/src/device/pnp_device.c index f799530..c7c6228 100644 --- a/src/device/pnp_device.c +++ b/src/device/pnp_device.c @@ -130,7 +130,7 @@ resource->index, resource_type(resource), resource->size); else - printk(BIOS_ERR, "%s %02lx %s size: 0x%010llx " + printk(BIOS_NOTICE, "%s %02lx %s size: 0x%010llx " "not assigned in devicetree\n", dev_path(dev), resource->index, resource_type(resource), resource->size); return; -- To view, visit https://review.coreboot.org/c/coreboot/+/80645?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3d9f22a06088596e14680190aede2d69880001fa Gerrit-Change-Number: 80645 Gerrit-PatchSet: 3 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: soc/intel/common/lpc: Don't open a window for unassigned resources
by Matt DeVillier (Code Review) 27 Feb '24

27 Feb '24

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80750?usp=email ) Change subject: soc/intel/common/lpc: Don't open a window for unassigned resources ...................................................................... soc/intel/common/lpc: Don't open a window for unassigned resources Don't attempt to open a PMIO window for a resource which doesn't have the IORESOURCE_ASSIGNED flag set, since there is no point in doing so and there's a high likelihood that the base address is 0, which will throw an error. TEST=build/boot purism/librem_cnl (Mini v2), ensure no errors in cbmem log for attempting to open a PMIO window for unaassigned resources with base address 0. Change-Id: Ifba14a8f134ba12d5f5e9fdbac775d4f82b4c4de Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80750 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Reviewed-by: Nico Huber <nico.h(a)gmx.de> --- M src/soc/intel/common/block/lpc/lpc.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: Felix Singer: Looks good to me, approved build bot (Jenkins): Verified Nico Huber: Looks good to me, but someone else must approve diff --git a/src/soc/intel/common/block/lpc/lpc.c b/src/soc/intel/common/block/lpc/lpc.c index b27e09e9..e805035 100644 --- a/src/soc/intel/common/block/lpc/lpc.c +++ b/src/soc/intel/common/block/lpc/lpc.c @@ -91,7 +91,7 @@ return; for (res = dev->resource_list; res; res = res->next) { - if (res->flags & IORESOURCE_IO) + if ((res->flags & IORESOURCE_IO) && (res->flags & IORESOURCE_ASSIGNED)) lpc_open_pmio_window(res->base, res->size); } pch_lpc_set_child_resources(dev); -- To view, visit https://review.coreboot.org/c/coreboot/+/80750?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifba14a8f134ba12d5f5e9fdbac775d4f82b4c4de Gerrit-Change-Number: 80750 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: mb/system76/adl,rpl: Add timeouts for PCIe 3.0 RPs
by Paul Menzel (Code Review) 27 Feb '24

27 Feb '24

Attention is currently required from: Jeremy Soller, Tim Crawford. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80756?usp=email ) Change subject: mb/system76/adl,rpl: Add timeouts for PCIe 3.0 RPs ...................................................................... Patch Set 1: (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/80756/comment/07e1592b_8f55aa5c : PS1, Line 7: Add timeouts for PCIe 3.0 RPs : Maybe: > Add 50 ms timeouts for PCIe 3.0 RPs https://review.coreboot.org/c/coreboot/+/80756/comment/895be8d3_31d7097f : PS1, Line 14: Tested on lemp12 with Samsung 980 PRO and 990 PRO drives. What drive firmware versions? https://review.coreboot.org/c/coreboot/+/80756/comment/7b43751d_ea1fb68f : PS1, Line 15: Is there a default time-out value? Why 50 ms and not another value? File src/mainboard/system76/adl/variants/darp8/overridetree.cb: https://review.coreboot.org/c/coreboot/+/80756/comment/08282b45_21fa1e06 : PS1, Line 155: .pcie_rp_detect_timeout_ms = 50, Is there a default timeout? -- To view, visit https://review.coreboot.org/c/coreboot/+/80756?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4f44fc429c52e407b7566d6bb6dd31b2cf85c48d Gerrit-Change-Number: 80756 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Comment-Date: Tue, 27 Feb 2024 20:17:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[main]: ec/chromeec: Enable auto fan control on startup
by Matt DeVillier (Code Review) 27 Feb '24

27 Feb '24

Attention is currently required from: Forest Mittelberg, Matt DeVillier. Hello Caveh Jalali, Forest Mittelberg, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/80712?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Code-Review+1 by Forest Mittelberg, Verified+1 by build bot (Jenkins) Change subject: ec/chromeec: Enable auto fan control on startup ...................................................................... ec/chromeec: Enable auto fan control on startup Several older ChromeOS boards have issues with fan control on cold boot and/or on S3 resume, so add functionality to allow those boards to programmatically enable auto fan control. TEST=build/boot google/link, verify fan ramps up/down accordingly with CPU load. Change-Id: I08a8562531f8af0c71230477d0221d536443f096 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/ec/google/chromeec/Kconfig M src/ec/google/chromeec/ec.c 2 files changed, 11 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/80712/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/80712?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I08a8562531f8af0c71230477d0221d536443f096 Gerrit-Change-Number: 80712 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Forest Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Forest Mittelberg <bmbm(a)google.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: util/crossgcc: Use ninja to build llvm/clang
by Felix Singer (Code Review) 27 Feb '24

27 Feb '24

Attention is currently required from: Arthur Heymans, Martin L Roth, Maximilian Brune. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80731?usp=email ) Change subject: util/crossgcc: Use ninja to build llvm/clang ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > I did 4 measurements (2 each) with 8 jobs on a machine that did nothing besides building the toolcha […] I also did some test builds using 32 threads and 128 GiB RAM. Using Ninja ``` real 17m19.320s user 477m53.363s sys 23m44.042s ``` Using Make ``` real 17m41.831s user 470m21.309s sys 23m52.428s ``` An improvement is not really noticeable here. So I rather would like to find a different reason for this change. Is Ninja the preferred build system? Or maybe the successor of Make? -- To view, visit https://review.coreboot.org/c/coreboot/+/80731?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I66d2a4e6e5c265f5580a74e59309e2ad8b1f1f61 Gerrit-Change-Number: 80731 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Tue, 27 Feb 2024 19:56:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-MessageType: comment

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