coreboot-gerrit February 2024

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[M] Change in coreboot[main]: vc/google/chromeos: Implement dynamic ChromeOS boot logo selection
by Subrata Banik (Code Review) 27 Feb '24

27 Feb '24

Attention is currently required from: Gwendal Grignou, Paul Menzel, Paz Zcharya. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80738?usp=email ) Change subject: vc/google/chromeos: Implement dynamic ChromeOS boot logo selection ...................................................................... Patch Set 7: (3 comments) File src/vendorcode/google/chromeos/tpm_factory_config.c: https://review.coreboot.org/c/coreboot/+/80738/comment/7ffce01d_6b5a41db : PS7, Line 49: * - Bits 3-0 (0x1): Must be 0x1 to signify compliance with Chromebook-Plus > To be future-proof, the test on line 61 should be > > `return factory_config & CHROMEBOOK_PLUS_DEVICE;` If you read the bug ticket number attached to the commit message, you will see that the issue this CL aims to remedy is due to the fact that we were originally returning `return factory_config & CHROMEBOOK_PLUS_DEVICE;` When we `return factory_config & CHROMEBOOK_PLUS_DEVICE;`, that means we are considering a device qualified as CBX if `Bit 4 is set` or `Bit 0-3 is set` or `both are set`. However, in practice, we have seen devices that are CBX HW compliant (bit 0-3) but are not branded as CBX. As a result, we are displaying the CBX logo instead of the correct device segment logo (CB). This CL is intended to fix that issue, as described in the commit message. - If the GSC bit indicates that both Bit-4 and Bit 0-3 are set to 1, then we know that this is a HW branded CBX. - If bit 0-3 is set, then it can be either a SB CBX or a regular CB. To detect which one it is properly, we are relying on VPD read. - If none of the above logic is being met, then this device is definitely a CB. https://review.coreboot.org/c/coreboot/+/80738/comment/573b8520_777971c1 : PS7, Line 74: * requirement. > I assume the design doc is at `go/cros-tiering-dd`. > If this CL only applies to new chromebook that have identification in their GSC where `chassis_x_branded` and `hw_x_compliance_version` are properly set, then we don't need to read the VPD at all. > Per design [see section `OS Runtime flow`], all the information we need in the GSC. Please read go/multi-logo-fw-splash-screen doc. and also as explained https://review.coreboot.org/c/coreboot/+/80738/comment/d8b19982_593d16b0/, we intended to relying on GSC for decision making but there are few corner case which forces us to still reading the VPD. ``` +--------------------------------------------------------------------------------------------------------+---------------------------------------------+---------------------+---------------------------+-------------------------+ | Devices | Config selection | Factory Config | | Feature_Device_Info VPD | +--------------------------------------------------------------------------------------------------------+---------------------------------------------+---------------------+---------------------------+-------------------------+ | Legacy Devices | CONFIG_BMP_LOGO=y, CONFIG_FSP2_0_LOGO_FILE | X | X | “CAE” | | Devices with Chromebook (no-CBX and no X-components) | CONFIG_FW_SPLASH_SCREEN=y, CONFIG_CB_LOGO= | chassis_x_branded=0 | hw_x_compliance_version=0 | “CAE” | | Devices Compliant with CBX HW Spec but treated Legacy (Soft Branded Legacy) | CONFIG_FW_SPLASH_SCREEN=y ,CONFIG_CBX_LOGO= | chassis_x_branded=0 | hw_x_compliance_version=1 | “CAE” | | Devices Compliant with CBX HW Spec and Waived as CBX (Soft Branded Waived Device) aka Soft-branded CBX | CONFIG_FW_SPLASH_SCREEN=y, CONFIG_CBX_LOGO= | chassis_x_branded=0 | hw_x_compliance_version=1 | “CAI” | | Devices with Hard Chromebook-Plus branding | CONFIG_FW_SPLASH_SCREEN=y, CONFIG_CBX_LOGO= | chassis_x_branded=1 | hw_x_compliance_version=1 | “CAI” | +--------------------------------------------------------------------------------------------------------+---------------------------------------------+---------------------+---------------------------+-------------------------+ ``` https://review.coreboot.org/c/coreboot/+/80738/comment/044e5b5e_4a29fbed : PS7, Line 104: return strncmp(vpd_get_feature_device_info(), "CAI", 3) == 0; > The previous comment states "all older devices will have legacy config", so we don't need the non-GSC bit parsing logic, do we? we are relying on non GSC bit parsing aka VPD logic to uniquely identify the #2 (below) if the HW complaint device is branded as SB CBX or regular CB device. SB CBX device 1. The device is compliant to the Chromebook-Plus Hardware Specification. 2. Product requirement makes this device qualified as Chromebook-Plus. Regular Chromebook device 1. Device is compliant to the Chromebook-Plus Hardware Specification. 2. Product requirement makes this device to act as Chromebook (it can be branded CBX later if required) -- To view, visit https://review.coreboot.org/c/coreboot/+/80738?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9bb1e868764738333977bd8c990bea4253c9d37b Gerrit-Change-Number: 80738 Gerrit-PatchSet: 7 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Gwendal Grignou <gwendal(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Paz Zcharya <pazz(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Paz Zcharya <pazz(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Gwendal Grignou <gwendal(a)chromium.org> Gerrit-Comment-Date: Wed, 28 Feb 2024 06:44:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Gwendal Grignou <gwendal(a)chromium.org> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: mb/google/brox: support ISH
by Ashish Kumar Mishra (Code Review) 27 Feb '24

27 Feb '24

Attention is currently required from: Ashish Kumar Mishra, Li1 Feng. Ashish Kumar Mishra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80773?usp=email ) Change subject: mb/google/brox: support ISH ...................................................................... Patch Set 1: (1 comment) File src/mainboard/google/brox/mainboard.c: https://review.coreboot.org/c/coreboot/+/80773/comment/f1178bca_f7657391 : PS1, Line 86: Could remove this blank line. -- To view, visit https://review.coreboot.org/c/coreboot/+/80773?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iadc5108c62737d27642a6948c00b5c122541aaba Gerrit-Change-Number: 80773 Gerrit-PatchSet: 1 Gerrit-Owner: Li1 Feng <li1.feng(a)intel.com> Gerrit-Reviewer: Ashish Kumar Mishra <ashish.k.mishra(a)intel.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Attention: Li1 Feng <li1.feng(a)intel.com> Gerrit-Attention: Ashish Kumar Mishra <ashish.k.mishra(a)intel.corp-partner.google.com> Gerrit-Comment-Date: Wed, 28 Feb 2024 06:44:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[main]: mb/google/brox: support ISH
by Li1 Feng (Code Review) 27 Feb '24

27 Feb '24

Li1 Feng has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80773?usp=email ) Change subject: mb/google/brox: support ISH ...................................................................... mb/google/brox: support ISH Set FW_CONFIG bit 21 to enable ISH PCI device and define ISH main firmware name so ISH shim loader can load firmware from file system. ISH also need to be enabled if STORAGE_UFS is set. BUG=b:280329972 TEST= Set bit CBI FW_CONFIG bit 21 Boot Brox board, check that ISH is enabled and loaded lspci shows: 00:12.0 Serial controller: Intel Corporation Alder Lake-P Integrated Sensor Hub (rev 01). Change-Id: Iadc5108c62737d27642a6948c00b5c122541aaba Signed-off-by: Li Feng <li1.feng(a)intel.com> --- M src/mainboard/google/brox/mainboard.c M src/mainboard/google/brox/variants/baseboard/brox/gpio.c M src/mainboard/google/brox/variants/brox/fw_config.c M src/mainboard/google/brox/variants/brox/overridetree.cb 4 files changed, 58 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/80773/1 diff --git a/src/mainboard/google/brox/mainboard.c b/src/mainboard/google/brox/mainboard.c index 5820805..8693bea 100644 --- a/src/mainboard/google/brox/mainboard.c +++ b/src/mainboard/google/brox/mainboard.c @@ -80,10 +80,15 @@ const struct pad_config *base_pads; const struct pad_config *override_pads; size_t base_num, override_num; + struct pad_config *padbased_table; + + padbased_table = new_padbased_table(); base_pads = variant_gpio_table(&base_num); override_pads = variant_gpio_override_table(&override_num); + fw_config_gpio_padbased_override(padbased_table); gpio_configure_pads_with_override(base_pads, base_num, override_pads, override_num); + free(padbased_table); } static void mainboard_init(void *chip_info) diff --git a/src/mainboard/google/brox/variants/baseboard/brox/gpio.c b/src/mainboard/google/brox/variants/baseboard/brox/gpio.c index 337fde1..d0277e0 100644 --- a/src/mainboard/google/brox/variants/baseboard/brox/gpio.c +++ b/src/mainboard/google/brox/variants/baseboard/brox/gpio.c @@ -68,7 +68,7 @@ /* GPP_A15 : [NF1: USB_OC2# NF2: DDSP_HPD4 NF4: DISP_MISC4 NF6: USB_C_GPP_A15] ==> USB_A1_OC_ODL */ PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), /* GPP_A16 : [NF1: USB_OC3# NF4: ISH_GP5 NF6: USB_C_GPP_A16] ==> TABLET_MODE_ODL */ - PAD_CFG_GPI(GPP_A16, NONE, PLTRST), + PAD_NC(GPP_A16, NONE), /* GPP_A17 : [NF4: DISP_MISCC NF6: USB_C_GPP_A17] ==> SOC_GPP_A17 */ PAD_NC(GPP_A17, NONE), /* GPP_A18 : [NF1: DDSP_HPDB NF4: DISP_MISCB NF6: USB_C_GPP_A18] ==> HDMI_HPD */ @@ -95,9 +95,9 @@ /* GPP_B4 : PROC_GP3/ISH_GP5B ==> BOARD_ID9 (NC) */ PAD_NC(GPP_B4, NONE), /* GPP_B5 : [NF1: ISH_I2C0_SDA NF2: I2C2_SDA NF6: USB_C_GPP_B5] ==> ISH_I2C_SENSOR_SDA */ - PAD_CFG_NF(GPP_B5, NONE, PLTRST, NF1), + PAD_NC(GPP_B5, NONE), /* GPP_B6 : [NF1: ISH_I2C0_SCL NF2: I2C2_SCL NF6: USB_C_GPP_B6] ==> ISH_I2C_SENSOR_SCL */ - PAD_CFG_NF(GPP_B6, NONE, PLTRST, NF1), + PAD_NC(GPP_B6, NONE), /* GPP_B7 : [NF1: ISH_I2C1_SDA NF2: I2C3_SDA NF6: USB_C_GPP_B7] ==> SOC_I2C3_SDA (NC) */ PAD_NC(GPP_B7, NONE), /* GPP_B8 : [NF1: ISH_I2C1_SCL NF2: I2C3_SCL NF6: USB_C_GPP_B8] ==> SOC_I2C3_SCL (NC) */ @@ -111,7 +111,7 @@ /* GPP_B14 : [NF1: SPKR NF2: TIME_SYNC1 NF4: SATA_LED# NF5: ISH_GP6 NF6: USB_C_GPP_B14] ==> ACZ_SPKR (NC) */ PAD_NC(GPP_B14, NONE), /* GPP_B15 : [NF2: TIME_SYNC0 NF5: ISH_GP7 NF6: USB_C_GPP_B15] ==> LID_OPEN_Q */ - PAD_CFG_GPI(GPP_B15, NONE, PLTRST), + PAD_NC(GPP_B15, NONE), /* b/316421831: GPP_B16/17 need to be enabled when ISH is enabled later on */ /* GPP_B16 : [NF2: I2C5_SDA NF4: ISH_I2C2_SDA NF6: USB_C_GPP_B16] ==> ISH_I2C_EC_SDA (NC) */ PAD_NC(GPP_B16, NONE), @@ -166,9 +166,9 @@ /* GPP_D12 : [NF1: ISH_SPI_MOSI NF2: DDP4_CTRLDATA NF4: TBT_LSX3_RXD NF5: BSSB_LS3_TX NF6: USB_C_GPP_D12 NF7: GSPI2_MOSI] ==> SOC_GPP_D12 (NC) */ PAD_NC(GPP_D12, NONE), /* GPP_D13 : [NF1: ISH_UART0_RXD NF3: I2C6_SDA NF6: USB_C_GPP_D13] ==> UART0_ISH_RX_DBG_TX */ - PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1), + PAD_NC(GPP_D13, NONE), /* GPP_D14 : [NF1: ISH_UART0_TXD NF3: I2C6_SCL NF6: USB_C_GPP_D14] ==> UART0_ISH_TX_DBG_RX */ - PAD_CFG_NF(GPP_D14, NONE, PLTRST, NF1), + PAD_NC(GPP_D14, NONE), /* GPP_D15 : ISH_UART0_RTS_L/I2C7B_SDA ==> SOC_ISH_UART0_RTS_L (NC) */ PAD_NC(GPP_D15, NONE), /* GPP_D16 : ISH_UART0_CTS_L/I2C7B_SCL ==> SOC_GPP_D16 (NC) */ diff --git a/src/mainboard/google/brox/variants/brox/fw_config.c b/src/mainboard/google/brox/variants/brox/fw_config.c index d1bdc80..1e9409d 100644 --- a/src/mainboard/google/brox/variants/brox/fw_config.c +++ b/src/mainboard/google/brox/variants/brox/fw_config.c @@ -1,6 +1,38 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <bootstate.h> +#include <baseboard/variants.h> +#include <fw_config.h> +#include <gpio.h> + +#define GPIO_PADBASED_OVERRIDE(b, a) gpio_padbased_override(b, a, ARRAY_SIZE(a)) + +static const struct pad_config ish_enable_pads[] = { + /* GPP_B5 : ISH I2C0_SDA */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B5, NONE, DEEP, NF1), + /* GPP_B6 : ISH_I2C0_SCL */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B6, NONE, DEEP, NF1), + /* GPP_D13 : [NF1: ISH_UART0_RXD ==> UART0_ISH_RX_DBG_TX */ + PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1), + /* GPP_D14 : [NF1: ISH_UART0_TXD ==> UART0_ISH_TX_DBG_RX */ + PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1), + /* GPP_D2 : ISH_GP2, SOC_ISH_ACCEL_INT_L */ + PAD_CFG_NF(GPP_D2, NONE, DEEP, NF1), + /* GPP_D3 : ISH_GP3, SOC_ISH_IMU_INT_L */ + PAD_CFG_NF(GPP_D3, NONE, DEEP, NF1), + /* GPP_B15 : ISH_GP7, LID_OPEN_1V8 */ + PAD_CFG_NF(GPP_B15, NONE, DEEP, NF5), + /* GPP_A16 : ISH_GP5, TABLET_MODE_ODL */ + PAD_CFG_NF(GPP_A16, NONE, DEEP, NF4), +}; + +void fw_config_gpio_padbased_override(struct pad_config *padbased_table) +{ + if (fw_config_probe(FW_CONFIG(ISH, ISH_ENABLE))) { + printk(BIOS_INFO, "Configure GPIOs for ISH.\n"); + GPIO_PADBASED_OVERRIDE(padbased_table, ish_enable_pads); + } +} static void fw_config_handle(void *unused) { diff --git a/src/mainboard/google/brox/variants/brox/overridetree.cb b/src/mainboard/google/brox/variants/brox/overridetree.cb index c41be4b..a0fae4a 100644 --- a/src/mainboard/google/brox/variants/brox/overridetree.cb +++ b/src/mainboard/google/brox/variants/brox/overridetree.cb @@ -21,6 +21,10 @@ option UFC_NONE 0 option UFC_OV2740 1 end + field ISH 21 + option ISH_DISABLE 0 + option ISH_ENABLE 1 + end end chip soc/intel/alderlake @@ -288,11 +292,20 @@ probe WIFI_BT WIFI_BT_CNVI end device ref ish on + probe ISH ISH_ENABLE + probe STORAGE STORAGE_UFS + chip drivers/intel/ish + register "firmware_name" = ""brox_ish.bin"" + device generic 0 on + probe ISH ISH_ENABLE + end + end chip drivers/intel/ish register "add_acpi_dma_property" = "true" - device generic 0 on end + device generic 0 on + probe STORAGE STORAGE_UFS + end end - probe STORAGE STORAGE_UFS end device ref ufs on probe STORAGE STORAGE_UFS -- To view, visit https://review.coreboot.org/c/coreboot/+/80773?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iadc5108c62737d27642a6948c00b5c122541aaba Gerrit-Change-Number: 80773 Gerrit-PatchSet: 1 Gerrit-Owner: Li1 Feng <li1.feng(a)intel.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[main]: soc/intel/common/block/cse: Use IFWI build version for update check
by Wonkyu Kim (Code Review) 27 Feb '24

27 Feb '24

Attention is currently required from: Anil Kumar K, Jamie Ryu, Paul Menzel, Pratikkumar V Prajapati, Subrata Banik. Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79413?usp=email ) Change subject: soc/intel/common/block/cse: Use IFWI build version for update check ...................................................................... Patch Set 18: Code-Review+1 (1 comment) File src/soc/intel/common/block/cse/cse_lite.c: https://review.coreboot.org/c/coreboot/+/79413/comment/8ba22e9a_3f0881ee : PS15, Line 912: CONFIG_SOC_INTEL_CSE_RW_VERSION_CBFS_NAME > Do we still want to call this CSE RW version. […] This is used for previous platform for saving CSE version, we're trying to reuse the file and makefile for less change and avoid previous platform impact. -- To view, visit https://review.coreboot.org/c/coreboot/+/79413?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib95ffeabda01c66fcce35ca3065c06362c75d848 Gerrit-Change-Number: 79413 Gerrit-PatchSet: 18 Gerrit-Owner: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Comment-Date: Wed, 28 Feb 2024 05:38:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: soc/intel/common/block/cse: Use IFWI build version for update check
by Wonkyu Kim (Code Review) 27 Feb '24

27 Feb '24

Attention is currently required from: Anil Kumar K, Jamie Ryu, Paul Menzel, Pratikkumar V Prajapati, Subrata Banik. Hello Anil Kumar K, Jamie Ryu, Pratikkumar V Prajapati, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/79413?usp=email to look at the new patch set (#18). Change subject: soc/intel/common/block/cse: Use IFWI build version for update check ...................................................................... soc/intel/common/block/cse: Use IFWI build version for update check Use IFWI build version(32bits) in existing CSE BPDT header instead of CSE FW version to check CSE FW update. New build config(SOC_INTEL_CSE_USE_IFWI_BUILD_VERSION) is added not to affect existing platforms which use cse_lite common code and CSE FW version for update check. With this change, we can do 1. can create CSE FW update image when other IFWI FWs(ex. PMC) is changed while CSE FW version is same 2. can create dummy upgrade/downgrade test image by just changing coreboot configuration For enabling this, we need to update below 1. Update build config CONFIG_SOC_INTEL_CSE_USE_IFWI_BUILD_VERSION=y CONFIG_SOC_INTEL_CSE_RW_VERSION="2347" #2023WW47 2. Update blobs with IFWI version in fit config IfwiBuildVersion value="2347" TEST= build coreboot image with specific IFWI build version (ex. 2347: 2023WW47) Upgrade test 1. Open coreboot image with FIT 2. Update IFWI build version to 2346. 3. Flash and boot to OS and check coreboot log Downgrade test 1. Open coreboot image with FIT 2. Update IFWI build version to 2348. 3. Flash and boot to OS and check coreboot log Restore test 1. Open coreboot image with FIT 2. Update IFWI build version to 0. 3. Flash and boot to OS and check coreboot log Check CSE FW upgrade/downgrade happen from the log Change-Id: Ib95ffeabda01c66fcce35ca3065c06362c75d848 Signed-off-by: Wonkyu Kim <wonkyu.kim(a)intel.com> --- M src/soc/intel/common/block/cse/Kconfig M src/soc/intel/common/block/cse/cse_lite.c 2 files changed, 108 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/79413/18 -- To view, visit https://review.coreboot.org/c/coreboot/+/79413?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib95ffeabda01c66fcce35ca3065c06362c75d848 Gerrit-Change-Number: 79413 Gerrit-PatchSet: 18 Gerrit-Owner: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-MessageType: newpatchset

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[M] Change in libgfxinit[main]: gma: Update DP training with new fields
by Kapil Porwal (Code Review) 27 Feb '24

27 Feb '24

Attention is currently required from: Angel Pons, Jérémy Compostella, Nick Vaccaro, Nico Huber, Shelley Chen, Tarun Tuli, Tim Wawrzynczak. Kapil Porwal has posted comments on this change. ( https://review.coreboot.org/c/libgfxinit/+/67490?usp=email ) Change subject: gma: Update DP training with new fields ...................................................................... Patch Set 23: Code-Review+2 -- To view, visit https://review.coreboot.org/c/libgfxinit/+/67490?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: main Gerrit-Change-Id: I3f7f8a93408a74cfa29d1493a48c88ce73dc690c Gerrit-Change-Number: 67490 Gerrit-PatchSet: 23 Gerrit-Owner: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: Shelley Chen <shchen(a)google.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Wed, 28 Feb 2024 05:32:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[main]: soc/intel/common/block/cse: Use IFWI build version for update check
by Wonkyu Kim (Code Review) 27 Feb '24

27 Feb '24

Attention is currently required from: Anil Kumar K, Jamie Ryu, Paul Menzel, Pratikkumar V Prajapati, Subrata Banik. Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79413?usp=email ) Change subject: soc/intel/common/block/cse: Use IFWI build version for update check ...................................................................... Patch Set 16: Code-Review+1 (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/79413/comment/1138a00c_2e11cfab : PS15, Line 7: verion > typo Done https://review.coreboot.org/c/coreboot/+/79413/comment/5c546a91_8d30a6ea : PS15, Line 9: > space not required Done https://review.coreboot.org/c/coreboot/+/79413/comment/bf4a737b_6d78c874 : PS15, Line 9: cse bpdt > use CAPS Done https://review.coreboot.org/c/coreboot/+/79413/comment/e32ed779_c5ad8d1e : PS15, Line 17: FWs > pls provide ex: on which other FW is being referred to here Done -- To view, visit https://review.coreboot.org/c/coreboot/+/79413?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib95ffeabda01c66fcce35ca3065c06362c75d848 Gerrit-Change-Number: 79413 Gerrit-PatchSet: 16 Gerrit-Owner: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Comment-Date: Wed, 28 Feb 2024 04:32:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: soc/intel/common/block/cse: Use IFWI build version for update check
by Wonkyu Kim (Code Review) 27 Feb '24

27 Feb '24

Attention is currently required from: Jamie Ryu, Paul Menzel, Pratikkumar V Prajapati, Subrata Banik, Wonkyu Kim. Hello Anil Kumar K, Jamie Ryu, Pratikkumar V Prajapati, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/79413?usp=email to look at the new patch set (#16). Change subject: soc/intel/common/block/cse: Use IFWI build version for update check ...................................................................... soc/intel/common/block/cse: Use IFWI build version for update check Use IFWI build version(32bits) in existing CSE BPDT header instead of CSE FW version to check CSE FW update. New build config (SOC_INTEL_CSE_USE_IFWI_BUILD_VERSION) is added not to affect existing platforms which use cse_lite common code and CSE FW version for update check. With this change, we can do 1. can create CSE FW update image when other IFWI FWs(ex. PMC) is changed while CSE FW version is same 2. can create dummy upgrade/downgrade test image by just changing coreboot configuration For enabling this, we need to update below 1. Update build config CONFIG_SOC_INTEL_CSE_USE_IFWI_BUILD_VERSION=y CONFIG_SOC_INTEL_CSE_RW_VERSION="2347" #2023WW47 2. Update blobs with IFWI version in fit config IfwiBuildVersion value="2347" TEST= build coreboot image with specific IFWI build version (ex. 2347: 2023WW47) Upgrade test 1. Open coreboot image with FIT 2. Update IFWI build version to 2346. 3. Flash and boot to OS and check coreboot log Downgrade test 1. Open coreboot image with FIT 2. Update IFWI build version to 2348. 3. Flash and boot to OS and check coreboot log Restore test 1. Open coreboot image with FIT 2. Update IFWI build version to 0. 3. Flash and boot to OS and check coreboot log Check CSE FW upgrade/downgrade happen from the log Change-Id: Ib95ffeabda01c66fcce35ca3065c06362c75d848 Signed-off-by: Wonkyu Kim <wonkyu.kim(a)intel.com> --- M src/soc/intel/common/block/cse/Kconfig M src/soc/intel/common/block/cse/cse_lite.c 2 files changed, 108 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/79413/16 -- To view, visit https://review.coreboot.org/c/coreboot/+/79413?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib95ffeabda01c66fcce35ca3065c06362c75d848 Gerrit-Change-Number: 79413 Gerrit-PatchSet: 16 Gerrit-Owner: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[main]: include/device/azalia_device.h: Merge location1 and location2
by Nicholas Sudsgaard (Code Review) 27 Feb '24

27 Feb '24

Attention is currently required from: Michael Niewöhner, Nico Huber. Nicholas Sudsgaard has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80740?usp=email ) Change subject: include/device/azalia_device.h: Merge location1 and location2 ...................................................................... Patch Set 13: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/80740?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5a61a37ed70027700f07f1532c500f04d7a16ce1 Gerrit-Change-Number: 80740 Gerrit-PatchSet: 13 Gerrit-Owner: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Comment-Date: Wed, 28 Feb 2024 03:40:38 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[L] Change in coreboot[main]: include/device: Merge enums from azalia_device.h and azalia.h
by Nicholas Sudsgaard (Code Review) 27 Feb '24

27 Feb '24

Attention is currently required from: Michael Niewöhner, Nicholas Chin, Nico Huber. Nicholas Sudsgaard has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80695?usp=email ) Change subject: include/device: Merge enums from azalia_device.h and azalia.h ...................................................................... Patch Set 9: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/80695?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie874b083a18963679981a9cd2b25d123890d628e Gerrit-Change-Number: 80695 Gerrit-PatchSet: 9 Gerrit-Owner: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Wed, 28 Feb 2024 03:40:32 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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