coreboot-gerrit February 2024

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[S] Change in coreboot[main]: soc/intel/xeon_sp/spr: Enable FSP_DOES_NOT_NEED_TEMP_RAM
by Shuo Liu (Code Review) 02 Feb '24

02 Feb '24

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Lean Sheng Tan, Patrick Rudolph, Tim Chu. Shuo Liu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80329?usp=email ) Change subject: soc/intel/xeon_sp/spr: Enable FSP_DOES_NOT_NEED_TEMP_RAM ...................................................................... soc/intel/xeon_sp/spr: Enable FSP_DOES_NOT_NEED_TEMP_RAM Change-Id: Ic84c4332dd5b6980ca03f6ab601b7464e0b18001 Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> --- M src/soc/intel/xeon_sp/spr/Kconfig 1 file changed, 2 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/80329/1 diff --git a/src/soc/intel/xeon_sp/spr/Kconfig b/src/soc/intel/xeon_sp/spr/Kconfig index bb88bec..fd19cff 100644 --- a/src/soc/intel/xeon_sp/spr/Kconfig +++ b/src/soc/intel/xeon_sp/spr/Kconfig @@ -13,6 +13,7 @@ select SOC_INTEL_CSE_SERVER_SKU select XEON_SP_COMMON_BASE select HAVE_IOAT_DOMAINS + select FSP_DOES_NOT_NEED_TEMP_RAM help Intel Sapphire Rapids-SP support @@ -64,7 +65,7 @@ config FSP_M_RC_HEAP_SIZE hex - default 0x150000 + default 0x1B0000 help On xeon_sp/spr FSP-M has two separate heap managers, one regular whose size and base are controllable via the StackBase and @@ -84,17 +85,6 @@ hex default 0x4000 -config FSP_TEMP_RAM_SIZE - hex - depends on FSP_USES_CB_STACK - default 0x60000 - help - The amount of anticipated heap usage in CAR by FSP. - Refer to Platform FSP integration guide document to know - the exact FSP requirement for Heap setup. The FSP integration - documentation says this needs to be at least 128KiB, but practice - show this needs to be 256KiB or more. - config IED_REGION_SIZE hex default 0x400000 -- To view, visit https://review.coreboot.org/c/coreboot/+/80329?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic84c4332dd5b6980ca03f6ab601b7464e0b18001 Gerrit-Change-Number: 80329 Gerrit-PatchSet: 1 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[main]: drivers/intel/fsp2_0: Add FSP_DOES_NOT_NEED_TEMP_RAM
by Shuo Liu (Code Review) 02 Feb '24

02 Feb '24

Shuo Liu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80328?usp=email ) Change subject: drivers/intel/fsp2_0: Add FSP_DOES_NOT_NEED_TEMP_RAM ...................................................................... drivers/intel/fsp2_0: Add FSP_DOES_NOT_NEED_TEMP_RAM FSP allocates temporary ram in its reserved memory ranges instead of requesting coreboot to do the allocation. This is supported by some FSP implementations for Xeon SP. Change-Id: I17a73e4f627c91808ed17c712b72937662ae9293 Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> --- M src/drivers/intel/fsp2_0/Kconfig M src/drivers/intel/fsp2_0/memory_init.c 2 files changed, 24 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/80328/1 diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index e27249f..33390e6 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -39,6 +39,26 @@ 1. Added ExtendedImageRevision field in FSP_INFO_HEADER 2. Added FSP_NON_VOLATILE_STORAGE_HOB2 +config FSP_DOES_NOT_NEED_TEMP_RAM + bool + default n + help + FSP allocates temporary ram in its reserved memory ranges + instead of requesting coreboot to do the allocation. This + is supported by some FSP implementations for Xeon SP. + +config FSP_TEMP_RAM_SIZE + hex + default 0x0 if FSP_DOES_NOT_NEED_TEMP_RAM + help + The amount of memory coreboot reserves for the FSP to use. In the + case of FSP 2.1 and newer that share the stack with coreboot instead + of having its own stack, this is the amount of anticipated heap usage + in CAR by FSP to setup HOB and needs to be the recommended value from + the Platform FSP integration guide. In the case of the FSP having its + own stack that will be placed in DRAM and not in CAR, this is the + amount of memory the FSP needs for its stack and heap. + if PLATFORM_USES_FSP2_0 config PLATFORM_USES_FSP2_X86_32 @@ -221,17 +241,6 @@ without reinitializing stack pointer. This feature is supported Icelake onwards. -config FSP_TEMP_RAM_SIZE - hex - help - The amount of memory coreboot reserves for the FSP to use. In the - case of FSP 2.1 and newer that share the stack with coreboot instead - of having its own stack, this is the amount of anticipated heap usage - in CAR by FSP to setup HOB and needs to be the recommended value from - the Platform FSP integration guide. In the case of the FSP having its - own stack that will be placed in DRAM and not in CAR, this is the - amount of memory the FSP needs for its stack and heap. - config FSP_PLATFORM_MEMORY_SETTINGS_VERSIONS bool help diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index f5de5c3..d2e86c8 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -152,6 +152,9 @@ bool s3wake, uint32_t version, const struct memranges *memmap) { + if (CONFIG(FSP_DOES_NOT_NEED_TEMP_RAM)) + goto temp_ram_assigned; + /* * FSP 2.1 version would use same stack as coreboot instead of * setting up separate stack frame. FSP 2.1 would not relocate stack @@ -177,6 +180,7 @@ return CB_ERR; } +temp_ram_assigned: fsp_fill_mrc_cache(arch_upd, version); /* Configure bootmode */ -- To view, visit https://review.coreboot.org/c/coreboot/+/80328?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I17a73e4f627c91808ed17c712b72937662ae9293 Gerrit-Change-Number: 80328 Gerrit-PatchSet: 1 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[main]: soc/amd: commonize PCI root IOAPIC initialization
by Felix Held (Code Review) 02 Feb '24

02 Feb '24

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk. Hello Fred Reitberger, Jason Glenesk, Matt DeVillier, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/80286?usp=email to look at the new patch set (#2). Change subject: soc/amd: commonize PCI root IOAPIC initialization ...................................................................... soc/amd: commonize PCI root IOAPIC initialization Make the initialization of the IOAPIC(s) in the PCI root(s) common across all AMD family 17h+ SoCs. For this the more general implementation from the Genoa code that supports multiple PC roots is moved to the common AMD code. All other family 17h+ SoCs are then adapted to use the common code. For those non-Genoa SoCs, the initialization of this second IOAPIC is moved from the northbridge device to the domain device above to match Genoa. Test=Both the FCH IOAPIC and the PCIe root IOAPIC are still initialized on Mandolin Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I7c0ec6ac2f11cb11e46248cceec96c1fd2a49c16 --- M src/soc/amd/cezanne/chip.c M src/soc/amd/cezanne/root_complex.c M src/soc/amd/common/block/include/amdblocks/root_complex.h M src/soc/amd/common/block/root_complex/Makefile.mk A src/soc/amd/common/block/root_complex/ioapic.c M src/soc/amd/genoa_poc/domain.c M src/soc/amd/glinda/chip.c M src/soc/amd/glinda/root_complex.c M src/soc/amd/mendocino/chip.c M src/soc/amd/mendocino/root_complex.c M src/soc/amd/phoenix/chip.c M src/soc/amd/phoenix/root_complex.c M src/soc/amd/picasso/chip.c M src/soc/amd/picasso/root_complex.c 14 files changed, 36 insertions(+), 41 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/80286/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/80286?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7c0ec6ac2f11cb11e46248cceec96c1fd2a49c16 Gerrit-Change-Number: 80286 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: soc/amd/phoenix/fch: only init ACPI IO ports in FSP case
by Felix Held (Code Review) 02 Feb '24

02 Feb '24

Attention is currently required from: Fred Reitberger, Jason Glenesk. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80297?usp=email ) Change subject: soc/amd/phoenix/fch: only init ACPI IO ports in FSP case ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/80297/comment/2cb246bf_39c46477 : PS1, Line 9: don't overwrite : those by the coreboot code. > phrasing is slightly awkward, maybe "coreboot should not overwrite them" Done -- To view, visit https://review.coreboot.org/c/coreboot/+/80297?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If10e5a9f52ab313ad1afebd7f9e722994d48b0a7 Gerrit-Change-Number: 80297 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Fri, 02 Feb 2024 09:40:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: soc/amd/phoenix/fch: only init ACPI IO ports in FSP case
by Felix Held (Code Review) 02 Feb '24

02 Feb '24

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[XL] Change in coreboot[main]: mb/emulation: Add SIMICS QSP support
by Leon Groß (Code Review) 02 Feb '24

02 Feb '24

Attention is currently required from: Arthur Heymans, Benjamin Doron, Lean Sheng Tan, Leon Groß, Nico Huber, Paul Menzel. Hello Angel Pons, Arthur Heymans, Benjamin Doron, Christian Walter, Lean Sheng Tan, Patrick Rudolph, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/77905?usp=email to look at the new patch set (#17). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: mb/emulation: Add SIMICS QSP support ...................................................................... mb/emulation: Add SIMICS QSP support SIMICS Quick Start Platform (QSP) is weird. It doesn't implement a single X58 register besides DEVID/VENID. Likely because those are never used by an OS. Not so good for firmware development. ICH10 seems to be more properly implemented. Working: - Boots to EDK2 payload (payloads/external/edk2) - TSEG works, ASEG is broken - Graphics init works Signed-off-by: Leon Gross <leon.gross(a)9elements.com> Change-Id: I175b20bb4746608e4d868aa96492fc06c149bd36 --- A Documentation/mainboard/emulation/simics-qsp.md M src/cpu/qemu-x86/Kconfig A src/mainboard/emulation/simics-qsp/Kconfig A src/mainboard/emulation/simics-qsp/Kconfig.name A src/mainboard/emulation/simics-qsp/Makefile.inc A src/mainboard/emulation/simics-qsp/acpi.h A src/mainboard/emulation/simics-qsp/acpi_tables.c A src/mainboard/emulation/simics-qsp/board_info.txt A src/mainboard/emulation/simics-qsp/bootblock.c A src/mainboard/emulation/simics-qsp/cmos.default A src/mainboard/emulation/simics-qsp/cmos.layout A src/mainboard/emulation/simics-qsp/cpu.c A src/mainboard/emulation/simics-qsp/devicetree.cb A src/mainboard/emulation/simics-qsp/dsdt.asl A src/mainboard/emulation/simics-qsp/exit_car.S A src/mainboard/emulation/simics-qsp/hda_verb.c A src/mainboard/emulation/simics-qsp/mainboard.c A src/mainboard/emulation/simics-qsp/memmap.c A src/mainboard/emulation/simics-qsp/memory.h A src/mainboard/emulation/simics-qsp/northbridge.c A src/mainboard/emulation/simics-qsp/romstage.c A src/mainboard/emulation/simics-qsp/vboot-rwa-16M.fmd A src/mainboard/emulation/simics-qsp/vboot-rwab-16M.fmd M src/southbridge/intel/i82801jx/Kconfig 24 files changed, 1,230 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/77905/17 -- To view, visit https://review.coreboot.org/c/coreboot/+/77905?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I175b20bb4746608e4d868aa96492fc06c149bd36 Gerrit-Change-Number: 77905 Gerrit-PatchSet: 17 Gerrit-Owner: Leon Groß <leon.gross(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Leon Groß <leon.gross(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-MessageType: newpatchset

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[L] Change in coreboot[main]: lib: Move IP checksum to commonlib
by Jakub Czapiga (Code Review) 02 Feb '24

02 Feb '24

Attention is currently required from: Angel Pons, Arthur Heymans, Hung-Te Lin, Julius Werner, Jérémy Compostella, Paul Menzel, Yu-Ping Wu. Jakub Czapiga has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80251?usp=email ) Change subject: lib: Move IP checksum to commonlib ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/80251?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic04c714c00439a17fc04a8a6e730cc2aa19b8e68 Gerrit-Change-Number: 80251 Gerrit-PatchSet: 3 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Fri, 02 Feb 2024 09:01:35 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in em100[main]: em100: return an error if a command fails
by Jakub Czapiga (Code Review) 02 Feb '24

02 Feb '24

Attention is currently required from: c.koehne(a)beckhoff.com. Jakub Czapiga has posted comments on this change. ( https://review.coreboot.org/c/em100/+/80250?usp=email ) Change subject: em100: return an error if a command fails ...................................................................... Patch Set 1: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/em100/+/80250/comment/bd43d5ea_382cc012 : PS1, Line 9: We don't properly return an error in every code path when a command fails. This : makes it hard to use this tool in a shell script because you can't be sure that : your command was successful. : Please match 72 characters line limit -- To view, visit https://review.coreboot.org/c/em100/+/80250?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: em100 Gerrit-Branch: main Gerrit-Change-Id: I2554252d007a92e939088389d67f9d4cede837ee Gerrit-Change-Number: 80250 Gerrit-PatchSet: 1 Gerrit-Owner: c.koehne(a)beckhoff.com Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: c.koehne(a)beckhoff.com Gerrit-Comment-Date: Fri, 02 Feb 2024 08:59:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in em100[main]: em100: exit when using an invalid device name
by Jakub Czapiga (Code Review) 02 Feb '24

02 Feb '24

Attention is currently required from: c.koehne(a)beckhoff.com. Jakub Czapiga has posted comments on this change. ( https://review.coreboot.org/c/em100/+/80249?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: em100: exit when using an invalid device name ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/em100/+/80249/comment/c11325be_1918a98c : PS1, Line 9: If you use a stupid device name like `em100 --device bla`, we won't exit with : an error right now. It just ignores the devices and uses the first device it : can find. This could lead to unexpected issues when connecting more than one : EM100 device to your machine. It's much better to exit if we're unable to parse : the device name. Please match 72 characters line limit -- To view, visit https://review.coreboot.org/c/em100/+/80249?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: em100 Gerrit-Branch: main Gerrit-Change-Id: If0f7b8b576224a9db6ab319c2212bc245110c5c1 Gerrit-Change-Number: 80249 Gerrit-PatchSet: 1 Gerrit-Owner: c.koehne(a)beckhoff.com Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: c.koehne(a)beckhoff.com Gerrit-Comment-Date: Fri, 02 Feb 2024 08:59:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in em100[main]: em100: exit when using an invalid device name
by Jakub Czapiga (Code Review) 02 Feb '24

02 Feb '24

Attention is currently required from: c.koehne(a)beckhoff.com. Jakub Czapiga has posted comments on this change. ( https://review.coreboot.org/c/em100/+/80249?usp=email ) Change subject: em100: exit when using an invalid device name ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/em100/+/80249?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: em100 Gerrit-Branch: main Gerrit-Change-Id: If0f7b8b576224a9db6ab319c2212bc245110c5c1 Gerrit-Change-Number: 80249 Gerrit-PatchSet: 1 Gerrit-Owner: c.koehne(a)beckhoff.com Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: c.koehne(a)beckhoff.com Gerrit-Comment-Date: Fri, 02 Feb 2024 08:58:41 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit February 2024