coreboot-gerrit February 2024

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[S] Change in coreboot[main]: vc/amd/opensil/genoa_poc: remove xSIM-api dependency from opensil.h
by Felix Held (Code Review) 02 Feb '24

02 Feb '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80287?usp=email ) Change subject: vc/amd/opensil/genoa_poc: remove xSIM-api dependency from opensil.h ...................................................................... vc/amd/opensil/genoa_poc: remove xSIM-api dependency from opensil.h Provide 3 separate functions for each openSIL time point instead of one, so that we don't need the xSIM-api header file to be included in opensil.h to decouple the coreboot code more form the openSIL code. This will allow to create an openSIL stub implementation to already get most of the coreboot-side SoC code in place before the openSIL source code is done and released. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I969bc0862560b7254c48f04e9a03387417f328bc Reviewed-on: https://review.coreboot.org/c/coreboot/+/80287 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-by: Varshit Pandya <pandyavarshit(a)gmail.com> --- M src/soc/amd/genoa_poc/chip.c M src/vendorcode/amd/opensil/genoa_poc/opensil.h M src/vendorcode/amd/opensil/genoa_poc/ramstage.c 3 files changed, 20 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved Varshit Pandya: Looks good to me, approved diff --git a/src/soc/amd/genoa_poc/chip.c b/src/soc/amd/genoa_poc/chip.c index d397800..13ede84 100644 --- a/src/soc/amd/genoa_poc/chip.c +++ b/src/soc/amd/genoa_poc/chip.c @@ -11,7 +11,7 @@ default_dev_ops_root.write_acpi_tables = soc_acpi_write_tables; setup_opensil(); - opensil_entry(SIL_TP1); + opensil_xSIM_timepoint_1(); fch_init(chip_info); } diff --git a/src/vendorcode/amd/opensil/genoa_poc/opensil.h b/src/vendorcode/amd/opensil/genoa_poc/opensil.h index e225522..334903f 100644 --- a/src/vendorcode/amd/opensil/genoa_poc/opensil.h +++ b/src/vendorcode/amd/opensil/genoa_poc/opensil.h @@ -4,7 +4,6 @@ #define _OPENSIL_H_ #include <acpi/acpi.h> -#include <xSIM-api.h> void SIL_STATUS_report(const char *function, const int status); // Add the memory map to dev, starting at index idx, returns last use idx @@ -15,6 +14,8 @@ void configure_mpio(void); void setup_opensil(void); -void opensil_entry(SIL_TIMEPOINT timepoint); +void opensil_xSIM_timepoint_1(void); +void opensil_xSIM_timepoint_2(void); +void opensil_xSIM_timepoint_3(void); #endif diff --git a/src/vendorcode/amd/opensil/genoa_poc/ramstage.c b/src/vendorcode/amd/opensil/genoa_poc/ramstage.c index 11289bb..758b284 100644 --- a/src/vendorcode/amd/opensil/genoa_poc/ramstage.c +++ b/src/vendorcode/amd/opensil/genoa_poc/ramstage.c @@ -129,7 +129,7 @@ configure_mpio(); } -void opensil_entry(SIL_TIMEPOINT timepoint) +static void opensil_entry(SIL_TIMEPOINT timepoint) { SIL_STATUS ret; SIL_TIMEPOINT tp = (uintptr_t)timepoint; @@ -160,4 +160,19 @@ } } +void opensil_xSIM_timepoint_1(void) +{ + opensil_entry(SIL_TP1); +} + +void opensil_xSIM_timepoint_2(void) +{ + opensil_entry(SIL_TP2); +} + +void opensil_xSIM_timepoint_3(void) +{ + opensil_entry(SIL_TP3); +} + /* TODO: also call timepoints 2 and 3 from coreboot. Are they NOOP? */ -- To view, visit https://review.coreboot.org/c/coreboot/+/80287?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I969bc0862560b7254c48f04e9a03387417f328bc Gerrit-Change-Number: 80287 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[main]: vc/amd/opensil: add openSIL stub implementation
by Martin L Roth (Code Review) 02 Feb '24

02 Feb '24

Attention is currently required from: Felix Held, Varshit Pandya. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80292?usp=email ) Change subject: vc/amd/opensil: add openSIL stub implementation ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/80292?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9284b0cbacba6eae7e2e7e69bc687f015076c2b0 Gerrit-Change-Number: 80292 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 02 Feb 2024 20:31:56 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/google/rex/var/karis: Update fw_config KB_TYPE field
by Eran Mitrani (Code Review) 02 Feb '24

02 Feb '24

Attention is currently required from: David Wu, Dinesh Gehlot, Jakub Czapiga, Kapil Porwal, Tarun, Tyler Wang. Eran Mitrani has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80331?usp=email ) Change subject: mb/google/rex/var/karis: Update fw_config KB_TYPE field ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/80331?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ied54f78dddd9dddca1272fc31c9502fc11c61dde Gerrit-Change-Number: 80331 Gerrit-PatchSet: 1 Gerrit-Owner: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Fri, 02 Feb 2024 19:07:22 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[main]: mb/amd/birman: add Phoenix with openSIL mainboard option
by Matt DeVillier (Code Review) 02 Feb '24

02 Feb '24

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80299?usp=email ) Change subject: mb/amd/birman: add Phoenix with openSIL mainboard option ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/80299?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I248102e92818b2d395d561a4bf2627f80906b2f7 Gerrit-Change-Number: 80299 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 02 Feb 2024 18:41:16 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: cpu/x86/Kconfig: Mark 64bit support as stable
by Arthur Heymans (Code Review) 02 Feb '24

02 Feb '24

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80338?usp=email ) Change subject: cpu/x86/Kconfig: Mark 64bit support as stable ...................................................................... cpu/x86/Kconfig: Mark 64bit support as stable With SMM holding page tables itself, we can consider SMM support stable and safe enough for general use. Also update the respective documentation. Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Change-Id: Ifcf0a1a5097a2d7c064bb709ec0b09ebee13a47d --- M Documentation/arch/x86/index.md M src/arch/x86/Kconfig 2 files changed, 4 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/80338/1 diff --git a/Documentation/arch/x86/index.md b/Documentation/arch/x86/index.md index c7115b4..ea0ec61 100644 --- a/Documentation/arch/x86/index.md +++ b/Documentation/arch/x86/index.md @@ -5,9 +5,7 @@ * [x86 PAE support](pae.md) ## State of x86_64 support -At the moment there's only experimental x86_64 support. -The `emulation/qemu-i440fx` and `emulation/qemu-q35` boards do support -*ARCH_RAMSTAGE_X86_64* , *ARCH_POSTCAR_X86_64* and *ARCH_ROMSTAGE_X86_64*. +A few SOCs now support 64bit mode. Search for HAVE_EXP_X86_64_SUPPORT in Kconfig. In order to add support for x86_64 the following assumptions were made: * The CPU supports long mode @@ -15,7 +13,6 @@ * All code that is to be run must be below 4GiB in physical memory * The high dword of pointers is always zero * The reference implementation is qemu -* The CPU supports 1GiB hugepages * x86 payloads are loaded below 4GiB in physical memory and are jumped to in *protected mode* @@ -54,7 +51,6 @@ 1. Fine grained page tables for SMM: * Must not have execute and write permissions for the same page. * Must allow only that TSEG pages can be marked executable - * Must reside in SMRAM 2. Support 64bit PCI BARs above 4GiB 3. Place and run code above 4GiB @@ -62,13 +58,10 @@ * Fix compilation errors * Test how well CAR works with x86_64 and paging * Improve mode switches -* Test libgfxinit / VGA Option ROMs / FSP -## Known bugs on real hardware +## Known problems on real hardware -According to Intel x86_64 mode hasn't been validated in CAR environments. -Until now it could be verified on various Intel platforms and no issues have -been found. +Running VGA rom directly fails. Yabel works fine though. ## Known bugs on KVM enabled qemu diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 1697ee7..c264130 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -74,7 +74,7 @@ to provide a config file for Jenkins to build-test the 64-bit option. config USE_EXP_X86_64_SUPPORT - bool "[EXPERIMENTAL] Run coreboot in long (64-bit) mode" + bool "Run coreboot in long (64-bit) mode" depends on HAVE_EXP_X86_64_SUPPORT select ARCH_ALL_STAGES_X86_64 help -- To view, visit https://review.coreboot.org/c/coreboot/+/80338?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifcf0a1a5097a2d7c064bb709ec0b09ebee13a47d Gerrit-Change-Number: 80338 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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[S] Change in coreboot[main]: cpu/x86: Link page tables in stage if possible
by Arthur Heymans (Code Review) 02 Feb '24

02 Feb '24

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Jérémy Compostella, Matt DeVillier. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80337?usp=email ) Change subject: cpu/x86: Link page tables in stage if possible ...................................................................... Patch Set 1: (1 comment) File src/soc/amd/picasso/Kconfig: https://review.coreboot.org/c/coreboot/+/80337/comment/1ccea960_daf22bec : PS1, Line 166: : default 0x20000 separate commit... But it does work on that platform with this setting. -- To view, visit https://review.coreboot.org/c/coreboot/+/80337?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ied54b66b930187cba5fbc578a81ed5859a616562 Gerrit-Change-Number: 80337 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 02 Feb 2024 18:37:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[main]: cpu/x86: Link page tables in stage if possible
by Arthur Heymans (Code Review) 02 Feb '24

02 Feb '24

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Jérémy Compostella, Matt DeVillier. Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80337?usp=email ) Change subject: cpu/x86: Link page tables in stage if possible ...................................................................... cpu/x86: Link page tables in stage if possible When switching back and forward from 32 to 64, for example to call a 32bit FSP or toe call the payload, a new page tables in the respective stage will be linked. TESTED on google/vilbox and qemu/q35: boots to payload Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Change-Id: Ied54b66b930187cba5fbc578a81ed5859a616562 --- M src/arch/x86/Kconfig M src/cpu/intel/car/non-evict/cache_as_ram.S M src/cpu/intel/car/p4-netburst/cache_as_ram.S M src/cpu/x86/64bit/Makefile.mk M src/cpu/x86/64bit/entry64.inc M src/cpu/x86/64bit/mode_switch.S M src/cpu/x86/64bit/mode_switch2.S M src/cpu/x86/64bit/pt.S M src/mainboard/emulation/qemu-i440fx/Kconfig M src/mainboard/emulation/qemu-q35/Kconfig M src/soc/amd/common/block/cpu/noncar/pre_c.S M src/soc/amd/picasso/Kconfig M src/soc/intel/common/block/cpu/car/cache_as_ram.S 13 files changed, 25 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/80337/1 diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 0c11653..1697ee7 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -84,9 +84,13 @@ is an experimental option: do not enable unless one wants to test it and has the means to recover a system when coreboot fails to boot. +config PAGE_TABLES_IN_CBFS + bool + default n + config ARCH_X86_64_PGTBL_LOC hex "x86_64 page table location in CBFS" - depends on ARCH_BOOTBLOCK_X86_64 + depends on ARCH_BOOTBLOCK_X86_64 && PAGE_TABLES_IN_CBFS default 0xfffe9000 help The position where to place pagetables. Needs to be known at diff --git a/src/cpu/intel/car/non-evict/cache_as_ram.S b/src/cpu/intel/car/non-evict/cache_as_ram.S index 578bf03..9485cd4 100644 --- a/src/cpu/intel/car/non-evict/cache_as_ram.S +++ b/src/cpu/intel/car/non-evict/cache_as_ram.S @@ -214,7 +214,7 @@ andl $0xfffffff0, %esp #if ENV_X86_64 - setup_longmode $(CONFIG_ARCH_X86_64_PGTBL_LOC) + setup_longmode $PM4LE movd %mm2, %rdi shlq $32, %rdi diff --git a/src/cpu/intel/car/p4-netburst/cache_as_ram.S b/src/cpu/intel/car/p4-netburst/cache_as_ram.S index 32fddd6..1cb422d 100644 --- a/src/cpu/intel/car/p4-netburst/cache_as_ram.S +++ b/src/cpu/intel/car/p4-netburst/cache_as_ram.S @@ -363,7 +363,7 @@ subl $4, %esp #if ENV_X86_64 - setup_longmode $(CONFIG_ARCH_X86_64_PGTBL_LOC) + setup_longmode $PM4LE movd %mm2, %rdi shlq $32, %rdi /* BIST */ diff --git a/src/cpu/x86/64bit/Makefile.mk b/src/cpu/x86/64bit/Makefile.mk index 24a5a96..7604164 100644 --- a/src/cpu/x86/64bit/Makefile.mk +++ b/src/cpu/x86/64bit/Makefile.mk @@ -2,6 +2,7 @@ all_x86-y += mode_switch.S all_x86-y += mode_switch2.S +all_x86-y += pt.S # Add --defsym=_start=0 to suppress a linker warning. $(objcbfs)/pt: $(dir)/pt.S $(obj)/config.h @@ -9,7 +10,7 @@ $(OBJCOPY_ramstage) -Obinary -j .rodata $@.tmp $@ rm $@.tmp -cbfs-files-y += pagetables +cbfs-files-$(CONFIG_PAGE_TABLES_IN_CBFS) += pagetables pagetables-file := $(objcbfs)/pt pagetables-type := raw pagetables-compression := none diff --git a/src/cpu/x86/64bit/entry64.inc b/src/cpu/x86/64bit/entry64.inc index 878f310..52da603 100644 --- a/src/cpu/x86/64bit/entry64.inc +++ b/src/cpu/x86/64bit/entry64.inc @@ -11,9 +11,11 @@ #if ENV_X86_64 .code32 +#if CONFIG(PAGE_TABLES_IN_CBFS) #if (CONFIG_ARCH_X86_64_PGTBL_LOC & 0xfff) > 0 #error pagetables must be 4KiB aligned! #endif +#endif #include <cpu/x86/msr.h> #if defined(__RAMSTAGE__) diff --git a/src/cpu/x86/64bit/mode_switch.S b/src/cpu/x86/64bit/mode_switch.S index 01fe003..9555cef 100644 --- a/src/cpu/x86/64bit/mode_switch.S +++ b/src/cpu/x86/64bit/mode_switch.S @@ -44,7 +44,7 @@ movl %eax, %ebx /* Preserves ebx */ - setup_longmode $(CONFIG_ARCH_X86_64_PGTBL_LOC) + setup_longmode $PM4LE /* Place return value in rax */ movl %ebx, %eax diff --git a/src/cpu/x86/64bit/mode_switch2.S b/src/cpu/x86/64bit/mode_switch2.S index 1807d2e..18c6425 100644 --- a/src/cpu/x86/64bit/mode_switch2.S +++ b/src/cpu/x86/64bit/mode_switch2.S @@ -21,7 +21,7 @@ mov %esp, %ebp /* Enter long mode, preserves ebx */ - setup_longmode $(CONFIG_ARCH_X86_64_PGTBL_LOC) + setup_longmode $PM4LE /* Align stack */ movabs $0xfffffffffffffff0, %rax diff --git a/src/cpu/x86/64bit/pt.S b/src/cpu/x86/64bit/pt.S index b105528..67e4b1b 100644 --- a/src/cpu/x86/64bit/pt.S +++ b/src/cpu/x86/64bit/pt.S @@ -18,7 +18,7 @@ #define _GEN_PAGE(a) (_PRES + _RW + _US + _PS + _A + _D + (a)) .global PM4LE -.align 32 +.align 4096 PM4LE: .quad _GEN_DIR(PDPE_table) diff --git a/src/mainboard/emulation/qemu-i440fx/Kconfig b/src/mainboard/emulation/qemu-i440fx/Kconfig index f02c92d..a71ead1 100644 --- a/src/mainboard/emulation/qemu-i440fx/Kconfig +++ b/src/mainboard/emulation/qemu-i440fx/Kconfig @@ -28,6 +28,10 @@ select GBB_FLAG_DISABLE_FWMP if ARCH_BOOTBLOCK_X86_64 +config PAGE_TABLES_IN_CBFS + bool + default y + # Need to install page tables in DRAM as the virtual MMU has problems translating paging # request when the page table resides in emulated ROM. This causes undefined behaviour # when handling data requests, as well as fetching and decoding instructions diff --git a/src/mainboard/emulation/qemu-q35/Kconfig b/src/mainboard/emulation/qemu-q35/Kconfig index 489fd07..6337882 100644 --- a/src/mainboard/emulation/qemu-q35/Kconfig +++ b/src/mainboard/emulation/qemu-q35/Kconfig @@ -30,6 +30,10 @@ default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/vboot-rwab-16M.fmd" if VBOOT_SLOTS_RW_AB if ARCH_BOOTBLOCK_X86_64 +config PAGE_TABLES_IN_CBFS + bool + default y + # Need to install page tables in DRAM as the virtual MMU has problems translating paging # request when the page table resides in emulated ROM. This causes undefined behaviour # when handling data requests, as well as fetching and decoding instructions diff --git a/src/soc/amd/common/block/cpu/noncar/pre_c.S b/src/soc/amd/common/block/cpu/noncar/pre_c.S index bb2203b..0e0be52 100644 --- a/src/soc/amd/common/block/cpu/noncar/pre_c.S +++ b/src/soc/amd/common/block/cpu/noncar/pre_c.S @@ -28,7 +28,7 @@ post_code(POSTCODE_BOOTBLOCK_PRE_C_ENTRY) #if ENV_X86_64 - setup_longmode $(CONFIG_ARCH_X86_64_PGTBL_LOC) + setup_longmode $PM4LE #endif /* Clear .bss section */ diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 42fe66f..cc8b689 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -164,7 +164,7 @@ config C_ENV_BOOTBLOCK_SIZE hex - default 0x10000 + default 0x20000 help Sets the size of the bootblock stage that should be loaded in DRAM. This variable controls the DRAM allocation size in linker script diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S index c22e7d9..ba98f1b 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S @@ -280,7 +280,7 @@ andl $0xfffffff0, %esp #if ENV_X86_64 - setup_longmode $(CONFIG_ARCH_X86_64_PGTBL_LOC) + setup_longmode $PM4LE movd %mm2, %rdi shlq $32, %rdi -- To view, visit https://review.coreboot.org/c/coreboot/+/80337?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ied54b66b930187cba5fbc578a81ed5859a616562 Gerrit-Change-Number: 80337 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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[M] Change in coreboot[main]: cpu/x86/smm: Set up page tables in safe SMRAM
by Arthur Heymans (Code Review) 02 Feb '24

02 Feb '24

Attention is currently required from: Jérémy Compostella. Hello Jérémy Compostella, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/80336?usp=email to look at the new patch set (#2). Change subject: cpu/x86/smm: Set up page tables in safe SMRAM ...................................................................... cpu/x86/smm: Set up page tables in safe SMRAM Relying on page tables being in RO flash is not safe in every setup, therefore set up some page tables in SMRAM that the permanent smihandler can use. Tested on QEMU. Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Change-Id: Icb3086abd577b9abb9966dd910a264a873ace4ed --- M src/cpu/x86/mp_init.c M src/cpu/x86/smm/smm_module_loader.c 2 files changed, 54 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/80336/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/80336?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icb3086abd577b9abb9966dd910a264a873ace4ed Gerrit-Change-Number: 80336 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: cpu/x86/(sipi|smm): Pass on CR3 from ramstage
by Arthur Heymans (Code Review) 02 Feb '24

02 Feb '24

Attention is currently required from: Jérémy Compostella. Hello Jérémy Compostella, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/80335?usp=email to look at the new patch set (#2). Change subject: cpu/x86/(sipi|smm): Pass on CR3 from ramstage ...................................................................... cpu/x86/(sipi|smm): Pass on CR3 from ramstage Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Change-Id: I1250ea6f63c65228178ee66e06d988dadfcc2a37 --- M src/cpu/x86/mp_init.c M src/cpu/x86/sipi_vector.S M src/cpu/x86/smm/smm_stub.S M src/include/cpu/x86/smm.h 4 files changed, 13 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/80335/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/80335?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1250ea6f63c65228178ee66e06d988dadfcc2a37 Gerrit-Change-Number: 80335 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: cpu/x86/64bit: Turn jumping to long mode into a macro
by Arthur Heymans (Code Review) 02 Feb '24

02 Feb '24

Attention is currently required from: Jérémy Compostella. Hello Jérémy Compostella, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/79261?usp=email to look at the new patch set (#3). Change subject: cpu/x86/64bit: Turn jumping to long mode into a macro ...................................................................... cpu/x86/64bit: Turn jumping to long mode into a macro This makes it easier to reuse, e.g. if you want to do it twice in one assembly file. Change-Id: Ida861338004187e4e714be41e17c8447fa4cf935 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/car/non-evict/cache_as_ram.S M src/cpu/intel/car/p4-netburst/cache_as_ram.S M src/cpu/qemu-x86/cache_as_ram_bootblock.S M src/cpu/x86/64bit/entry64.inc M src/cpu/x86/64bit/mode_switch.S M src/cpu/x86/64bit/mode_switch2.S M src/cpu/x86/sipi_vector.S M src/cpu/x86/smm/smm_stub.S M src/soc/amd/common/block/cpu/noncar/pre_c.S M src/soc/intel/common/block/cpu/car/cache_as_ram.S 10 files changed, 29 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/79261/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/79261?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ida861338004187e4e714be41e17c8447fa4cf935 Gerrit-Change-Number: 79261 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-MessageType: newpatchset

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