Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80295?usp=email )
Change subject: soc/amd/phoenix/fch: only call gpp_clk_setup in FSP case
......................................................................
soc/amd/phoenix/fch: only call gpp_clk_setup in FSP case
The configuration of the PCIe clock generators in the FCH was moved from
the FSP to coreboot, since all registers are documented. This
initialization is however tightly integrated in the rest of the PCIe
init code inside the reference code. In the FSP case, this code was
manually removed. openSIL will do that part of the initialization so
that there's no coreboot-specific change needed in openSIL. This will
also avoid the problems caused by mismatching configurations done by the
coreboot code and the PCIe init part of the reference code.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: I6d64285a301ade6860c07e62dcb1a718e7a96644
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80295
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com>
---
M src/soc/amd/phoenix/fch.c
1 file changed, 3 insertions(+), 1 deletion(-)
Approvals:
build bot (Jenkins): Verified
Matt DeVillier: Looks good to me, approved
diff --git a/src/soc/amd/phoenix/fch.c b/src/soc/amd/phoenix/fch.c
index c2f0558..e9bc80a 100644
--- a/src/soc/amd/phoenix/fch.c
+++ b/src/soc/amd/phoenix/fch.c
@@ -200,7 +200,9 @@
acpi_pm_gpe_add_events_print_events();
gpio_add_events();
- gpp_clk_setup();
+ if (CONFIG(PLATFORM_USES_FSP2_0))
+ gpp_clk_setup();
+
fch_clk_output_48Mhz();
cgpll_clock_gate_init();
}
--
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Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: I6d64285a301ade6860c07e62dcb1a718e7a96644
Gerrit-Change-Number: 80295
Gerrit-PatchSet: 2
Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com>
Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com>
Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-MessageType: merged
Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80294?usp=email )
Change subject: soc/amd/phoenix: add get_pci_routing_table stub for non-FSP case
......................................................................
soc/amd/phoenix: add get_pci_routing_table stub for non-FSP case
In the FSP case we get this info via a HOB. It's currently unclear if
we'll get a data structure for this from openSIL or if we'll end up
being able to just read the configuration fro the hardware, so add a
get_pci_routing_table stub for now to be able to build.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: I5003e287d6a3a9320922beaffff8a3a846531e14
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80294
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com>
---
M src/soc/amd/phoenix/Makefile.mk
A src/soc/amd/phoenix/pci_irq_routing.c
2 files changed, 15 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Matt DeVillier: Looks good to me, approved
diff --git a/src/soc/amd/phoenix/Makefile.mk b/src/soc/amd/phoenix/Makefile.mk
index 9c775cc..be0a022 100644
--- a/src/soc/amd/phoenix/Makefile.mk
+++ b/src/soc/amd/phoenix/Makefile.mk
@@ -32,6 +32,7 @@
ramstage-y += graphics.c
ramstage-y += mca.c
ramstage-y += memmap.c
+ramstage-$(CONFIG_SOC_AMD_PHOENIX_OPENSIL) += pci_irq_routing.c
ramstage-y += root_complex.c
ramstage-y += soc_util.c
ramstage-y += xhci.c
diff --git a/src/soc/amd/phoenix/pci_irq_routing.c b/src/soc/amd/phoenix/pci_irq_routing.c
new file mode 100644
index 0000000..5c891c2
--- /dev/null
+++ b/src/soc/amd/phoenix/pci_irq_routing.c
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <amdblocks/amd_pci_util.h>
+#include <console/console.h>
+#include <types.h>
+
+const struct pci_routing_info *get_pci_routing_table(size_t *entries)
+{
+ /* TODO: still needs to be implemented for the non-FSP case */
+ printk(BIOS_NOTICE, "%s stub: returning empty IRQ routing table\n", __func__);
+
+ *entries = 0;
+ return NULL;
+}
--
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Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: I5003e287d6a3a9320922beaffff8a3a846531e14
Gerrit-Change-Number: 80294
Gerrit-PatchSet: 2
Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com>
Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com>
Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-MessageType: merged
Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80293?usp=email )
Change subject: soc/amd/phoenix/Kconfig: add SOC_AMD_PHOENIX_OPENSIL option
......................................................................
soc/amd/phoenix/Kconfig: add SOC_AMD_PHOENIX_OPENSIL option
Add the SOC_AMD_PHOENIX_OPENSIL Kconfig option to be able to build the
Phoenix code using openSIL instead of FSP for initializing the hardware.
Since there's currently no publicly available openSIL code for Phoenix,
SOC_AMD_OPENSIL_STUB is selected to have the stubs added to the build
instead of the actual openSIL code. The code added by selecting
SOC_AMD_COMMON_BLOCK_ACPI_CPPC relies on getting the information it
needs via a HOB, so for only select that option in the FSP case for now.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: If597ff3dc824ce832399d3efde32352b36354b21
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80293
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/soc/amd/phoenix/Kconfig
1 file changed, 7 insertions(+), 1 deletion(-)
Approvals:
build bot (Jenkins): Verified
Arthur Heymans: Looks good to me, approved
diff --git a/src/soc/amd/phoenix/Kconfig b/src/soc/amd/phoenix/Kconfig
index fd40231..f37dd20 100644
--- a/src/soc/amd/phoenix/Kconfig
+++ b/src/soc/amd/phoenix/Kconfig
@@ -29,7 +29,7 @@
select SOC_AMD_COMMON_BLOCK_ACPI # TODO: Check if this is still correct
select SOC_AMD_COMMON_BLOCK_ACPIMMIO # TODO: Check if this is still correct
select SOC_AMD_COMMON_BLOCK_ACPI_ALIB # TODO: Check if this is still correct
- select SOC_AMD_COMMON_BLOCK_ACPI_CPPC
+ select SOC_AMD_COMMON_BLOCK_ACPI_CPPC if !SOC_AMD_PHOENIX_OPENSIL # TODO: add support for openSIL case
select SOC_AMD_COMMON_BLOCK_ACPI_CPU_POWER_STATE
select SOC_AMD_COMMON_BLOCK_ACPI_GPIO # TODO: Check if this is still correct
select SOC_AMD_COMMON_BLOCK_ACPI_IVRS # TODO: Check if this is still correct
@@ -100,6 +100,12 @@
help
AMD Phoenix support using FSP
+config SOC_AMD_PHOENIX_OPENSIL
+ bool
+ select SOC_AMD_PHOENIX_BASE
+ select SOC_AMD_OPENSIL
+ select SOC_AMD_OPENSIL_STUB
+
if SOC_AMD_PHOENIX_BASE
config CHIPSET_DEVICETREE
--
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Gerrit-Branch: main
Gerrit-Change-Id: If597ff3dc824ce832399d3efde32352b36354b21
Gerrit-Change-Number: 80293
Gerrit-PatchSet: 2
Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com>
Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com>
Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-MessageType: merged
Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80292?usp=email )
Change subject: vc/amd/opensil: add openSIL stub implementation
......................................................................
vc/amd/opensil: add openSIL stub implementation
Add a stub implementation of the openSIL interface between coreboot and
vendorcode. This can be used to add most of the coreboot-side support
for a SoC using openSIL without the actual opnSIL code already being
publicly available. Once the corresponding openSIL code is available,
the SoC can then switch over to using the actual openSIL implementation.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: I9284b0cbacba6eae7e2e7e69bc687f015076c2b0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80292
Reviewed-by: Martin L Roth <gaumless(a)gmail.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com>
---
M src/vendorcode/amd/opensil/Kconfig
M src/vendorcode/amd/opensil/Makefile.mk
A src/vendorcode/amd/opensil/stub/Makefile.mk
A src/vendorcode/amd/opensil/stub/opensil.h
A src/vendorcode/amd/opensil/stub/ramstage.c
A src/vendorcode/amd/opensil/stub/romstage.c
6 files changed, 97 insertions(+), 1 deletion(-)
Approvals:
build bot (Jenkins): Verified
Matt DeVillier: Looks good to me, but someone else must approve
Martin L Roth: Looks good to me, approved
diff --git a/src/vendorcode/amd/opensil/Kconfig b/src/vendorcode/amd/opensil/Kconfig
index bc80b8c..f0a303c 100644
--- a/src/vendorcode/amd/opensil/Kconfig
+++ b/src/vendorcode/amd/opensil/Kconfig
@@ -2,6 +2,13 @@
if SOC_AMD_OPENSIL
+config SOC_AMD_OPENSIL_STUB
+ bool
+ help
+ Select this option to include the openSIL stub in the build that can
+ be used for build-testing before the actual openSIL source code for a
+ SoC is released.
+
config SOC_AMD_OPENSIL_GENOA_POC
bool
help
diff --git a/src/vendorcode/amd/opensil/Makefile.mk b/src/vendorcode/amd/opensil/Makefile.mk
index a97bf63..3e8661d 100644
--- a/src/vendorcode/amd/opensil/Makefile.mk
+++ b/src/vendorcode/amd/opensil/Makefile.mk
@@ -2,6 +2,12 @@
ifeq ($(CONFIG_SOC_AMD_OPENSIL),y)
+ifeq ($(CONFIG_SOC_AMD_OPENSIL_STUB),y)
+
+subdirs-y += stub
+
+else # CONFIG_SOC_AMD_OPENSIL_STUB
+
ifneq ($(CONFIG_ARCH_RAMSTAGE_X86_32)$(CONFIG_ARCH_RAMSTAGE_X86_64),y)
$(error OpenSIL can only be built for either x86 or x86_64)
endif
@@ -90,4 +96,6 @@
romstage-libs += $(OBJPATH)/opensil.a
ramstage-libs += $(OBJPATH)/opensil.a
-endif
+endif # CONFIG_SOC_AMD_OPENSIL_STUB
+
+endif # CONFIG_SOC_AMD_OPENSIL
diff --git a/src/vendorcode/amd/opensil/stub/Makefile.mk b/src/vendorcode/amd/opensil/stub/Makefile.mk
new file mode 100644
index 0000000..29ef421
--- /dev/null
+++ b/src/vendorcode/amd/opensil/stub/Makefile.mk
@@ -0,0 +1,5 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+romstage-y += romstage.c
+
+ramstage-y += ramstage.c
\ No newline at end of file
diff --git a/src/vendorcode/amd/opensil/stub/opensil.h b/src/vendorcode/amd/opensil/stub/opensil.h
new file mode 100644
index 0000000..caa7b13
--- /dev/null
+++ b/src/vendorcode/amd/opensil/stub/opensil.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _OPENSIL_H_
+#define _OPENSIL_H_
+
+#include <acpi/acpi.h>
+
+// Add the memory map to dev, starting at index idx, returns last use idx
+void add_opensil_memmap(struct device *dev, unsigned long *idx);
+// Fill in FADT from openSIL
+void opensil_fill_fadt_io_ports(acpi_fadt_t *fadt);
+
+void setup_opensil(void);
+void opensil_xSIM_timepoint_1(void);
+void opensil_xSIM_timepoint_2(void);
+void opensil_xSIM_timepoint_3(void);
+
+#endif
diff --git a/src/vendorcode/amd/opensil/stub/ramstage.c b/src/vendorcode/amd/opensil/stub/ramstage.c
new file mode 100644
index 0000000..33ca447
--- /dev/null
+++ b/src/vendorcode/amd/opensil/stub/ramstage.c
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi.h>
+#include <device/device.h>
+#include "opensil.h"
+
+void add_opensil_memmap(struct device *dev, unsigned long *idx)
+{
+ printk(BIOS_NOTICE, "openSIL stub: %s\n", __func__);
+}
+
+void opensil_fill_fadt_io_ports(acpi_fadt_t *fadt)
+{
+ printk(BIOS_NOTICE, "openSIL stub: %s\n", __func__);
+}
+
+void setup_opensil(void)
+{
+ printk(BIOS_NOTICE, "openSIL stub: %s\n", __func__);
+}
+
+void opensil_xSIM_timepoint_1(void)
+{
+ printk(BIOS_NOTICE, "openSIL stub: %s\n", __func__);
+}
+
+void opensil_xSIM_timepoint_2(void)
+{
+ printk(BIOS_NOTICE, "openSIL stub: %s\n", __func__);
+}
+
+void opensil_xSIM_timepoint_3(void)
+{
+ printk(BIOS_NOTICE, "openSIL stub: %s\n", __func__);
+}
diff --git a/src/vendorcode/amd/opensil/stub/romstage.c b/src/vendorcode/amd/opensil/stub/romstage.c
new file mode 100644
index 0000000..36dff95
--- /dev/null
+++ b/src/vendorcode/amd/opensil/stub/romstage.c
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <cbmem.h>
+#include <console/console.h>
+#include <inttypes.h>
+
+uintptr_t cbmem_top_chipset(void)
+{
+ /* Since the stub doesn't have the openSIL function xPrfGetLowUsableDramAddress to
+ call, we just use 0xc0000000 here which should be a usable value in most cases */
+ uintptr_t top_mem = 0xc0000000;
+
+ printk(BIOS_NOTICE, "openSIL stub: %s retuns %" PRIxPTR "\n", __func__, top_mem);
+
+ /* The TSEG MSR has an 8M granularity. TSEG also needs to be aligned to its size so
+ account for potentially ill aligned TOP_MEM. */
+ if (CONFIG_SMM_TSEG_SIZE) {
+ top_mem -= CONFIG_SMM_TSEG_SIZE;
+ top_mem = ALIGN_DOWN(top_mem, CONFIG_SMM_TSEG_SIZE);
+ }
+
+ return top_mem;
+}
--
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Gerrit-Branch: main
Gerrit-Change-Id: I9284b0cbacba6eae7e2e7e69bc687f015076c2b0
Gerrit-Change-Number: 80292
Gerrit-PatchSet: 2
Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com>
Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com>
Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-MessageType: merged
Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80291?usp=email )
Change subject: soc/amd/common/amdblocks/pci_clk_req: remove unneeded include
......................................................................
soc/amd/common/amdblocks/pci_clk_req: remove unneeded include
Remove the unused soc/platform_descriptors.h include and add the missing
types.h include.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: Ie0b066aa5dc657f7709f9cce734a025180bf5bfe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80291
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com>
---
M src/soc/amd/common/block/include/amdblocks/pci_clk_req.h
1 file changed, 1 insertion(+), 1 deletion(-)
Approvals:
Matt DeVillier: Looks good to me, approved
build bot (Jenkins): Verified
diff --git a/src/soc/amd/common/block/include/amdblocks/pci_clk_req.h b/src/soc/amd/common/block/include/amdblocks/pci_clk_req.h
index 32dadf4..7c10e5d 100644
--- a/src/soc/amd/common/block/include/amdblocks/pci_clk_req.h
+++ b/src/soc/amd/common/block/include/amdblocks/pci_clk_req.h
@@ -3,7 +3,7 @@
#ifndef AMD_BLOCK_PCI_GPP_H
#define AMD_BLOCK_PCI_GPP_H
-#include <soc/platform_descriptors.h>
+#include <types.h>
enum gpp_clk_req {
GPP_CLK_ON, /* GPP clock always on; default */
--
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Gerrit-Change-Id: Ie0b066aa5dc657f7709f9cce734a025180bf5bfe
Gerrit-Change-Number: 80291
Gerrit-PatchSet: 2
Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com>
Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com>
Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-MessageType: merged
Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80289?usp=email )
Change subject: mb/amd/birman/Kconfig: fix comment on endif
......................................................................
mb/amd/birman/Kconfig: fix comment on endif
The last 'endif' belongs to the 'if BOARD_AMD_BIRMAN_COMMON' in line 26,
so fix the comment. Commit 35a30de7afcc ("mb/amd/birman: Use common
option for variant configuration") changed that condition, but missed
updating this comment, so do this now.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: I986e5a456e8f9fd92aacd007479c861feea06199
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80289
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com>
Reviewed-by: Varshit Pandya <pandyavarshit(a)gmail.com>
---
M src/mainboard/amd/birman/Kconfig
1 file changed, 1 insertion(+), 1 deletion(-)
Approvals:
build bot (Jenkins): Verified
Matt DeVillier: Looks good to me, approved
Varshit Pandya: Looks good to me, approved
diff --git a/src/mainboard/amd/birman/Kconfig b/src/mainboard/amd/birman/Kconfig
index 8d7de450..3b9d607 100644
--- a/src/mainboard/amd/birman/Kconfig
+++ b/src/mainboard/amd/birman/Kconfig
@@ -153,4 +153,4 @@
endif # !EM100
-endif # BOARD_AMD_BIRMAN_GLINDA || BOARD_AMD_BIRMAN_PHOENIX
+endif # BOARD_AMD_BIRMAN_COMMON
--
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Gerrit-Branch: main
Gerrit-Change-Id: I986e5a456e8f9fd92aacd007479c861feea06199
Gerrit-Change-Number: 80289
Gerrit-PatchSet: 2
Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com>
Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com>
Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com>
Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-MessageType: merged
Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80288?usp=email )
Change subject: soc/amd/phoenix/Makefile: only include FSP folder conditionally
......................................................................
soc/amd/phoenix/Makefile: only include FSP folder conditionally
Only add the vendorcode/amd/fsp/phoenix and vendorcode/amd/fsp/common
folders to the include search path when the SOC_AMD_PHOENIX_FSP Kconfig
option is selected.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: I18668ab8578b297c328fdc647c8a95f540ac6272
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80288
Reviewed-by: Varshit Pandya <pandyavarshit(a)gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M src/soc/amd/phoenix/Makefile.mk
1 file changed, 3 insertions(+), 0 deletions(-)
Approvals:
Matt DeVillier: Looks good to me, approved
Varshit Pandya: Looks good to me, approved
build bot (Jenkins): Verified
diff --git a/src/soc/amd/phoenix/Makefile.mk b/src/soc/amd/phoenix/Makefile.mk
index feb9b1a..9c775cc 100644
--- a/src/soc/amd/phoenix/Makefile.mk
+++ b/src/soc/amd/phoenix/Makefile.mk
@@ -42,8 +42,11 @@
CPPFLAGS_common += -I$(src)/soc/amd/phoenix/include
CPPFLAGS_common += -I$(src)/soc/amd/phoenix/acpi
+
+ifeq ($(CONFIG_SOC_AMD_PHOENIX_FSP),y)
CPPFLAGS_common += -I$(src)/vendorcode/amd/fsp/phoenix
CPPFLAGS_common += -I$(src)/vendorcode/amd/fsp/common
+endif
# Building the cbfs image will fail if the offset, aligned to 64 bytes, isn't large enough
ifeq ($(CONFIG_CBFS_VERIFICATION),y)
--
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Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: I18668ab8578b297c328fdc647c8a95f540ac6272
Gerrit-Change-Number: 80288
Gerrit-PatchSet: 2
Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com>
Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com>
Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com>
Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-MessageType: merged
Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80287?usp=email )
Change subject: vc/amd/opensil/genoa_poc: remove xSIM-api dependency from opensil.h
......................................................................
vc/amd/opensil/genoa_poc: remove xSIM-api dependency from opensil.h
Provide 3 separate functions for each openSIL time point instead of one,
so that we don't need the xSIM-api header file to be included in
opensil.h to decouple the coreboot code more form the openSIL code. This
will allow to create an openSIL stub implementation to already get most
of the coreboot-side SoC code in place before the openSIL source code is
done and released.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: I969bc0862560b7254c48f04e9a03387417f328bc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80287
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz>
Reviewed-by: Varshit Pandya <pandyavarshit(a)gmail.com>
---
M src/soc/amd/genoa_poc/chip.c
M src/vendorcode/amd/opensil/genoa_poc/opensil.h
M src/vendorcode/amd/opensil/genoa_poc/ramstage.c
3 files changed, 20 insertions(+), 4 deletions(-)
Approvals:
build bot (Jenkins): Verified
Arthur Heymans: Looks good to me, approved
Varshit Pandya: Looks good to me, approved
diff --git a/src/soc/amd/genoa_poc/chip.c b/src/soc/amd/genoa_poc/chip.c
index d397800..13ede84 100644
--- a/src/soc/amd/genoa_poc/chip.c
+++ b/src/soc/amd/genoa_poc/chip.c
@@ -11,7 +11,7 @@
default_dev_ops_root.write_acpi_tables = soc_acpi_write_tables;
setup_opensil();
- opensil_entry(SIL_TP1);
+ opensil_xSIM_timepoint_1();
fch_init(chip_info);
}
diff --git a/src/vendorcode/amd/opensil/genoa_poc/opensil.h b/src/vendorcode/amd/opensil/genoa_poc/opensil.h
index e225522..334903f 100644
--- a/src/vendorcode/amd/opensil/genoa_poc/opensil.h
+++ b/src/vendorcode/amd/opensil/genoa_poc/opensil.h
@@ -4,7 +4,6 @@
#define _OPENSIL_H_
#include <acpi/acpi.h>
-#include <xSIM-api.h>
void SIL_STATUS_report(const char *function, const int status);
// Add the memory map to dev, starting at index idx, returns last use idx
@@ -15,6 +14,8 @@
void configure_mpio(void);
void setup_opensil(void);
-void opensil_entry(SIL_TIMEPOINT timepoint);
+void opensil_xSIM_timepoint_1(void);
+void opensil_xSIM_timepoint_2(void);
+void opensil_xSIM_timepoint_3(void);
#endif
diff --git a/src/vendorcode/amd/opensil/genoa_poc/ramstage.c b/src/vendorcode/amd/opensil/genoa_poc/ramstage.c
index 11289bb..758b284 100644
--- a/src/vendorcode/amd/opensil/genoa_poc/ramstage.c
+++ b/src/vendorcode/amd/opensil/genoa_poc/ramstage.c
@@ -129,7 +129,7 @@
configure_mpio();
}
-void opensil_entry(SIL_TIMEPOINT timepoint)
+static void opensil_entry(SIL_TIMEPOINT timepoint)
{
SIL_STATUS ret;
SIL_TIMEPOINT tp = (uintptr_t)timepoint;
@@ -160,4 +160,19 @@
}
}
+void opensil_xSIM_timepoint_1(void)
+{
+ opensil_entry(SIL_TP1);
+}
+
+void opensil_xSIM_timepoint_2(void)
+{
+ opensil_entry(SIL_TP2);
+}
+
+void opensil_xSIM_timepoint_3(void)
+{
+ opensil_entry(SIL_TP3);
+}
+
/* TODO: also call timepoints 2 and 3 from coreboot. Are they NOOP? */
--
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Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: I969bc0862560b7254c48f04e9a03387417f328bc
Gerrit-Change-Number: 80287
Gerrit-PatchSet: 2
Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-MessageType: merged