coreboot-gerrit February 2024

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[main]: soc/amd/phoenix/fch: only init ACPI IO ports in FSP case
by Felix Held (Code Review) 02 Feb '24

02 Feb '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80297?usp=email ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/amd/phoenix/fch: only init ACPI IO ports in FSP case ...................................................................... soc/amd/phoenix/fch: only init ACPI IO ports in FSP case Since openSIL configures the APCI IO port addresses, coreboot should not overwrite them. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: If10e5a9f52ab313ad1afebd7f9e722994d48b0a7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80297 Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/phoenix/fch.c 1 file changed, 6 insertions(+), 4 deletions(-) Approvals: Matt DeVillier: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/amd/phoenix/fch.c b/src/soc/amd/phoenix/fch.c index e9bc80a..1e03cda 100644 --- a/src/soc/amd/phoenix/fch.c +++ b/src/soc/amd/phoenix/fch.c @@ -89,10 +89,12 @@ * ACPI tables are generated. Enable these ports indiscriminately. */ - pm_write16(PM_EVT_BLK, ACPI_PM_EVT_BLK); - pm_write16(PM1_CNT_BLK, ACPI_PM1_CNT_BLK); - pm_write16(PM_TMR_BLK, ACPI_PM_TMR_BLK); - pm_write16(PM_GPE0_BLK, ACPI_GPE0_BLK); + if (CONFIG(PLATFORM_USES_FSP2_0)) { + pm_write16(PM_EVT_BLK, ACPI_PM_EVT_BLK); + pm_write16(PM1_CNT_BLK, ACPI_PM1_CNT_BLK); + pm_write16(PM_TMR_BLK, ACPI_PM_TMR_BLK); + pm_write16(PM_GPE0_BLK, ACPI_GPE0_BLK); + } if (CONFIG(HAVE_SMI_HANDLER)) { /* APMC - SMI Command Port */ -- To view, visit https://review.coreboot.org/c/coreboot/+/80297?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If10e5a9f52ab313ad1afebd7f9e722994d48b0a7 Gerrit-Change-Number: 80297 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[main]: soc/amd/phoenix: add openSIL calls
by Felix Held (Code Review) 02 Feb '24

02 Feb '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80296?usp=email ) Change subject: soc/amd/phoenix: add openSIL calls ...................................................................... soc/amd/phoenix: add openSIL calls Add the calls to the openSIL stubs to do the silicon initialization, to get the APCI IO ports, and to get the memory map. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I6f37bf211e130cb44927f8a0e7f9134d246dfc1c Reviewed-on: https://review.coreboot.org/c/coreboot/+/80296 Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/phoenix/acpi.c M src/soc/amd/phoenix/chip.c M src/soc/amd/phoenix/memmap.c 3 files changed, 20 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved diff --git a/src/soc/amd/phoenix/acpi.c b/src/soc/amd/phoenix/acpi.c index a6482ee..606a45f 100644 --- a/src/soc/amd/phoenix/acpi.c +++ b/src/soc/amd/phoenix/acpi.c @@ -19,6 +19,7 @@ #include <device/device.h> #include <soc/iomap.h> #include <types.h> +#include <vendorcode/amd/opensil/genoa_poc/opensil.h> #include "chip.h" /* @@ -29,12 +30,17 @@ { const struct soc_amd_phoenix_config *cfg = config_of_soc(); - printk(BIOS_DEBUG, "pm_base: 0x%04x\n", ACPI_IO_BASE); + if (CONFIG(PLATFORM_USES_FSP2_0)) { + printk(BIOS_DEBUG, "pm_base: 0x%04x\n", ACPI_IO_BASE); - fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK; - fadt->pm1a_cnt_blk = ACPI_PM1_CNT_BLK; - fadt->pm_tmr_blk = ACPI_PM_TMR_BLK; - fadt->gpe0_blk = ACPI_GPE0_BLK; + fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK; + fadt->pm1a_cnt_blk = ACPI_PM1_CNT_BLK; + fadt->pm_tmr_blk = ACPI_PM_TMR_BLK; + fadt->gpe0_blk = ACPI_GPE0_BLK; + } else { + /* Fill in pm1_evt, pm1_cnt, pm_tmr, gpe0_blk from openSIL input structure */ + opensil_fill_fadt_io_ports(fadt); + } fadt->pm1_evt_len = 4; /* 32 bits */ fadt->pm1_cnt_len = 2; /* 16 bits */ diff --git a/src/soc/amd/phoenix/chip.c b/src/soc/amd/phoenix/chip.c index 2291945..a9b0e57 100644 --- a/src/soc/amd/phoenix/chip.c +++ b/src/soc/amd/phoenix/chip.c @@ -12,6 +12,7 @@ #include <soc/pci_devs.h> #include <soc/southbridge.h> #include <types.h> +#include <vendorcode/amd/opensil/stub/opensil.h> #include "chip.h" static const char *soc_acpi_name(const struct device *dev) @@ -39,8 +40,12 @@ { default_dev_ops_root.write_acpi_tables = soc_acpi_write_tables; - if (CONFIG(PLATFORM_USES_FSP2_0)) + if (CONFIG(PLATFORM_USES_FSP2_0)) { amd_fsp_silicon_init(); + } else { + setup_opensil(); + opensil_xSIM_timepoint_1(); + } data_fabric_set_mmio_np(); diff --git a/src/soc/amd/phoenix/memmap.c b/src/soc/amd/phoenix/memmap.c index 432d850..e516572 100644 --- a/src/soc/amd/phoenix/memmap.c +++ b/src/soc/amd/phoenix/memmap.c @@ -7,6 +7,7 @@ #include <cbmem.h> #include <device/device.h> #include <stdint.h> +#include <vendorcode/amd/opensil/stub/opensil.h> /* * +--------------------------------+ @@ -96,4 +97,6 @@ if (CONFIG(PLATFORM_USES_FSP2_0)) read_fsp_resources(dev, idx); + else + add_opensil_memmap(dev, idx); } -- To view, visit https://review.coreboot.org/c/coreboot/+/80296?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6f37bf211e130cb44927f8a0e7f9134d246dfc1c Gerrit-Change-Number: 80296 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: soc/amd/phoenix/fch: only call gpp_clk_setup in FSP case
by Felix Held (Code Review) 02 Feb '24

02 Feb '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80295?usp=email ) Change subject: soc/amd/phoenix/fch: only call gpp_clk_setup in FSP case ...................................................................... soc/amd/phoenix/fch: only call gpp_clk_setup in FSP case The configuration of the PCIe clock generators in the FCH was moved from the FSP to coreboot, since all registers are documented. This initialization is however tightly integrated in the rest of the PCIe init code inside the reference code. In the FSP case, this code was manually removed. openSIL will do that part of the initialization so that there's no coreboot-specific change needed in openSIL. This will also avoid the problems caused by mismatching configurations done by the coreboot code and the PCIe init part of the reference code. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I6d64285a301ade6860c07e62dcb1a718e7a96644 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80295 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> --- M src/soc/amd/phoenix/fch.c 1 file changed, 3 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved diff --git a/src/soc/amd/phoenix/fch.c b/src/soc/amd/phoenix/fch.c index c2f0558..e9bc80a 100644 --- a/src/soc/amd/phoenix/fch.c +++ b/src/soc/amd/phoenix/fch.c @@ -200,7 +200,9 @@ acpi_pm_gpe_add_events_print_events(); gpio_add_events(); - gpp_clk_setup(); + if (CONFIG(PLATFORM_USES_FSP2_0)) + gpp_clk_setup(); + fch_clk_output_48Mhz(); cgpll_clock_gate_init(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/80295?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6d64285a301ade6860c07e62dcb1a718e7a96644 Gerrit-Change-Number: 80295 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[main]: soc/amd/phoenix: add get_pci_routing_table stub for non-FSP case
by Felix Held (Code Review) 02 Feb '24

02 Feb '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80294?usp=email ) Change subject: soc/amd/phoenix: add get_pci_routing_table stub for non-FSP case ...................................................................... soc/amd/phoenix: add get_pci_routing_table stub for non-FSP case In the FSP case we get this info via a HOB. It's currently unclear if we'll get a data structure for this from openSIL or if we'll end up being able to just read the configuration fro the hardware, so add a get_pci_routing_table stub for now to be able to build. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I5003e287d6a3a9320922beaffff8a3a846531e14 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80294 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> --- M src/soc/amd/phoenix/Makefile.mk A src/soc/amd/phoenix/pci_irq_routing.c 2 files changed, 15 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved diff --git a/src/soc/amd/phoenix/Makefile.mk b/src/soc/amd/phoenix/Makefile.mk index 9c775cc..be0a022 100644 --- a/src/soc/amd/phoenix/Makefile.mk +++ b/src/soc/amd/phoenix/Makefile.mk @@ -32,6 +32,7 @@ ramstage-y += graphics.c ramstage-y += mca.c ramstage-y += memmap.c +ramstage-$(CONFIG_SOC_AMD_PHOENIX_OPENSIL) += pci_irq_routing.c ramstage-y += root_complex.c ramstage-y += soc_util.c ramstage-y += xhci.c diff --git a/src/soc/amd/phoenix/pci_irq_routing.c b/src/soc/amd/phoenix/pci_irq_routing.c new file mode 100644 index 0000000..5c891c2 --- /dev/null +++ b/src/soc/amd/phoenix/pci_irq_routing.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <amdblocks/amd_pci_util.h> +#include <console/console.h> +#include <types.h> + +const struct pci_routing_info *get_pci_routing_table(size_t *entries) +{ + /* TODO: still needs to be implemented for the non-FSP case */ + printk(BIOS_NOTICE, "%s stub: returning empty IRQ routing table\n", __func__); + + *entries = 0; + return NULL; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/80294?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5003e287d6a3a9320922beaffff8a3a846531e14 Gerrit-Change-Number: 80294 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: soc/amd/phoenix/Kconfig: add SOC_AMD_PHOENIX_OPENSIL option
by Felix Held (Code Review) 02 Feb '24

02 Feb '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80293?usp=email ) Change subject: soc/amd/phoenix/Kconfig: add SOC_AMD_PHOENIX_OPENSIL option ...................................................................... soc/amd/phoenix/Kconfig: add SOC_AMD_PHOENIX_OPENSIL option Add the SOC_AMD_PHOENIX_OPENSIL Kconfig option to be able to build the Phoenix code using openSIL instead of FSP for initializing the hardware. Since there's currently no publicly available openSIL code for Phoenix, SOC_AMD_OPENSIL_STUB is selected to have the stubs added to the build instead of the actual openSIL code. The code added by selecting SOC_AMD_COMMON_BLOCK_ACPI_CPPC relies on getting the information it needs via a HOB, so for only select that option in the FSP case for now. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: If597ff3dc824ce832399d3efde32352b36354b21 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80293 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/amd/phoenix/Kconfig 1 file changed, 7 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved diff --git a/src/soc/amd/phoenix/Kconfig b/src/soc/amd/phoenix/Kconfig index fd40231..f37dd20 100644 --- a/src/soc/amd/phoenix/Kconfig +++ b/src/soc/amd/phoenix/Kconfig @@ -29,7 +29,7 @@ select SOC_AMD_COMMON_BLOCK_ACPI # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_ACPIMMIO # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_ACPI_ALIB # TODO: Check if this is still correct - select SOC_AMD_COMMON_BLOCK_ACPI_CPPC + select SOC_AMD_COMMON_BLOCK_ACPI_CPPC if !SOC_AMD_PHOENIX_OPENSIL # TODO: add support for openSIL case select SOC_AMD_COMMON_BLOCK_ACPI_CPU_POWER_STATE select SOC_AMD_COMMON_BLOCK_ACPI_GPIO # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_ACPI_IVRS # TODO: Check if this is still correct @@ -100,6 +100,12 @@ help AMD Phoenix support using FSP +config SOC_AMD_PHOENIX_OPENSIL + bool + select SOC_AMD_PHOENIX_BASE + select SOC_AMD_OPENSIL + select SOC_AMD_OPENSIL_STUB + if SOC_AMD_PHOENIX_BASE config CHIPSET_DEVICETREE -- To view, visit https://review.coreboot.org/c/coreboot/+/80293?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If597ff3dc824ce832399d3efde32352b36354b21 Gerrit-Change-Number: 80293 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[main]: vc/amd/opensil: add openSIL stub implementation
by Felix Held (Code Review) 02 Feb '24

02 Feb '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80292?usp=email ) Change subject: vc/amd/opensil: add openSIL stub implementation ...................................................................... vc/amd/opensil: add openSIL stub implementation Add a stub implementation of the openSIL interface between coreboot and vendorcode. This can be used to add most of the coreboot-side support for a SoC using openSIL without the actual opnSIL code already being publicly available. Once the corresponding openSIL code is available, the SoC can then switch over to using the actual openSIL implementation. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I9284b0cbacba6eae7e2e7e69bc687f015076c2b0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80292 Reviewed-by: Martin L Roth <gaumless(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> --- M src/vendorcode/amd/opensil/Kconfig M src/vendorcode/amd/opensil/Makefile.mk A src/vendorcode/amd/opensil/stub/Makefile.mk A src/vendorcode/amd/opensil/stub/opensil.h A src/vendorcode/amd/opensil/stub/ramstage.c A src/vendorcode/amd/opensil/stub/romstage.c 6 files changed, 97 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, but someone else must approve Martin L Roth: Looks good to me, approved diff --git a/src/vendorcode/amd/opensil/Kconfig b/src/vendorcode/amd/opensil/Kconfig index bc80b8c..f0a303c 100644 --- a/src/vendorcode/amd/opensil/Kconfig +++ b/src/vendorcode/amd/opensil/Kconfig @@ -2,6 +2,13 @@ if SOC_AMD_OPENSIL +config SOC_AMD_OPENSIL_STUB + bool + help + Select this option to include the openSIL stub in the build that can + be used for build-testing before the actual openSIL source code for a + SoC is released. + config SOC_AMD_OPENSIL_GENOA_POC bool help diff --git a/src/vendorcode/amd/opensil/Makefile.mk b/src/vendorcode/amd/opensil/Makefile.mk index a97bf63..3e8661d 100644 --- a/src/vendorcode/amd/opensil/Makefile.mk +++ b/src/vendorcode/amd/opensil/Makefile.mk @@ -2,6 +2,12 @@ ifeq ($(CONFIG_SOC_AMD_OPENSIL),y) +ifeq ($(CONFIG_SOC_AMD_OPENSIL_STUB),y) + +subdirs-y += stub + +else # CONFIG_SOC_AMD_OPENSIL_STUB + ifneq ($(CONFIG_ARCH_RAMSTAGE_X86_32)$(CONFIG_ARCH_RAMSTAGE_X86_64),y) $(error OpenSIL can only be built for either x86 or x86_64) endif @@ -90,4 +96,6 @@ romstage-libs += $(OBJPATH)/opensil.a ramstage-libs += $(OBJPATH)/opensil.a -endif +endif # CONFIG_SOC_AMD_OPENSIL_STUB + +endif # CONFIG_SOC_AMD_OPENSIL diff --git a/src/vendorcode/amd/opensil/stub/Makefile.mk b/src/vendorcode/amd/opensil/stub/Makefile.mk new file mode 100644 index 0000000..29ef421 --- /dev/null +++ b/src/vendorcode/amd/opensil/stub/Makefile.mk @@ -0,0 +1,5 @@ +## SPDX-License-Identifier: GPL-2.0-only + +romstage-y += romstage.c + +ramstage-y += ramstage.c \ No newline at end of file diff --git a/src/vendorcode/amd/opensil/stub/opensil.h b/src/vendorcode/amd/opensil/stub/opensil.h new file mode 100644 index 0000000..caa7b13 --- /dev/null +++ b/src/vendorcode/amd/opensil/stub/opensil.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _OPENSIL_H_ +#define _OPENSIL_H_ + +#include <acpi/acpi.h> + +// Add the memory map to dev, starting at index idx, returns last use idx +void add_opensil_memmap(struct device *dev, unsigned long *idx); +// Fill in FADT from openSIL +void opensil_fill_fadt_io_ports(acpi_fadt_t *fadt); + +void setup_opensil(void); +void opensil_xSIM_timepoint_1(void); +void opensil_xSIM_timepoint_2(void); +void opensil_xSIM_timepoint_3(void); + +#endif diff --git a/src/vendorcode/amd/opensil/stub/ramstage.c b/src/vendorcode/amd/opensil/stub/ramstage.c new file mode 100644 index 0000000..33ca447 --- /dev/null +++ b/src/vendorcode/amd/opensil/stub/ramstage.c @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> +#include <device/device.h> +#include "opensil.h" + +void add_opensil_memmap(struct device *dev, unsigned long *idx) +{ + printk(BIOS_NOTICE, "openSIL stub: %s\n", __func__); +} + +void opensil_fill_fadt_io_ports(acpi_fadt_t *fadt) +{ + printk(BIOS_NOTICE, "openSIL stub: %s\n", __func__); +} + +void setup_opensil(void) +{ + printk(BIOS_NOTICE, "openSIL stub: %s\n", __func__); +} + +void opensil_xSIM_timepoint_1(void) +{ + printk(BIOS_NOTICE, "openSIL stub: %s\n", __func__); +} + +void opensil_xSIM_timepoint_2(void) +{ + printk(BIOS_NOTICE, "openSIL stub: %s\n", __func__); +} + +void opensil_xSIM_timepoint_3(void) +{ + printk(BIOS_NOTICE, "openSIL stub: %s\n", __func__); +} diff --git a/src/vendorcode/amd/opensil/stub/romstage.c b/src/vendorcode/amd/opensil/stub/romstage.c new file mode 100644 index 0000000..36dff95 --- /dev/null +++ b/src/vendorcode/amd/opensil/stub/romstage.c @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <cbmem.h> +#include <console/console.h> +#include <inttypes.h> + +uintptr_t cbmem_top_chipset(void) +{ + /* Since the stub doesn't have the openSIL function xPrfGetLowUsableDramAddress to + call, we just use 0xc0000000 here which should be a usable value in most cases */ + uintptr_t top_mem = 0xc0000000; + + printk(BIOS_NOTICE, "openSIL stub: %s retuns %" PRIxPTR "\n", __func__, top_mem); + + /* The TSEG MSR has an 8M granularity. TSEG also needs to be aligned to its size so + account for potentially ill aligned TOP_MEM. */ + if (CONFIG_SMM_TSEG_SIZE) { + top_mem -= CONFIG_SMM_TSEG_SIZE; + top_mem = ALIGN_DOWN(top_mem, CONFIG_SMM_TSEG_SIZE); + } + + return top_mem; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/80292?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9284b0cbacba6eae7e2e7e69bc687f015076c2b0 Gerrit-Change-Number: 80292 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: soc/amd/common/amdblocks/pci_clk_req: remove unneeded include
by Felix Held (Code Review) 02 Feb '24

02 Feb '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80291?usp=email ) Change subject: soc/amd/common/amdblocks/pci_clk_req: remove unneeded include ...................................................................... soc/amd/common/amdblocks/pci_clk_req: remove unneeded include Remove the unused soc/platform_descriptors.h include and add the missing types.h include. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ie0b066aa5dc657f7709f9cce734a025180bf5bfe Reviewed-on: https://review.coreboot.org/c/coreboot/+/80291 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> --- M src/soc/amd/common/block/include/amdblocks/pci_clk_req.h 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: Matt DeVillier: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/amd/common/block/include/amdblocks/pci_clk_req.h b/src/soc/amd/common/block/include/amdblocks/pci_clk_req.h index 32dadf4..7c10e5d 100644 --- a/src/soc/amd/common/block/include/amdblocks/pci_clk_req.h +++ b/src/soc/amd/common/block/include/amdblocks/pci_clk_req.h @@ -3,7 +3,7 @@ #ifndef AMD_BLOCK_PCI_GPP_H #define AMD_BLOCK_PCI_GPP_H -#include <soc/platform_descriptors.h> +#include <types.h> enum gpp_clk_req { GPP_CLK_ON, /* GPP clock always on; default */ -- To view, visit https://review.coreboot.org/c/coreboot/+/80291?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie0b066aa5dc657f7709f9cce734a025180bf5bfe Gerrit-Change-Number: 80291 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[main]: mb/amd/birman: add _FSP postfix to BOARD_AMD_BIRMAN_PHOENIX
by Felix Held (Code Review) 02 Feb '24

02 Feb '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80290?usp=email ) Change subject: mb/amd/birman: add _FSP postfix to BOARD_AMD_BIRMAN_PHOENIX ...................................................................... mb/amd/birman: add _FSP postfix to BOARD_AMD_BIRMAN_PHOENIX Rename the BOARD_AMD_BIRMAN_PHOENIX option to BOARD_AMD_BIRMAN_PHOENIX_FSP to distinguish between the FSP-based SoC initialization and the non-FSP based one. Also change the MAINBOARD_PART_NUMBER string to 'Birman_Phoenix_FSP'. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Id3293a07cd1b1833df15ee0a40cad3127e19b7df Reviewed-on: https://review.coreboot.org/c/coreboot/+/80290 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> --- M src/mainboard/amd/birman/Kconfig M src/mainboard/amd/birman/Kconfig.name M src/mainboard/amd/birman/Makefile.mk 3 files changed, 7 insertions(+), 7 deletions(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved diff --git a/src/mainboard/amd/birman/Kconfig b/src/mainboard/amd/birman/Kconfig index 3b9d607..cd7e938 100644 --- a/src/mainboard/amd/birman/Kconfig +++ b/src/mainboard/amd/birman/Kconfig @@ -15,7 +15,7 @@ select SOC_AMD_COMMON_BLOCK_SIMNOW_SUPPORTED select SPI_FLASH_EXIT_4_BYTE_ADDR_MODE -config BOARD_AMD_BIRMAN_PHOENIX +config BOARD_AMD_BIRMAN_PHOENIX_FSP select BOARD_AMD_BIRMAN_COMMON select SOC_AMD_PHOENIX_FSP @@ -27,7 +27,7 @@ config FMDFILE default "src/mainboard/amd/birman/chromeos_glinda.fmd" if CHROMEOS && BOARD_AMD_BIRMAN_GLINDA - default "src/mainboard/amd/birman/chromeos_phoenix.fmd" if CHROMEOS && BOARD_AMD_BIRMAN_PHOENIX + default "src/mainboard/amd/birman/chromeos_phoenix.fmd" if CHROMEOS && BOARD_AMD_BIRMAN_PHOENIX_FSP default "src/mainboard/amd/birman/board_glinda.fmd" if BOARD_AMD_BIRMAN_GLINDA default "src/mainboard/amd/birman/board_phoenix.fmd" @@ -36,7 +36,7 @@ config MAINBOARD_PART_NUMBER default "Birman_Glinda" if BOARD_AMD_BIRMAN_GLINDA - default "Birman_Phoenix" + default "Birman_Phoenix_FSP" if BOARD_AMD_BIRMAN_PHOENIX_FSP config DEVICETREE default "devicetree_glinda.cb" if BOARD_AMD_BIRMAN_GLINDA diff --git a/src/mainboard/amd/birman/Kconfig.name b/src/mainboard/amd/birman/Kconfig.name index c02173c..9eee171 100644 --- a/src/mainboard/amd/birman/Kconfig.name +++ b/src/mainboard/amd/birman/Kconfig.name @@ -1,7 +1,7 @@ comment "Birman" -config BOARD_AMD_BIRMAN_PHOENIX - bool "-> Birman for Phoenix SoC" +config BOARD_AMD_BIRMAN_PHOENIX_FSP + bool "-> Birman for Phoenix SoC using FSP" config BOARD_AMD_BIRMAN_GLINDA bool "-> Birman for Glinda SoC" diff --git a/src/mainboard/amd/birman/Makefile.mk b/src/mainboard/amd/birman/Makefile.mk index 4dba53e..6c417ce 100644 --- a/src/mainboard/amd/birman/Makefile.mk +++ b/src/mainboard/amd/birman/Makefile.mk @@ -4,12 +4,12 @@ bootblock-y += early_gpio.c bootblock-y += ec.c -romstage-$(CONFIG_BOARD_AMD_BIRMAN_PHOENIX) += port_descriptors_phoenix.c +romstage-$(CONFIG_BOARD_AMD_BIRMAN_PHOENIX_FSP) += port_descriptors_phoenix.c romstage-$(CONFIG_BOARD_AMD_BIRMAN_GLINDA) += port_descriptors_glinda.c ramstage-y += chromeos.c ramstage-y += gpio.c -ramstage-$(CONFIG_BOARD_AMD_BIRMAN_PHOENIX) += port_descriptors_phoenix.c +ramstage-$(CONFIG_BOARD_AMD_BIRMAN_PHOENIX_FSP) += port_descriptors_phoenix.c ramstage-$(CONFIG_BOARD_AMD_BIRMAN_GLINDA) += port_descriptors_glinda.c ifneq ($(wildcard $(MAINBOARD_BLOBS_DIR)/APCB_FP8_LPDDR5.bin),) -- To view, visit https://review.coreboot.org/c/coreboot/+/80290?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id3293a07cd1b1833df15ee0a40cad3127e19b7df Gerrit-Change-Number: 80290 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: mb/amd/birman/Kconfig: fix comment on endif
by Felix Held (Code Review) 02 Feb '24

02 Feb '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80289?usp=email ) Change subject: mb/amd/birman/Kconfig: fix comment on endif ...................................................................... mb/amd/birman/Kconfig: fix comment on endif The last 'endif' belongs to the 'if BOARD_AMD_BIRMAN_COMMON' in line 26, so fix the comment. Commit 35a30de7afcc ("mb/amd/birman: Use common option for variant configuration") changed that condition, but missed updating this comment, so do this now. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I986e5a456e8f9fd92aacd007479c861feea06199 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80289 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Reviewed-by: Varshit Pandya <pandyavarshit(a)gmail.com> --- M src/mainboard/amd/birman/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved Varshit Pandya: Looks good to me, approved diff --git a/src/mainboard/amd/birman/Kconfig b/src/mainboard/amd/birman/Kconfig index 8d7de450..3b9d607 100644 --- a/src/mainboard/amd/birman/Kconfig +++ b/src/mainboard/amd/birman/Kconfig @@ -153,4 +153,4 @@ endif # !EM100 -endif # BOARD_AMD_BIRMAN_GLINDA || BOARD_AMD_BIRMAN_PHOENIX +endif # BOARD_AMD_BIRMAN_COMMON -- To view, visit https://review.coreboot.org/c/coreboot/+/80289?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I986e5a456e8f9fd92aacd007479c861feea06199 Gerrit-Change-Number: 80289 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: soc/amd/phoenix/Makefile: only include FSP folder conditionally
by Felix Held (Code Review) 02 Feb '24

02 Feb '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80288?usp=email ) Change subject: soc/amd/phoenix/Makefile: only include FSP folder conditionally ...................................................................... soc/amd/phoenix/Makefile: only include FSP folder conditionally Only add the vendorcode/amd/fsp/phoenix and vendorcode/amd/fsp/common folders to the include search path when the SOC_AMD_PHOENIX_FSP Kconfig option is selected. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I18668ab8578b297c328fdc647c8a95f540ac6272 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80288 Reviewed-by: Varshit Pandya <pandyavarshit(a)gmail.com> Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/phoenix/Makefile.mk 1 file changed, 3 insertions(+), 0 deletions(-) Approvals: Matt DeVillier: Looks good to me, approved Varshit Pandya: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/amd/phoenix/Makefile.mk b/src/soc/amd/phoenix/Makefile.mk index feb9b1a..9c775cc 100644 --- a/src/soc/amd/phoenix/Makefile.mk +++ b/src/soc/amd/phoenix/Makefile.mk @@ -42,8 +42,11 @@ CPPFLAGS_common += -I$(src)/soc/amd/phoenix/include CPPFLAGS_common += -I$(src)/soc/amd/phoenix/acpi + +ifeq ($(CONFIG_SOC_AMD_PHOENIX_FSP),y) CPPFLAGS_common += -I$(src)/vendorcode/amd/fsp/phoenix CPPFLAGS_common += -I$(src)/vendorcode/amd/fsp/common +endif # Building the cbfs image will fail if the offset, aligned to 64 bytes, isn't large enough ifeq ($(CONFIG_CBFS_VERIFICATION),y) -- To view, visit https://review.coreboot.org/c/coreboot/+/80288?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I18668ab8578b297c328fdc647c8a95f540ac6272 Gerrit-Change-Number: 80288 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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