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Change subject: drivers/wifi: Use depends instead of if in Kconfig
......................................................................
Patch Set 2: Code-Review+2
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Change subject: drivers/wifi: Add MTCL function to ACPI SSDT
......................................................................
Patch Set 19: Code-Review+2
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Change subject: cpu/x86: Link page tables in stage if possible
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
LGTM other than Arthur's request to move the picasso change to a separate patch.
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Change subject: cpu/x86/Kconfig: Mark 64bit support as stable
......................................................................
Patch Set 1: Code-Review+2
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Hello Arthur Heymans, Caveh Jalali, Christian Walter, Cliff Huang, Felix Held, Forest Mittelberg, Fred Reitberger, Hung-Te Lin, Jakub Czapiga, Jason Glenesk, Jeff Daly, Johnny Lin, Jonathan Zhang, Julius Werner, Lance Zhao, Matt DeVillier, Raul Rangel, Sean Rhodes, Tim Chu, Tim Wawrzynczak, Vanessa Eusebio, Xi Chen, Yidi Lin, Yu-Ping Wu, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/77098?usp=email
to look at the new patch set (#3).
Change subject: treewide: Change I2C/SMBUS master/slave to controller/target
......................................................................
treewide: Change I2C/SMBUS master/slave to controller/target
The I2C and SMBUS specifications have updated their terminology from
master/slave to controller/target. As stated in the coreboot language
style page, using the word 'slave' should be avoided when possible [1]
except when discussing the term as applicable by the current standards.
As the SMBUS and I2C standards are no longer using this terminology,
the updated terms controller/target should be used in the coreboot
I2C/SMBUS code.
We'll keep register names for devices are they are in the datasheets.
[1] https://doc.coreboot.org/community/language_style.html#discussing-words-to-…
Signed-off-by: Martin Roth <gaumless(a)gmail.com>
Change-Id: I6c141fa4322de9e9ed208589f591560fed609825
---
M Documentation/technotes/console.md
M Documentation/tutorial/part3.md
M src/acpi/device.c
M src/commonlib/bsd/include/commonlib/bsd/cb_err.h
M src/console/Kconfig
M src/device/dram/rcd.c
M src/device/i2c_bus.c
M src/device/software_i2c.c
M src/drivers/analogix/anx7625/anx7625.c
M src/drivers/i2c/designware/dw_i2c.c
M src/drivers/i2c/tpm/tpm.c
M src/drivers/i2c/ww_ring/ww_ring.c
M src/drivers/intel/gma/edid.c
M src/drivers/intel/gma/edid.h
M src/drivers/smbus/i2c_smbus_console.c
M src/drivers/smbus/sc16is7xx_init.c
M src/ec/google/chromeec/ec_i2c.c
M src/ec/kontron/kempld/kempld_i2c.c
M src/include/device/i2c.h
M src/include/device/i2c_bus.h
M src/include/device/i2c_simple.h
M src/include/device/smbus_host.h
M src/include/smbios.h
M src/lib/smbios.c
M src/mainboard/asus/p8x7x-series/variants/p8c_ws/overridetree.cb
M src/mainboard/google/auron/variants/auron_paine/include/variant/acpi/mainboard.asl
M src/mainboard/google/auron/variants/auron_yuna/include/variant/acpi/mainboard.asl
M src/mainboard/google/auron/variants/buddy/include/variant/acpi/mainboard.asl
M src/mainboard/google/auron/variants/gandof/include/variant/acpi/mainboard.asl
M src/mainboard/google/auron/variants/lulu/include/variant/acpi/mainboard.asl
M src/mainboard/google/auron/variants/samus/include/variant/acpi/mainboard.asl
M src/mainboard/google/cyan/acpi/touchscreen_elan.asl
M src/mainboard/google/cyan/acpi/touchscreen_melfas.asl
M src/mainboard/google/cyan/acpi/touchscreen_synaptics.asl
M src/mainboard/google/cyan/acpi/trackpad_atmel.asl
M src/mainboard/google/cyan/acpi/trackpad_elan.asl
M src/mainboard/google/daisy/exynos5250.h
M src/mainboard/google/daisy/mainboard.c
M src/mainboard/google/kukui/boardid.c
M src/mainboard/google/octopus/variants/baseboard/devicetree.cb
M src/mainboard/google/rambi/acpi/mainboard.asl
M src/mainboard/google/rambi/acpi/touchscreen_atmel.asl
M src/mainboard/google/rambi/acpi/touchscreen_elan.asl
M src/mainboard/google/rambi/acpi/touchscreen_wdt.asl
M src/mainboard/google/rambi/acpi/trackpad_atmel.asl
M src/mainboard/google/rambi/acpi/trackpad_elan.asl
M src/mainboard/google/slippy/variants/falco/include/variant/acpi/mainboard.asl
M src/mainboard/google/slippy/variants/leon/include/variant/acpi/mainboard.asl
M src/mainboard/google/slippy/variants/peppy/include/variant/acpi/mainboard.asl
M src/mainboard/google/slippy/variants/wolf/include/variant/acpi/mainboard.asl
M src/mainboard/intel/glkrvp/touchpad.asl
M src/mainboard/intel/strago/acpi/mainboard.asl
M src/northbridge/intel/i945/gma.c
M src/soc/amd/stoneyridge/smbus_spd.c
M src/soc/cavium/cn81xx/twsi.c
M src/soc/cavium/common/bdk-coreboot.c
M src/soc/intel/apollolake/chip.h
M src/soc/intel/baytrail/scc.c
M src/soc/intel/common/block/include/intelblocks/imc.h
M src/soc/intel/common/block/smbus/smbus.c
M src/soc/mediatek/common/i2c.c
M src/soc/nvidia/tegra/i2c.c
M src/soc/qualcomm/common/qupv3_i2c.c
M src/soc/qualcomm/ipq40xx/i2c.c
M src/soc/qualcomm/ipq806x/i2c.c
M src/soc/qualcomm/qcs405/i2c.c
M src/soc/rockchip/common/i2c.c
M src/soc/samsung/exynos5250/i2c.c
M src/soc/samsung/exynos5420/i2c.c
M src/southbridge/amd/pi/hudson/smbus_spd.c
M src/southbridge/intel/bd82x6x/smbus.c
M src/southbridge/intel/common/smbus.c
M src/southbridge/intel/ibexpeak/smbus.c
M src/southbridge/intel/lynxpoint/smbus.c
M tests/device/i2c-test.c
M util/intelvbttool/intelvbttool.c
76 files changed, 268 insertions(+), 268 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/77098/3
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80299?usp=email )
Change subject: mb/amd/birman: add Phoenix with openSIL mainboard option
......................................................................
mb/amd/birman: add Phoenix with openSIL mainboard option
Introduce BOARD_AMD_BIRMAN_PHOENIX_OPENSIL which selects the openSIL
based Phoenix SoC code. Since the Phoenix chip.c is different due to
some FSP-specific data structures in there that are guarded in the
openSIL case, a separate devicetree for the openSIL case is added.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: I248102e92818b2d395d561a4bf2627f80906b2f7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80299
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com>
---
M src/mainboard/amd/birman/Kconfig
M src/mainboard/amd/birman/Kconfig.name
R src/mainboard/amd/birman/devicetree_phoenix_fsp.cb
A src/mainboard/amd/birman/devicetree_phoenix_opensil.cb
4 files changed, 155 insertions(+), 2 deletions(-)
Approvals:
Matt DeVillier: Looks good to me, approved
build bot (Jenkins): Verified
diff --git a/src/mainboard/amd/birman/Kconfig b/src/mainboard/amd/birman/Kconfig
index cd7e938..9fafae1 100644
--- a/src/mainboard/amd/birman/Kconfig
+++ b/src/mainboard/amd/birman/Kconfig
@@ -19,6 +19,10 @@
select BOARD_AMD_BIRMAN_COMMON
select SOC_AMD_PHOENIX_FSP
+config BOARD_AMD_BIRMAN_PHOENIX_OPENSIL
+ select BOARD_AMD_BIRMAN_COMMON
+ select SOC_AMD_PHOENIX_OPENSIL
+
config BOARD_AMD_BIRMAN_GLINDA
select BOARD_AMD_BIRMAN_COMMON
select SOC_AMD_GLINDA
@@ -27,7 +31,7 @@
config FMDFILE
default "src/mainboard/amd/birman/chromeos_glinda.fmd" if CHROMEOS && BOARD_AMD_BIRMAN_GLINDA
- default "src/mainboard/amd/birman/chromeos_phoenix.fmd" if CHROMEOS && BOARD_AMD_BIRMAN_PHOENIX_FSP
+ default "src/mainboard/amd/birman/chromeos_phoenix.fmd" if CHROMEOS
default "src/mainboard/amd/birman/board_glinda.fmd" if BOARD_AMD_BIRMAN_GLINDA
default "src/mainboard/amd/birman/board_phoenix.fmd"
@@ -37,10 +41,12 @@
config MAINBOARD_PART_NUMBER
default "Birman_Glinda" if BOARD_AMD_BIRMAN_GLINDA
default "Birman_Phoenix_FSP" if BOARD_AMD_BIRMAN_PHOENIX_FSP
+ default "Birman_Phoenix_openSIL" if BOARD_AMD_BIRMAN_PHOENIX_OPENSIL
config DEVICETREE
default "devicetree_glinda.cb" if BOARD_AMD_BIRMAN_GLINDA
- default "devicetree_phoenix.cb"
+ default "devicetree_phoenix_fsp.cb" if BOARD_AMD_BIRMAN_PHOENIX_FSP
+ default "devicetree_phoenix_opensil.cb" if BOARD_AMD_BIRMAN_PHOENIX_OPENSIL
config BIRMAN_HAVE_MCHP_FW
bool "Have Microchip EC firmware?"
diff --git a/src/mainboard/amd/birman/Kconfig.name b/src/mainboard/amd/birman/Kconfig.name
index 9eee171..6daea88 100644
--- a/src/mainboard/amd/birman/Kconfig.name
+++ b/src/mainboard/amd/birman/Kconfig.name
@@ -3,5 +3,8 @@
config BOARD_AMD_BIRMAN_PHOENIX_FSP
bool "-> Birman for Phoenix SoC using FSP"
+config BOARD_AMD_BIRMAN_PHOENIX_OPENSIL
+ bool "-> Birman for Phoenix SoC using openSIL"
+
config BOARD_AMD_BIRMAN_GLINDA
bool "-> Birman for Glinda SoC"
diff --git a/src/mainboard/amd/birman/devicetree_phoenix.cb b/src/mainboard/amd/birman/devicetree_phoenix_fsp.cb
similarity index 100%
rename from src/mainboard/amd/birman/devicetree_phoenix.cb
rename to src/mainboard/amd/birman/devicetree_phoenix_fsp.cb
diff --git a/src/mainboard/amd/birman/devicetree_phoenix_opensil.cb b/src/mainboard/amd/birman/devicetree_phoenix_opensil.cb
new file mode 100644
index 0000000..58cead5
--- /dev/null
+++ b/src/mainboard/amd/birman/devicetree_phoenix_opensil.cb
@@ -0,0 +1,144 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+# TODO: Update for birman
+
+chip soc/amd/phoenix
+ register "common_config.espi_config" = "{
+ .std_io_decode_bitmap = ESPI_DECODE_IO_0x80_EN | ESPI_DECODE_IO_0X2E_0X2F_EN | ESPI_DECODE_IO_0X60_0X64_EN,
+ .generic_io_range[0] = {
+ .base = 0x3f8,
+ .size = 8,
+ },
+ .generic_io_range[1] = {
+ .base = 0x600,
+ .size = 256,
+ },
+ .io_mode = ESPI_IO_MODE_QUAD,
+ .op_freq_mhz = ESPI_OP_FREQ_16_MHZ,
+ .crc_check_enable = 1,
+ .alert_pin = ESPI_ALERT_PIN_PUSH_PULL,
+ .periph_ch_en = 1,
+ .vw_ch_en = 1,
+ .oob_ch_en = 1,
+ .flash_ch_en = 0,
+ }"
+
+ register "i2c_scl_reset" = "GPIO_I2C0_SCL | GPIO_I2C1_SCL |
+ GPIO_I2C2_SCL | GPIO_I2C3_SCL"
+
+ register "i2c[0].early_init" = "1"
+ register "i2c[1].early_init" = "1"
+ register "i2c[2].early_init" = "1"
+ register "i2c[3].early_init" = "1"
+
+ # I2C Pad Control RX Select Configuration
+ register "i2c_pad[0].rx_level" = "I2C_PAD_RX_1_8V"
+ register "i2c_pad[1].rx_level" = "I2C_PAD_RX_1_8V"
+ register "i2c_pad[2].rx_level" = "I2C_PAD_RX_1_8V"
+ register "i2c_pad[3].rx_level" = "I2C_PAD_RX_1_8V"
+
+ register "s0ix_enable" = "true"
+
+ register "pspp_policy" = "DXIO_PSPP_DISABLED" # TODO: reenable when PSPP works<
+
+ device domain 0 on
+ device ref iommu on end
+ device ref gpp_bridge_1_1 on end # MXM
+ device ref gpp_bridge_1_2 on
+ # Required so the NVMe gets placed into D3 when entering S0i3.
+ chip drivers/pcie/rtd3/device
+ register "name" = ""NVME""
+ device pci 00.0 on end
+ end
+ end # NVMe SSD1
+ device ref gpp_bridge_1_3 on end # GBE
+ device ref gpp_bridge_2_1 on end # SD
+ device ref gpp_bridge_2_2 on end # WWAN
+ device ref gpp_bridge_2_3 on end # WIFI
+ device ref gpp_bridge_2_4 on
+ # Required so the NVMe gets placed into D3 when entering S0i3.
+ chip drivers/pcie/rtd3/device
+ register "name" = ""NVME""
+ device pci 00.0 on end
+ end
+ end # NVMe SSD0
+ device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A
+ device ref gfx on end # Internal GPU (GFX)
+ device ref gfx_hda on end # Display HD Audio Controller (GFXAZ)
+ device ref crypto on end # Crypto Coprocessor
+ device ref xhci_0 on # USB 3.1 (USB0)
+ chip drivers/usb/acpi
+ device ref xhci_0_root_hub on
+ chip drivers/usb/acpi
+ device ref usb3_port2 on end
+ end
+ chip drivers/usb/acpi
+ device ref usb3_port3 on end
+ end
+ chip drivers/usb/acpi
+ device ref usb2_port2 on end
+ end
+ chip drivers/usb/acpi
+ device ref usb2_port3 on end
+ end
+ chip drivers/usb/acpi
+ device ref usb2_port4 on end
+ end
+ chip drivers/usb/acpi
+ device ref usb2_port5 on end
+ end
+ chip drivers/usb/acpi
+ device ref usb2_port6 on end
+ end
+ end
+ end
+ end
+ device ref xhci_1 on # USB 3.1 (USB1)
+ chip drivers/usb/acpi
+ device ref xhci_1_root_hub on
+ chip drivers/usb/acpi
+ device ref usb3_port7 on end
+ end
+ chip drivers/usb/acpi
+ device ref usb2_port7 on end
+ end
+ end
+ end
+ end
+ device ref acp on end # Audio Processor (ACP)
+ end
+ device ref gpp_bridge_c on # Internal GPP Bridge 2 to Bus C
+ device ref usb4_xhci_0 on
+ chip drivers/usb/acpi
+ device ref usb4_xhci_0_root_hub on
+ chip drivers/usb/acpi
+ device ref usb3_port0 on end
+ end
+ chip drivers/usb/acpi
+ device ref usb2_port0 on end
+ end
+ end
+ end
+ end
+ device ref usb4_xhci_1 on
+ chip drivers/usb/acpi
+ device ref usb4_xhci_1_root_hub on
+ chip drivers/usb/acpi
+ device ref usb3_port1 on end
+ end
+ chip drivers/usb/acpi
+ device ref usb2_port1 on end
+ end
+ end
+ end
+ end
+ end
+ end
+
+ device ref i2c_0 on end
+ device ref i2c_1 on end
+ device ref i2c_2 on end
+ device ref i2c_3 on end
+ device ref uart_0 on end # UART0
+
+end
--
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Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: I248102e92818b2d395d561a4bf2627f80906b2f7
Gerrit-Change-Number: 80299
Gerrit-PatchSet: 4
Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com>
Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com>
Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-MessageType: merged
Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80298?usp=email )
(
2 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
)Change subject: soc/amd/phoenix/chip.h: guard FSP-specific data structures
......................................................................
soc/amd/phoenix/chip.h: guard FSP-specific data structures
Since the USB configuration data structure is FSP-specific, add guards
on this part of the soc_amd_phoenix_config struct and the corresponding
include.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: I6c324421fbc3dc7b9a7bf6f5868785e9718147a5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80298
Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M src/soc/amd/phoenix/chip.h
1 file changed, 4 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Matt DeVillier: Looks good to me, approved
diff --git a/src/soc/amd/phoenix/chip.h b/src/soc/amd/phoenix/chip.h
index f436f9f..e3cadc2 100644
--- a/src/soc/amd/phoenix/chip.h
+++ b/src/soc/amd/phoenix/chip.h
@@ -13,7 +13,9 @@
#include <soc/southbridge.h>
#include <drivers/i2c/designware/dw_i2c.h>
#include <types.h>
+#if CONFIG(PLATFORM_USES_FSP2_0)
#include <vendorcode/amd/fsp/phoenix/FspUsb.h>
+#endif
struct soc_amd_phoenix_config {
struct soc_amd_common_config common_config;
@@ -103,8 +105,10 @@
DXIO_PSPP_POWERSAVE,
} pspp_policy;
+#if CONFIG(PLATFORM_USES_FSP2_0)
uint8_t usb_phy_custom;
struct usb_phy_config usb_phy;
+#endif
};
#endif /* PHOENIX_CHIP_H */
--
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Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: I6c324421fbc3dc7b9a7bf6f5868785e9718147a5
Gerrit-Change-Number: 80298
Gerrit-PatchSet: 4
Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com>
Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com>
Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-MessageType: merged
Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80297?usp=email )
(
1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
)Change subject: soc/amd/phoenix/fch: only init ACPI IO ports in FSP case
......................................................................
soc/amd/phoenix/fch: only init ACPI IO ports in FSP case
Since openSIL configures the APCI IO port addresses, coreboot should not
overwrite them.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: If10e5a9f52ab313ad1afebd7f9e722994d48b0a7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80297
Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M src/soc/amd/phoenix/fch.c
1 file changed, 6 insertions(+), 4 deletions(-)
Approvals:
Matt DeVillier: Looks good to me, approved
build bot (Jenkins): Verified
diff --git a/src/soc/amd/phoenix/fch.c b/src/soc/amd/phoenix/fch.c
index e9bc80a..1e03cda 100644
--- a/src/soc/amd/phoenix/fch.c
+++ b/src/soc/amd/phoenix/fch.c
@@ -89,10 +89,12 @@
* ACPI tables are generated. Enable these ports indiscriminately.
*/
- pm_write16(PM_EVT_BLK, ACPI_PM_EVT_BLK);
- pm_write16(PM1_CNT_BLK, ACPI_PM1_CNT_BLK);
- pm_write16(PM_TMR_BLK, ACPI_PM_TMR_BLK);
- pm_write16(PM_GPE0_BLK, ACPI_GPE0_BLK);
+ if (CONFIG(PLATFORM_USES_FSP2_0)) {
+ pm_write16(PM_EVT_BLK, ACPI_PM_EVT_BLK);
+ pm_write16(PM1_CNT_BLK, ACPI_PM1_CNT_BLK);
+ pm_write16(PM_TMR_BLK, ACPI_PM_TMR_BLK);
+ pm_write16(PM_GPE0_BLK, ACPI_GPE0_BLK);
+ }
if (CONFIG(HAVE_SMI_HANDLER)) {
/* APMC - SMI Command Port */
--
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Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: If10e5a9f52ab313ad1afebd7f9e722994d48b0a7
Gerrit-Change-Number: 80297
Gerrit-PatchSet: 3
Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com>
Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com>
Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-MessageType: merged