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Change subject: cpu/x86/smm: Set up page tables in safe SMRAM
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Patch Set 2: Code-Review+2
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Change subject: cpu/x86/(sipi|smm): Pass on CR3 from ramstage
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Patch Set 2: Code-Review+2
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Change subject: cpu/x86/64bit: Turn jumping to long mode into a macro
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Patch Set 3:
(1 comment)
Patchset:
PS3:
`src/cpu/intel/car/core2/cache_as_ram.S` is missing
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Change subject: drivers/intel/fsp2_0: Add FSP_DOES_NOT_NEED_TEMP_RAM
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Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/80328/comment/eda8b30a_c2dceda0 :
PS3, Line 8:
> Yeah, it is for the 2S issue. https://review.coreboot. […]
Wouldn't it be easier to select `PLATFORM_USES_FSP2_0` instead of `PLATFORM_USES_FSP2_2`?
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Change subject: device/azalia: Rework the verb table
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Patch Set 5:
(1 comment)
Patchset:
PS5:
Did some quick tests on compiler explorer and it seems like using pointers can cut down the instructions roughly 35%.
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Change subject: mb/google/rex/var/karis: Follow rex0 CNVi/PCIe switching
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Patch Set 5: Code-Review+2
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Change subject: mb/google/brox: Initialize TCHSCR_RST_L/EN_PP3300_TCHSCR to 0
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Patch Set 2:
(1 comment)
This change is ready for review.
File src/mainboard/google/brox/variants/baseboard/brox/gpio.c:
https://review.coreboot.org/c/coreboot/+/80300/comment/e603478c_94cd5f8d :
PS1, Line 265: PAD_CFG_GPO(GPP_F17, 0, DEEP),
> If we have declared "generic.detect" = "1" in devicetree. […]
Thank you very much for your help Ivy! This was exactly the information that we were looking for.
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Change subject: brox: Handle GPI_INT pin value lower to GPI_WAKE
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Patch Set 1:
(1 comment)
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PS1:
Oh also, is this a restriction that we need to adhere to for future devices (INT pin needs to be higher IRQ# than WAKE pin)?
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