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Change subject: device/azalia: Rework the verb table
......................................................................
Patch Set 5:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/80333/comment/0cab2022_5605ce6d :
PS5, Line 9: This is a very experimental change and I would appreciate anyone's
: opinion on this. :)
:
I recommend to bring this up on the mailing list and reference your change-set here.
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Change subject: device/azalia: Cleanup codec initialization code
......................................................................
Patch Set 4:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/80332/comment/54e8c212_18d575ba :
PS4, Line 7: Cleanup
The verb is spelled with a space: Clean up
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Hello Christian Walter, Felix Held, Jonathan Zhang, Krystian Hebel, Martin L Roth, Martin Roth, Michał Żygowski, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: drivers/ipmi: add Block Transfer (BT) interface
......................................................................
drivers/ipmi: add Block Transfer (BT) interface
Unlike already implemented Keyboard Controller Style (KCS) interface
Block Transfer interface is not byte-oriented and implies that device is
capable of buffering command before processing it. Another difference
is that polling can be replaced with interrupts, though not used by this
implementation.
Change-Id: Idb67972d1c38bbae04c7b4de3405350c229a05b9
Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com>
---
M Documentation/drivers/index.md
A Documentation/drivers/ipmi_bt.md
M src/drivers/ipmi/Kconfig
M src/drivers/ipmi/Makefile.mk
A src/drivers/ipmi/ipmi_bt.c
A src/drivers/ipmi/ipmi_bt.h
A src/drivers/ipmi/ipmi_bt_ops.c
M src/drivers/ipmi/ipmi_ops_premem.c
8 files changed, 404 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/67057/23
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Change subject: ppc64: Kconfig switch for bootblock in SEEPROM, zero HRMOR
......................................................................
ppc64: Kconfig switch for bootblock in SEEPROM, zero HRMOR
On PPC64 each address is logically OR'ed with HRMOR (Hypervisor Real
Mode Offset Register) before it is dispatched to the underlying memory,
meaning that memory space overlaps at the least significant bit set in
HRMOR. coreboot is entered with HRMOR = 4GB-128MB both on hardware
(when started by hostboot bootloader) and in Qemu in hb-mode. This means
that memory overlaps every 128MB in this particular case. HRMOR can be
explicitly ignored when MSB of an address is set, but this would require
using different memory model for linking.
If we zero HRMOR in bootblock, linking can be done against real address.
This greatly simplifies memory layout and allows to forget about HRMOR
from that point on.
Signed-off-by: Krystian Hebel <krystian.hebel(a)3mdeb.com>
Signed-off-by: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com>
Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com>
Change-Id: I0170463968c91b943c4b0dc15fe73fa616a164da
---
M src/arch/ppc64/Makefile.mk
M src/arch/ppc64/bootblock_crt0.S
M src/mainboard/emulation/qemu-power8/memlayout.ld
M src/mainboard/emulation/qemu-power9/memlayout.ld
M src/mainboard/raptor-cs/talos-2/Kconfig
A src/mainboard/raptor-cs/talos-2/board-bootblock-in-seeprom.fmd
A src/mainboard/raptor-cs/talos-2/board.fmd
M src/mainboard/raptor-cs/talos-2/memlayout.ld
M src/soc/ibm/power9/Makefile.inc
9 files changed, 344 insertions(+), 57 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/67067/28
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Change subject: 3rdparty/open-power-signing-utils: add SecureBoot utility for OpenPOWER
......................................................................
3rdparty/open-power-signing-utils: add SecureBoot utility for OpenPOWER
Signing is performed with test keys by default, set
CONFIG_SIGNING_KEYS_DIR to non-empty value to use other keys.
Change-Id: Id88baef5ecb1f8ffd74a7f464bbbaaaea0ca643d
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---
M .gitmodules
A 3rdparty/open-power-signing-utils
M Makefile.mk
M src/soc/ibm/power9/Kconfig
M src/soc/ibm/power9/Makefile.inc
5 files changed, 55 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/67065/27
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Change subject: Makefile.inc: compile ECC tools and inject ECC to final image
......................................................................
Makefile.inc: compile ECC tools and inject ECC to final image
Change-Id: I8541aa6f1429ed6143830ed11c47c150183ddf0d
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---
M Makefile.mk
M src/soc/ibm/power9/Makefile.inc
2 files changed, 14 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/67064/26
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Change subject: security/tpm: support compiling in multiple TPM drivers
......................................................................
security/tpm: support compiling in multiple TPM drivers
Starting from here CONFIG_TPM1 and CONFIG_TPM2 are no longer mutually
exclusive.
Making probe functions static and always using them uncovered that
bootblock stage included TPM driver which it didn't use. This is why
Makefile.inc files were updated to replace `all-*` with romstage,
ramstage and verstage.
Change-Id: I44c5a1d825afe414c2f5c2c90f4cfe41ba9bef5f
Ticket: https://ticket.coreboot.org/issues/433
Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com>
---
M src/drivers/crb/Makefile.mk
M src/drivers/crb/tis.c
M src/drivers/i2c/tpm/Makefile.mk
M src/drivers/i2c/tpm/tis.c
M src/drivers/i2c/tpm/tis_atmel.c
M src/drivers/pc80/tpm/Makefile.mk
M src/drivers/pc80/tpm/tis.c
M src/drivers/spi/tpm/Makefile.mk
M src/drivers/spi/tpm/tis.c
M src/lib/program.ld
M src/security/tpm/Kconfig
M src/security/tpm/tis.h
M src/security/tpm/tss/tss.c
M src/soc/amd/common/block/cpu/noncar/memlayout_psp_verstage.ld
14 files changed, 81 insertions(+), 34 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/69162/30
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Hello Christian Walter, Erik van den Bogaert, Felix Held, Frans Hendriks, Fred Reitberger, Jason Glenesk, Julius Werner, Krystian Hebel, Matt DeVillier, Michał Żygowski, Raul Rangel, Yu-Ping Wu, build bot (Jenkins),
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Change subject: security/tpm: resolve conflicts in TSS implementations
......................................................................
security/tpm: resolve conflicts in TSS implementations
No functional changes. Refactor code such that there won't be any
compiler or linker errors if TSS 1.2 and TSS 2.0 were both compiled
in. One might want to support both TPM families for example if TPM
is pluggable, in which case currently one has to update firmware along
with switching TPM device.
Change-Id: Ia0ea5a917c46ada9fc3274f17240e12bca98db6a
Ticket: https://ticket.coreboot.org/issues/433
Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com>
---
M src/drivers/crb/tis.c
M src/security/tpm/Makefile.mk
M src/security/tpm/tspi/tspi.c
M src/security/tpm/tss.h
M src/security/tpm/tss/tcg-1.2/tss.c
M src/security/tpm/tss/tcg-2.0/tss.c
M src/security/tpm/tss/tcg-2.0/tss_marshaling.c
A src/security/tpm/tss/tss.c
M src/security/tpm/tss/vendor/cr50/cr50.c
A src/security/tpm/tss1.h
A src/security/tpm/tss2.h
M src/security/vboot/secdata_tpm.c
M src/soc/amd/common/psp_verstage/psp_verstage.c
M src/vendorcode/eltan/security/mboot/mboot.c
M src/vendorcode/google/chromeos/tpm2.c
15 files changed, 408 insertions(+), 295 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/69160/29
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Change subject: cpu/x86/Kconfig: Mark 64bit support as stable
......................................................................
Patch Set 1:
(1 comment)
File src/arch/x86/Kconfig:
https://review.coreboot.org/c/coreboot/+/80338/comment/78a67dd7_5cfd32ad :
PS1, Line 76: EXP
> nit: If it's no longer experimental, should it still say "EXP" here?
I'd recommend to drop `EXP` when we start using `ARCH_ALL_STAGES_X86_64` over `ARCH_ALL_STAGES_X86_32` as default. But this would require more testing, especially non-generic code, legacy code like oprom handling and silicon blob interactions.
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Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80337?usp=email )
Change subject: cpu/x86: Link page tables in stage if possible
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Patch Set 1:
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https://review.coreboot.org/c/coreboot/+/80337/comment/4dc73f13_a6583b01 :
PS1, Line 9: When switching back and forward from 32 to 64, for example to call a
I don't understand this. Where's the relation between protected mode calls and linking page tables into the stage?
Doesn't this increase the stage size and thus occupies more flash in the end? That should be mentioned here as well.
What's the benefit of linking instead over having it in CBFS?
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