coreboot-gerrit February 2024

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[S] Change in coreboot[main]: lib: Declare heap in assembly
by Arthur Heymans (Code Review) 28 Feb '24

28 Feb '24

Attention is currently required from: Arthur Heymans, Julius Werner, Maximilian Brune, Nico Huber. Hello Julius Werner, Lean Sheng Tan, Maximilian Brune, Nico Huber, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/80776?usp=email to look at the new patch set (#3). Change subject: lib: Declare heap in assembly ...................................................................... lib: Declare heap in assembly Some linkers like LLD don't set up the NOBITS flag on the .heap section when just declaring that region in the linker script. This would have the program loader initialize the heap, which is not desirable for performance reasons. Also if the cbfs file would not be compressed it would be huge as the default heap is 1M. This fixes commit 99bf23c9e73c, which broke setups with a relocatable ramstage as the heap size was not accounted for when allocating memory in cbmem. The alloc code could trash higher cbmem entries in that case. Change-Id: I67cb5ce886fda313e0720b0bc7c6e66e4aae45fa Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/lib/Makefile.mk A src/lib/heap.S M src/lib/program.ld 3 files changed, 20 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/80776/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/80776?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I67cb5ce886fda313e0720b0bc7c6e66e4aae45fa Gerrit-Change-Number: 80776 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[main]: mb/emulation/qemu-riscv: Change to -bios option
by Maximilian Brune (Code Review) 28 Feb '24

28 Feb '24

Attention is currently required from: Arthur Heymans, Philipp Hug, ron minnich. Hello Arthur Heymans, Philipp Hug, build bot (Jenkins), ron minnich, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/80746?usp=email to look at the new patch set (#5). Change subject: mb/emulation/qemu-riscv: Change to -bios option ...................................................................... mb/emulation/qemu-riscv: Change to -bios option This changes the virt target so that it can be run with the -bios option and a pflash backend for the flash. QEMU can now be run as follows: qemu -M virt -m 1G -nographic -bios build/coreboot.rom \ -drive if=pflash,file=./build/coreboot.rom,format=raw coreboot will start in DRAM, but still have a flash to put CBFS onto and to load subsequent stages and payload from. Probing ram size on riscv is currently not working therefore the RAM size stays fixed for now. Tested bootflow: coreboot -> OpenSBI -> Linux -> u-root Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> Change-Id: I009d97fa3e13068b91c604e987e50a65e525407d --- M Documentation/mainboard/emulation/qemu-riscv.md M src/mainboard/emulation/Kconfig M src/mainboard/emulation/qemu-riscv/Kconfig M src/mainboard/emulation/qemu-riscv/Makefile.mk A src/mainboard/emulation/qemu-riscv/cbmem.c A src/mainboard/emulation/qemu-riscv/chip.c M src/mainboard/emulation/qemu-riscv/devicetree.cb M src/mainboard/emulation/qemu-riscv/include/mainboard/addressmap.h M src/mainboard/emulation/qemu-riscv/mainboard.c M src/mainboard/emulation/qemu-riscv/memlayout.ld M src/mainboard/emulation/qemu-riscv/rom_media.c M src/mainboard/emulation/qemu-riscv/romstage.c 12 files changed, 118 insertions(+), 56 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/80746/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/80746?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I009d97fa3e13068b91c604e987e50a65e525407d Gerrit-Change-Number: 80746 Gerrit-PatchSet: 5 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[main]: soc/intel/xeon_sp/util: Locate PCU by PCI device ID
by Lean Sheng Tan (Code Review) 28 Feb '24

28 Feb '24

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80095?usp=email ) ( 12 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/intel/xeon_sp/util: Locate PCU by PCI device ID ...................................................................... soc/intel/xeon_sp/util: Locate PCU by PCI device ID Instead of manually crafting S:B:D:F numbers for each PCI device search for the devices by PCI vendor and device ID. This adds PCI multi-segment support without any further code modifications, since the correct PCI segment will be stored in the devicetree. Change-Id: I1dcad4ba3fbc0295d74e1bf832cce95f014fd7bf Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80095 Reviewed-by: Shuo Liu <shuo.liu(a)intel.com> Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/xeon_sp/util.c 1 file changed, 45 insertions(+), 42 deletions(-) Approvals: build bot (Jenkins): Verified Shuo Liu: Looks good to me, but someone else must approve Lean Sheng Tan: Looks good to me, approved diff --git a/src/soc/intel/xeon_sp/util.c b/src/soc/intel/xeon_sp/util.c index 8658e01..7fc903a 100644 --- a/src/soc/intel/xeon_sp/util.c +++ b/src/soc/intel/xeon_sp/util.c @@ -6,9 +6,11 @@ #include <delay.h> #include <device/device.h> #include <device/pci.h> +#include <device/pci_ids.h> #include <intelblocks/cfg.h> #include <intelblocks/cpulib.h> #include <intelpch/lockdown.h> +#include <soc/chip_common.h> #include <soc/pci_devs.h> #include <soc/msr.h> #include <soc/soc_util.h> @@ -120,19 +122,20 @@ #if ENV_RAMSTAGE /* Setting devtree variables is only allowed in ramstage. */ /* return true if command timed out else false */ -static bool wait_for_bios_cmd_cpl(pci_devfn_t dev, uint32_t reg, uint32_t mask, - uint32_t target) +static bool wait_for_bios_cmd_cpl(struct device *pcu1, uint32_t reg, uint32_t mask, + uint32_t target) { const uint32_t max_delay = 5000; /* 5 seconds max */ const uint32_t step_delay = 50; /* 50 us */ struct stopwatch sw; stopwatch_init_msecs_expire(&sw, max_delay); - while ((pci_s_read_config32(dev, reg) & mask) != target) { + while ((pci_read_config32(pcu1, reg) & mask) != target) { udelay(step_delay); if (stopwatch_expired(&sw)) { - printk(BIOS_ERR, "%s timed out for dev: %x, reg: 0x%x, " - "mask: 0x%x, target: 0x%x\n", __func__, dev, reg, mask, target); + printk(BIOS_ERR, "%s timed out for dev: %s, reg: 0x%x, " + "mask: 0x%x, target: 0x%x\n", + __func__, dev_path(pcu1), reg, mask, target); return true; /* timedout */ } } @@ -140,94 +143,94 @@ } /* return true if command timed out else false */ -static bool write_bios_mailbox_cmd(pci_devfn_t dev, uint32_t command, uint32_t data) +static bool write_bios_mailbox_cmd(struct device *pcu1, uint32_t command, uint32_t data) { /* verify bios is not in busy state */ - if (wait_for_bios_cmd_cpl(dev, PCU_CR1_BIOS_MB_INTERFACE_REG, BIOS_MB_RUN_BUSY_MASK, 0)) + if (wait_for_bios_cmd_cpl(pcu1, PCU_CR1_BIOS_MB_INTERFACE_REG, BIOS_MB_RUN_BUSY_MASK, 0)) return true; /* timed out */ /* write data to data register */ - printk(BIOS_SPEW, "%s - pci_s_write_config32 reg: 0x%x, data: 0x%x\n", __func__, - PCU_CR1_BIOS_MB_DATA_REG, data); - pci_s_write_config32(dev, PCU_CR1_BIOS_MB_DATA_REG, data); + printk(BIOS_SPEW, "%s - pci_write_config32 reg: 0x%x, data: 0x%x\n", __func__, + PCU_CR1_BIOS_MB_DATA_REG, data); + + pci_write_config32(pcu1, PCU_CR1_BIOS_MB_DATA_REG, data); /* write the command */ - printk(BIOS_SPEW, "%s - pci_s_write_config32 reg: 0x%x, data: 0x%lx\n", __func__, - PCU_CR1_BIOS_MB_INTERFACE_REG, command | BIOS_MB_RUN_BUSY_MASK); - pci_s_write_config32(dev, PCU_CR1_BIOS_MB_INTERFACE_REG, - command | BIOS_MB_RUN_BUSY_MASK); + printk(BIOS_SPEW, "%s - pci_write_config32 reg: 0x%x, data: 0x%lx\n", __func__, + PCU_CR1_BIOS_MB_INTERFACE_REG, command | BIOS_MB_RUN_BUSY_MASK); + + pci_write_config32(pcu1, PCU_CR1_BIOS_MB_INTERFACE_REG, + command | BIOS_MB_RUN_BUSY_MASK); /* wait for completion or time out*/ - return wait_for_bios_cmd_cpl(dev, PCU_CR1_BIOS_MB_INTERFACE_REG, - BIOS_MB_RUN_BUSY_MASK, 0); + return wait_for_bios_cmd_cpl(pcu1, PCU_CR1_BIOS_MB_INTERFACE_REG, + BIOS_MB_RUN_BUSY_MASK, 0); } /* return true if command timed out else false */ -static bool set_bios_reset_cpl_for_package(uint32_t socket, uint32_t rst_cpl_mask, - uint32_t pcode_init_mask, uint32_t val) +static bool set_bios_reset_cpl_for_package(struct device *pcu1, + uint32_t rst_cpl_mask, + uint32_t pcode_init_mask, + uint32_t val) { - const uint32_t bus = get_socket_ubox_busno(socket); - const pci_devfn_t dev = PCI_DEV(bus, PCU_DEV, PCU_CR1_FUN); - - uint32_t reg = pci_s_read_config32(dev, PCU_CR1_BIOS_RESET_CPL_REG); - reg &= (uint32_t)~rst_cpl_mask; - reg |= val; - /* update BIOS RESET completion bit */ - pci_s_write_config32(dev, PCU_CR1_BIOS_RESET_CPL_REG, reg); + pci_update_config32(pcu1, PCU_CR1_BIOS_RESET_CPL_REG, ~rst_cpl_mask, val); /* wait for PCU ack */ - return wait_for_bios_cmd_cpl(dev, PCU_CR1_BIOS_RESET_CPL_REG, pcode_init_mask, - pcode_init_mask); + return wait_for_bios_cmd_cpl(pcu1, PCU_CR1_BIOS_RESET_CPL_REG, + pcode_init_mask, pcode_init_mask); } static void set_bios_init_completion_for_package(uint32_t socket) { + struct device *pcu0 = dev_find_device_on_socket(socket, PCI_VID_INTEL, PCU_CR0_DEVID); + struct device *pcu1 = dev_find_device_on_socket(socket, PCI_VID_INTEL, PCU_CR1_DEVID); uint32_t data; bool timedout; - const uint32_t bus = get_socket_ubox_busno(socket); - const pci_devfn_t dev = PCI_DEV(bus, PCU_DEV, PCU_CR1_FUN); + + if (!pcu0 || !pcu1) + die("Failed to locate PCU PCI device\n"); /* read PCU config */ - timedout = write_bios_mailbox_cmd(dev, BIOS_CMD_READ_PCU_MISC_CFG, 0); + timedout = write_bios_mailbox_cmd(pcu1, BIOS_CMD_READ_PCU_MISC_CFG, 0); if (timedout) { /* 2nd try */ - timedout = write_bios_mailbox_cmd(dev, BIOS_CMD_READ_PCU_MISC_CFG, 0); + timedout = write_bios_mailbox_cmd(pcu1, BIOS_CMD_READ_PCU_MISC_CFG, 0); if (timedout) die("BIOS PCU Misc Config Read timed out.\n"); /* Since the 1st try failed, we need to make sure PCU is in stable state */ - data = pci_s_read_config32(dev, PCU_CR1_BIOS_MB_DATA_REG); - printk(BIOS_SPEW, "%s - pci_s_read_config32 reg: 0x%x, data: 0x%x\n", + data = pci_read_config32(pcu1, PCU_CR1_BIOS_MB_DATA_REG); + printk(BIOS_SPEW, "%s - pci_read_config32 reg: 0x%x, data: 0x%x\n", __func__, PCU_CR1_BIOS_MB_DATA_REG, data); - timedout = write_bios_mailbox_cmd(dev, BIOS_CMD_WRITE_PCU_MISC_CFG, data); + timedout = write_bios_mailbox_cmd(pcu1, BIOS_CMD_WRITE_PCU_MISC_CFG, data); if (timedout) die("BIOS PCU Misc Config Write timed out.\n"); } /* update RST_CPL3, PCODE_INIT_DONE3 */ - timedout = set_bios_reset_cpl_for_package(socket, RST_CPL3_MASK, + timedout = set_bios_reset_cpl_for_package(pcu1, RST_CPL3_MASK, PCODE_INIT_DONE3_MASK, RST_CPL3_MASK); if (timedout) die("BIOS RESET CPL3 timed out.\n"); /* Set PMAX_LOCK - must be set before RESET CPL4 */ - data = pci_s_read_config32(PCI_DEV(bus, PCU_DEV, PCU_CR0_FUN), PCU_CR0_PMAX); + data = pci_read_config32(pcu0, PCU_CR0_PMAX); data |= PMAX_LOCK; - pci_s_write_config32(PCI_DEV(bus, PCU_DEV, PCU_CR0_FUN), PCU_CR0_PMAX, data); + pci_write_config32(pcu0, PCU_CR0_PMAX, data); /* update RST_CPL4, PCODE_INIT_DONE4 */ - timedout = set_bios_reset_cpl_for_package(socket, RST_CPL4_MASK, + timedout = set_bios_reset_cpl_for_package(pcu1, RST_CPL4_MASK, PCODE_INIT_DONE4_MASK, RST_CPL4_MASK); if (timedout) die("BIOS RESET CPL4 timed out.\n"); /* set CSR_DESIRED_CORES_CFG2 lock bit */ - data = pci_s_read_config32(dev, PCU_CR1_DESIRED_CORES_CFG2_REG); + data = pci_read_config32(pcu1, PCU_CR1_DESIRED_CORES_CFG2_REG); data |= PCU_CR1_DESIRED_CORES_CFG2_REG_LOCK_MASK; - printk(BIOS_SPEW, "%s - pci_s_write_config32 PCU_CR1_DESIRED_CORES_CFG2_REG 0x%x, data: 0x%x\n", + printk(BIOS_SPEW, "%s - pci_write_config32 PCU_CR1_DESIRED_CORES_CFG2_REG 0x%x, data: 0x%x\n", __func__, PCU_CR1_DESIRED_CORES_CFG2_REG, data); - pci_s_write_config32(dev, PCU_CR1_DESIRED_CORES_CFG2_REG, data); + pci_write_config32(pcu1, PCU_CR1_DESIRED_CORES_CFG2_REG, data); } void set_bios_init_completion(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/80095?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1dcad4ba3fbc0295d74e1bf832cce95f014fd7bf Gerrit-Change-Number: 80095 Gerrit-PatchSet: 14 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[main]: soc/intel/xeon_sp: Locate PCU by PCI device ID
by Felix Held (Code Review) 28 Feb '24

28 Feb '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80093?usp=email ) Change subject: soc/intel/xeon_sp: Locate PCU by PCI device ID ...................................................................... soc/intel/xeon_sp: Locate PCU by PCI device ID Instead of manually crafting S:B:D:F numbers for each PCI device search for the devices by PCI vendor and device ID. This adds PCI multi-segment support without any further code modifications, since the correct PCI segment will be stored in the devicetree. Intel Document-ID: 735086 Intel Document-ID: 612246 Tested: On SPR 4S all PCU on all 4 sockets could be found and locked. Change-Id: I06694715cba76b101165f1cef66d161b0f896b26 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80093 Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/xeon_sp/cpx/chip.c M src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h M src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h M src/soc/intel/xeon_sp/skx/soc_util.c M src/soc/intel/xeon_sp/spr/chip.c M src/soc/intel/xeon_sp/spr/include/soc/pci_devs.h 6 files changed, 107 insertions(+), 90 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, but someone else must approve Lean Sheng Tan: Looks good to me, approved diff --git a/src/soc/intel/xeon_sp/cpx/chip.c b/src/soc/intel/xeon_sp/cpx/chip.c index 1e84dd5..6274f02 100644 --- a/src/soc/intel/xeon_sp/cpx/chip.c +++ b/src/soc/intel/xeon_sp/cpx/chip.c @@ -6,6 +6,7 @@ #include <cpu/x86/mp.h> #include <device/pci.h> #include <device/pci_ids.h> +#include <device/pci_def.h> #include <gpio.h> #include <intelblocks/acpi.h> #include <intelblocks/lpc_lib.h> @@ -115,33 +116,38 @@ static void set_pcu_locks(void) { - for (uint32_t socket = 0; socket < CONFIG_MAX_SOCKET; ++socket) { - if (!soc_cpu_is_enabled(socket)) - continue; - uint32_t bus = get_socket_stack_busno(socket, PCU_IIO_STACK); + struct device *dev = NULL; - /* configure PCU_CR0_FUN csrs */ - const struct device *cr0_dev = PCU_DEV_CR0(bus); - pci_or_config32(cr0_dev, PCU_CR0_P_STATE_LIMITS, P_STATE_LIMITS_LOCK); - pci_or_config32(cr0_dev, PCU_CR0_PACKAGE_RAPL_LIMIT_UPR, PKG_PWR_LIM_LOCK_UPR); - pci_or_config32(cr0_dev, PCU_CR0_TURBO_ACTIVATION_RATIO, TURBO_ACTIVATION_RATIO_LOCK); - - - /* configure PCU_CR1_FUN csrs */ - const struct device *cr1_dev = PCU_DEV_CR1(bus); - pci_or_config32(cr1_dev, PCU_CR1_SAPMCTL, SAPMCTL_LOCK_MASK); - - /* configure PCU_CR2_FUN csrs */ - const struct device *cr2_dev = PCU_DEV_CR2(bus); - pci_or_config32(cr2_dev, PCU_CR2_DRAM_PLANE_POWER_LIMIT, PP_PWR_LIM_LOCK); - pci_or_config32(cr2_dev, PCU_CR2_DRAM_POWER_INFO_UPR, DRAM_POWER_INFO_LOCK_UPR); - - /* configure PCU_CR3_FUN csrs */ - const struct device *cr3_dev = PCU_DEV_CR3(bus); - pci_or_config32(cr3_dev, PCU_CR3_CONFIG_TDP_CONTROL, TDP_LOCK); - pci_or_config32(cr3_dev, PCU_CR3_FLEX_RATIO, OC_LOCK); + while ((dev = dev_find_device(PCI_VID_INTEL, PCU_CR0_DEVID, dev))) { + printk(BIOS_SPEW, "%s: locking registers\n", dev_path(dev)); + pci_or_config32(dev, PCU_CR0_P_STATE_LIMITS, P_STATE_LIMITS_LOCK); + pci_or_config32(dev, PCU_CR0_PACKAGE_RAPL_LIMIT_UPR, + PKG_PWR_LIM_LOCK_UPR); + pci_or_config32(dev, PCU_CR0_TURBO_ACTIVATION_RATIO, + TURBO_ACTIVATION_RATIO_LOCK); } + dev = NULL; + while ((dev = dev_find_device(PCI_VID_INTEL, PCU_CR1_DEVID, dev))) { + printk(BIOS_SPEW, "%s: locking registers\n", dev_path(dev)); + pci_or_config32(dev, PCU_CR1_SAPMCTL, SAPMCTL_LOCK_MASK); + } + + dev = NULL; + while ((dev = dev_find_device(PCI_VID_INTEL, PCU_CR2_DEVID, dev))) { + printk(BIOS_SPEW, "%s: locking registers\n", dev_path(dev)); + pci_or_config32(dev, PCU_CR2_DRAM_PLANE_POWER_LIMIT, + PP_PWR_LIM_LOCK); + pci_or_config32(dev, PCU_CR2_DRAM_POWER_INFO_UPR, + DRAM_POWER_INFO_LOCK_UPR); + } + + dev = NULL; + while ((dev = dev_find_device(PCI_VID_INTEL, PCU_CR3_DEVID, dev))) { + printk(BIOS_SPEW, "%s: locking registers\n", dev_path(dev)); + pci_or_config32(dev, PCU_CR3_CONFIG_TDP_CONTROL, TDP_LOCK); + pci_or_config32(dev, PCU_CR3_FLEX_RATIO, OC_LOCK); + } } static void set_imc_locks(void) diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h index 587c97c..614f42a 100644 --- a/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h +++ b/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h @@ -24,6 +24,7 @@ #define PCU_DEV 30 #define PCU_CR0_FUN 0 +#define PCU_CR0_DEVID 0x344a #define PCU_DEV_CR0(bus) _PCU_DEV(bus, PCU_CR0_FUN) #define PCU_CR0_PLATFORM_INFO 0xa8 #define PCU_CR0_TURBO_ACTIVATION_RATIO 0xb0 @@ -37,6 +38,7 @@ #define PMAX_LOCK BIT(31) #define PCU_CR1_FUN 1 +#define PCU_CR1_DEVID 0x344b #define PCU_DEV_CR1(bus) _PCU_DEV(bus, PCU_CR1_FUN) #define PCU_CR1_BIOS_MB_DATA_REG 0x8c @@ -64,6 +66,7 @@ #define SAPMCTL_LOCK_MASK BIT(31) #define PCU_CR2_FUN 2 +#define PCU_CR2_DEVID 0x344c #define PCU_DEV_CR2(bus) _PCU_DEV(bus, PCU_CR2_FUN) #define PCU_CR2_DRAM_POWER_INFO_LWR 0xa8 #define PCU_CR2_DRAM_POWER_INFO_UPR (PCU_CR2_DRAM_POWER_INFO_LWR + 4) @@ -72,6 +75,7 @@ #define PP_PWR_LIM_LOCK BIT(31) #define PCU_CR3_FUN 3 +#define PCU_CR3_DEVID 0x344d #define PCU_DEV_CR3(bus) _PCU_DEV(bus, PCU_CR3_FUN) #define PCU_CR3_CONFIG_TDP_CONTROL 0x60 #define TDP_LOCK BIT(31) diff --git a/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h index d317d0c..8b3c36c 100644 --- a/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h +++ b/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h @@ -9,17 +9,15 @@ #include <hob_iiouds.h> #include <soc/pch_pci_devs.h> -#define dump_csr(fmt, dev, reg) \ - printk(BIOS_SPEW, "%s%x:%x:%x reg: %s (0x%x), data: 0x%x\n", \ - fmt, ((uint32_t)dev >> 20) & 0xfff, ((uint32_t)dev >> 15) & 0x1f, \ - ((uint32_t)dev >> 12) & 0x07, \ - #reg, reg, pci_s_read_config32(dev, reg)) +#define dump_csr(dev, reg) \ + printk(BIOS_SPEW, "%s reg: %s (0x%x), data: 0x%x\n", \ + dev_path(dev), \ + #reg, reg, pci_read_config32(dev, reg)) -#define dump_csr64(fmt, dev, reg) \ - printk(BIOS_SPEW, "%s%x:%x:%x reg: %s (0x%x), data: 0x%x%x\n", \ - fmt, ((uint32_t)dev >> 20) & 0xfff, ((uint32_t)dev >> 15) & 0x1f, \ - ((uint32_t)dev >> 12) & 0x07, #reg, reg, \ - pci_s_read_config32(dev, reg+4), pci_s_read_config32(dev, reg)) +#define dump_csr64(dev, reg) \ + printk(BIOS_SPEW, "%s reg: %s (0x%x), data: 0x%x%x\n", \ + dev_path(dev), #reg, reg, \ + pci_read_config32(dev, reg+4), pci_read_config32(dev, reg)) #define SAD_ALL_DEV 29 #define SAD_ALL_FUNC 0 @@ -36,8 +34,10 @@ #define PCU_IIO_STACK 1 #define PCU_DEV 30 #define PCU_CR1_FUN 1 +#define PCU_CR1_DEVID 0x2081 #define PCU_CR0_FUN 0 +#define PCU_CR0_DEVID 0x2080 #define PCU_DEV_CR0(bus) _PCU_DEV(bus, PCU_CR0_FUN) #define PCU_CR0_PLATFORM_INFO 0xa8 #define PCU_CR0_P_STATE_LIMITS 0xd8 @@ -73,6 +73,8 @@ #define PCU_CR1_DESIRED_CORES_CFG2_REG 0xa0 #define PCU_CR1_DESIRED_CORES_CFG2_REG_LOCK_MASK BIT(31) +#define PCU_CR2_DEVID 0x2082 + #if !defined(__SIMPLE_DEVICE__) #define _UBOX_DEV(func) pcidev_path_on_root_debug(PCI_DEVFN(UBOX_DEV, func), __func__) #else diff --git a/src/soc/intel/xeon_sp/skx/soc_util.c b/src/soc/intel/xeon_sp/skx/soc_util.c index 3e02999..4201d10 100644 --- a/src/soc/intel/xeon_sp/skx/soc_util.c +++ b/src/soc/intel/xeon_sp/skx/soc_util.c @@ -3,6 +3,8 @@ #include <assert.h> #include <console/console.h> #include <device/pci.h> +#include <device/pci_def.h> +#include <device/pci_ids.h> #include <hob_iiouds.h> #include <intelblocks/cpulib.h> #include <intelblocks/pcr.h> @@ -110,55 +112,55 @@ return get_socket_stack_busno(socket, PCU_IIO_STACK); } +#if ENV_RAMSTAGE void config_reset_cpl3_csrs(void) { uint32_t data, plat_info, max_min_turbo_limit_ratio; + struct device *dev; - for (uint32_t socket = 0; socket < MAX_SOCKET; ++socket) { - uint32_t bus = get_socket_stack_busno(socket, PCU_IIO_STACK); - - /* configure PCU_CR0_FUN csrs */ - pci_devfn_t cr0_dev = PCI_DEV(bus, PCU_DEV, PCU_CR0_FUN); - data = pci_s_read_config32(cr0_dev, PCU_CR0_P_STATE_LIMITS); + dev = NULL; + while ((dev = dev_find_device(PCI_VID_INTEL, PCU_CR0_DEVID, dev))) { + data = pci_read_config32(dev, PCU_CR0_P_STATE_LIMITS); data |= P_STATE_LIMITS_LOCK; - pci_s_write_config32(cr0_dev, PCU_CR0_P_STATE_LIMITS, data); + pci_write_config32(dev, PCU_CR0_P_STATE_LIMITS, data); - plat_info = pci_s_read_config32(cr0_dev, PCU_CR0_PLATFORM_INFO); - dump_csr64("", cr0_dev, PCU_CR0_PLATFORM_INFO); + plat_info = pci_read_config32(dev, PCU_CR0_PLATFORM_INFO); + dump_csr64(dev, PCU_CR0_PLATFORM_INFO); max_min_turbo_limit_ratio = (plat_info & MAX_NON_TURBO_LIM_RATIO_MASK) >> MAX_NON_TURBO_LIM_RATIO_SHIFT; printk(BIOS_SPEW, "plat_info: 0x%x, max_min_turbo_limit_ratio: 0x%x\n", plat_info, max_min_turbo_limit_ratio); + } - /* configure PCU_CR1_FUN csrs */ - pci_devfn_t cr1_dev = PCI_DEV(bus, PCU_DEV, PCU_CR1_FUN); - - data = pci_s_read_config32(cr1_dev, PCU_CR1_SAPMCTL); + dev = NULL; + while ((dev = dev_find_device(PCI_VID_INTEL, PCU_CR1_DEVID, dev))) { + data = pci_read_config32(dev, PCU_CR1_SAPMCTL); /* clear bits 27:31 - FSP sets this with 0x7 which needs to be cleared */ data &= 0x0fffffff; data |= SAPMCTL_LOCK_MASK; - pci_s_write_config32(cr1_dev, PCU_CR1_SAPMCTL, data); + pci_write_config32(dev, PCU_CR1_SAPMCTL, data); + } - /* configure PCU_CR1_FUN csrs */ - pci_devfn_t cr2_dev = PCI_DEV(bus, PCU_DEV, PCU_CR2_FUN); - + dev = NULL; + while ((dev = dev_find_device(PCI_VID_INTEL, PCU_CR2_DEVID, dev))) { data = PCIE_IN_PKGCSTATE_L1_MASK; - pci_s_write_config32(cr2_dev, PCU_CR2_PKG_CST_ENTRY_CRITERIA_MASK, data); + pci_write_config32(dev, PCU_CR2_PKG_CST_ENTRY_CRITERIA_MASK, data); data = KTI_IN_PKGCSTATE_L1_MASK; - pci_s_write_config32(cr2_dev, PCU_CR2_PKG_CST_ENTRY_CRITERIA_MASK2, data); + pci_write_config32(dev, PCU_CR2_PKG_CST_ENTRY_CRITERIA_MASK2, data); data = PROCHOT_RATIO; printk(BIOS_SPEW, "PCU_CR2_PROCHOT_RESPONSE_RATIO_REG data: 0x%x\n", data); - pci_s_write_config32(cr2_dev, PCU_CR2_PROCHOT_RESPONSE_RATIO_REG, data); - dump_csr("", cr2_dev, PCU_CR2_PROCHOT_RESPONSE_RATIO_REG); + pci_write_config32(dev, PCU_CR2_PROCHOT_RESPONSE_RATIO_REG, data); + dump_csr(dev, PCU_CR2_PROCHOT_RESPONSE_RATIO_REG); - data = pci_s_read_config32(cr2_dev, PCU_CR2_DYNAMIC_PERF_POWER_CTL); + data = pci_read_config32(dev, PCU_CR2_DYNAMIC_PERF_POWER_CTL); data |= UNOCRE_PLIMIT_OVERRIDE_SHIFT; - pci_s_write_config32(cr2_dev, PCU_CR2_DYNAMIC_PERF_POWER_CTL, data); + pci_write_config32(dev, PCU_CR2_DYNAMIC_PERF_POWER_CTL, data); } } +#endif /* * EX: SKX-SP diff --git a/src/soc/intel/xeon_sp/spr/chip.c b/src/soc/intel/xeon_sp/spr/chip.c index cebe4fe..d57b240 100644 --- a/src/soc/intel/xeon_sp/spr/chip.c +++ b/src/soc/intel/xeon_sp/spr/chip.c @@ -6,6 +6,7 @@ #include <cpu/x86/lapic.h> #include <device/pci.h> #include <device/pci_ids.h> +#include <device/pci_def.h> #include <device/pciexp.h> #include <intelblocks/gpio.h> #include <intelblocks/lpc_lib.h> @@ -80,45 +81,41 @@ } } -static void pcu_pci_or_config32(u8 bus, u8 func, u32 reg, u32 orval) -{ - u32 data; - const uint32_t pcie_offset = PCI_DEV(bus, PCU_DEV, func); - - data = pci_s_read_config32(pcie_offset, reg); - data |= orval; - pci_s_write_config32(pcie_offset, reg, data); -} - static void set_pcu_locks(void) { - for (uint32_t socket = 0; socket < CONFIG_MAX_SOCKET; ++socket) { - if (!soc_cpu_is_enabled(socket)) - continue; - const uint32_t bus = get_ubox_busno(socket, UNCORE_BUS_1); + struct device *dev = NULL; - /* configure PCU_CR0_FUN csrs */ - pcu_pci_or_config32(bus, PCU_CR0_FUN, PCU_CR0_P_STATE_LIMITS, - P_STATE_LIMITS_LOCK); - pcu_pci_or_config32(bus, PCU_CR0_FUN, PCU_CR0_PACKAGE_RAPL_LIMIT_UPR, - PKG_PWR_LIM_LOCK_UPR); - pcu_pci_or_config32(bus, PCU_CR0_FUN, PCU_CR0_TURBO_ACTIVATION_RATIO, - TURBO_ACTIVATION_RATIO_LOCK); + while ((dev = dev_find_device(PCI_VID_INTEL, PCU_CR0_DEVID, dev))) { + printk(BIOS_SPEW, "%s: locking registers\n", dev_path(dev)); + pci_or_config32(dev, PCU_CR0_P_STATE_LIMITS, P_STATE_LIMITS_LOCK); + pci_or_config32(dev, PCU_CR0_PACKAGE_RAPL_LIMIT_UPR, + PKG_PWR_LIM_LOCK_UPR); + pci_or_config32(dev, PCU_CR0_TURBO_ACTIVATION_RATIO, + TURBO_ACTIVATION_RATIO_LOCK); + } - /* configure PCU_CR2_FUN csrs */ - pcu_pci_or_config32(bus, PCU_CR2_FUN, PCU_CR2_DRAM_POWER_INFO_UPR, - DRAM_POWER_INFO_LOCK_UPR); - pcu_pci_or_config32(bus, PCU_CR2_FUN, PCU_CR2_DRAM_PLANE_POWER_LIMIT_UPR, - PP_PWR_LIM_LOCK_UPR); + dev = NULL; + while ((dev = dev_find_device(PCI_VID_INTEL, PCU_CR2_DEVID, dev))) { + printk(BIOS_SPEW, "%s: locking registers\n", dev_path(dev)); + pci_or_config32(dev, PCU_CR2_DRAM_POWER_INFO_UPR, + DRAM_POWER_INFO_LOCK_UPR); + pci_or_config32(dev, PCU_CR2_DRAM_PLANE_POWER_LIMIT_UPR, + PP_PWR_LIM_LOCK_UPR); + } - /* configure PCU_CR3_FUN csrs */ - pcu_pci_or_config32(bus, PCU_CR3_FUN, PCU_CR3_CONFIG_TDP_CONTROL, TDP_LOCK); + dev = NULL; + while ((dev = dev_find_device(PCI_VID_INTEL, PCU_CR3_DEVID, dev))) { + printk(BIOS_SPEW, "%s: locking registers\n", dev_path(dev)); + pci_or_config32(dev, PCU_CR3_CONFIG_TDP_CONTROL, TDP_LOCK); + } - /* configure PCU_CR6_FUN csrs */ - pcu_pci_or_config32(bus, PCU_CR6_FUN, PCU_CR6_PLATFORM_RAPL_LIMIT_CFG_UPR, - PLT_PWR_LIM_LOCK_UPR); - pcu_pci_or_config32(bus, PCU_CR6_FUN, PCU_CR6_PLATFORM_POWER_INFO_CFG_UPR, - PLT_PWR_INFO_LOCK_UPR); + dev = NULL; + while ((dev = dev_find_device(PCI_VID_INTEL, PCU_CR6_DEVID, dev))) { + printk(BIOS_SPEW, "%s: locking registers\n", dev_path(dev)); + pci_or_config32(dev, PCU_CR6_PLATFORM_RAPL_LIMIT_CFG_UPR, + PLT_PWR_LIM_LOCK_UPR); + pci_or_config32(dev, PCU_CR6_PLATFORM_POWER_INFO_CFG_UPR, + PLT_PWR_INFO_LOCK_UPR); } } diff --git a/src/soc/intel/xeon_sp/spr/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/spr/include/soc/pci_devs.h index 158352a..1d7dedd 100644 --- a/src/soc/intel/xeon_sp/spr/include/soc/pci_devs.h +++ b/src/soc/intel/xeon_sp/spr/include/soc/pci_devs.h @@ -47,6 +47,7 @@ #define PCU_DEV 30 #define PCU_CR0_FUN 0 +#define PCU_CR0_DEVID 0x3258 #define PCU_DEV_CR0(bus) _PCU_DEV(bus, PCU_CR0_FUN) #define PCU_CR0_PLATFORM_INFO 0xa8 #define PCU_CR0_TURBO_ACTIVATION_RATIO 0xb0 @@ -62,6 +63,7 @@ #define VR_CURRENT_CONFIG_LOCK BIT(31) #define PCU_CR1_FUN 1 +#define PCU_CR1_DEVID 0x3259 #define PCU_DEV_CR1(bus) _PCU_DEV(bus, PCU_CR1_FUN) #define PCU_CR1_BIOS_MB_DATA_REG 0x8c @@ -86,6 +88,7 @@ #define PCU_CR1_DESIRED_CORES_CFG2_REG_LOCK_MASK BIT(31) #define PCU_CR2_FUN 2 +#define PCU_CR2_DEVID 0x325a #define PCU_DEV_CR2(bus) _PCU_DEV(bus, PCU_CR2_FUN) #define PCU_CR2_DRAM_POWER_INFO_LWR 0xa8 #define PCU_CR2_DRAM_POWER_INFO_UPR (PCU_CR2_DRAM_POWER_INFO_LWR + 4) @@ -96,6 +99,7 @@ #define PP_PWR_LIM_LOCK_UPR BIT(31) #define PCU_CR3_FUN 3 +#define PCU_CR3_DEVID 0x325b #define PCU_CR3_CAPID4 0x94 #define ERR_SPOOFING_DIS 1 #define PCU_DEV_CR3(bus) _PCU_DEV(bus, PCU_CR3_FUN) @@ -105,6 +109,7 @@ #define OC_LOCK BIT(20) #define PCU_CR4_FUN 4 +#define PCU_CR4_DEVID 0x325c #define PCU_VIRAL_CONTROL 0x84 #define PCU_FW_ERR_EN (1 << 10) #define PCU_UC_ERR_EN (1 << 9) @@ -112,6 +117,7 @@ #define PCU_EMCA_MODE (1 << 2) #define PCU_CR6_FUN 6 +#define PCU_CR6_DEVID 0x325e #define PCU_DEV_CR6(bus) _PCU_DEV(bus, PCU_CR6_FUN) #define PCU_CR6_PLATFORM_RAPL_LIMIT_CFG_LWR 0xa8 #define PCU_CR6_PLATFORM_RAPL_LIMIT_CFG_UPR (PCU_CR6_PLATFORM_RAPL_LIMIT_CFG_LWR + 4) -- To view, visit https://review.coreboot.org/c/coreboot/+/80093?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I06694715cba76b101165f1cef66d161b0f896b26 Gerrit-Change-Number: 80093 Gerrit-PatchSet: 13 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[main]: lib: Declare heap in assembly
by Lean Sheng Tan (Code Review) 28 Feb '24

28 Feb '24

Attention is currently required from: Arthur Heymans, Julius Werner, Maximilian Brune, Nico Huber. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80776?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: lib: Declare heap in assembly ...................................................................... Patch Set 2: Code-Review+1 (1 comment) Patchset: PS2: cannot find the commit that mentioned in the commit message: commit 99bf23c9e73ca -- To view, visit https://review.coreboot.org/c/coreboot/+/80776?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I67cb5ce886fda313e0720b0bc7c6e66e4aae45fa Gerrit-Change-Number: 80776 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Wed, 28 Feb 2024 16:59:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[S] Change in coreboot[main]: lib: Declare heap in assembly
by Subrata Banik (Code Review) 28 Feb '24

28 Feb '24

Attention is currently required from: Arthur Heymans, Julius Werner, Maximilian Brune, Nico Huber. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80776?usp=email ) Change subject: lib: Declare heap in assembly ...................................................................... Patch Set 2: Code-Review+2 (2 comments) Patchset: PS2: tested on rex and looks good. lets land this cl. PS2: > yes before this patch i saw this error: > [INFO ] MMAP window: SPI flash base=0x1000000, Host base=0xff000000, Size=0x1000000 > [INFO ] CBFS: Found 'fallback/ramstage' @0x98b40 size 0x1eb44 in mcache @0x789fd10c > [DEBUG] Loading module at 0x78995000 with entry 0x78995000. filesize: 0x41340 memsize: 0x58af0 > [DEBUG] Processing 4940 relocs. Offset value of 0x74995000 > [DEBUG] Error: Can't add stage_cache 57a9e100 to imd > > After applying this patch it is gone. ``` > [DEBUG] Error: Can't add stage_cache 57a9e100 to imd ``` shouldn't this has to be treated as ERROR type instead debug ? -- To view, visit https://review.coreboot.org/c/coreboot/+/80776?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I67cb5ce886fda313e0720b0bc7c6e66e4aae45fa Gerrit-Change-Number: 80776 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Wed, 28 Feb 2024 16:59:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-MessageType: comment

1 0

[S] Change in coreboot[main]: lib: Declare heap in assembly
by Lean Sheng Tan (Code Review) 28 Feb '24

28 Feb '24

Attention is currently required from: Arthur Heymans, Julius Werner, Maximilian Brune, Nico Huber, Subrata Banik. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80776?usp=email ) Change subject: lib: Declare heap in assembly ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: yes before this patch i saw this error: [INFO ] MMAP window: SPI flash base=0x1000000, Host base=0xff000000, Size=0x1000000 [INFO ] CBFS: Found 'fallback/ramstage' @0x98b40 size 0x1eb44 in mcache @0x789fd10c [DEBUG] Loading module at 0x78995000 with entry 0x78995000. filesize: 0x41340 memsize: 0x58af0 [DEBUG] Processing 4940 relocs. Offset value of 0x74995000 [DEBUG] Error: Can't add stage_cache 57a9e100 to imd After applying this patch it is gone. -- To view, visit https://review.coreboot.org/c/coreboot/+/80776?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I67cb5ce886fda313e0720b0bc7c6e66e4aae45fa Gerrit-Change-Number: 80776 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Wed, 28 Feb 2024 16:47:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[main]: lib: Declare heap in assembly
by Lean Sheng Tan (Code Review) 28 Feb '24

28 Feb '24

Attention is currently required from: Arthur Heymans, Julius Werner, Maximilian Brune, Nico Huber, Subrata Banik. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80776?usp=email ) Change subject: lib: Declare heap in assembly ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/80776?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I67cb5ce886fda313e0720b0bc7c6e66e4aae45fa Gerrit-Change-Number: 80776 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Wed, 28 Feb 2024 16:47:06 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: ec/chromeec: Enable auto fan control on startup
by Matt DeVillier (Code Review) 28 Feb '24

28 Feb '24

Attention is currently required from: Forest Mittelberg. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80712?usp=email ) Change subject: ec/chromeec: Enable auto fan control on startup ...................................................................... Patch Set 2: (1 comment) File src/ec/google/chromeec/ec.c: https://review.coreboot.org/c/coreboot/+/80712/comment/8593b59a_134952c5 : PS1, Line 1195: google_chromeec_command > you should be able to call `ec_cmd_thermal_auto_fan_ctrl()` […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/80712?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I08a8562531f8af0c71230477d0221d536443f096 Gerrit-Change-Number: 80712 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Forest Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Forest Mittelberg <bmbm(a)google.com> Gerrit-Comment-Date: Wed, 28 Feb 2024 16:12:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Caveh Jalali <caveh(a)chromium.org> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: device/pnp_device: fix log levels for unassigned resource messages
by Arthur Heymans (Code Review) 28 Feb '24

28 Feb '24

Attention is currently required from: Felix Held, Nico Huber. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80774?usp=email ) Change subject: device/pnp_device: fix log levels for unassigned resource messages ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/80774?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I232e60ef7ae672e18cc1837b8e6a0427d01c142b Gerrit-Change-Number: 80774 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 28 Feb 2024 15:55:28 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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