coreboot-gerrit February 2024

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[XS] Change in coreboot[main]: Revert "lib: Explicitly declare heap as NOLOAD"
by Nico Huber (Code Review) 28 Feb '24

28 Feb '24

Attention is currently required from: Arthur Heymans, Caveh Jalali, Julius Werner, Subrata Banik. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80775?usp=email ) Change subject: Revert "lib: Explicitly declare heap as NOLOAD" ...................................................................... Patch Set 1: Code-Review+1 (1 comment) Patchset: PS1: Haven't fully figured out what went wrong yet. The `memsz` in the program header seems to lose the 1MiB heap, i.e. it's not allocated? Which seems wrong. -- To view, visit https://review.coreboot.org/c/coreboot/+/80775?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8d49e2dc49cd2935a9d8023c989869ec9558039e Gerrit-Change-Number: 80775 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Wed, 28 Feb 2024 14:37:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: device/pnp_device: fix log levels for unassigned resource messages
by Felix Held (Code Review) 28 Feb '24

28 Feb '24

Attention is currently required from: Nico Huber. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80774?usp=email ) Change subject: device/pnp_device: fix log levels for unassigned resource messages ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > Hmmm, hard to remember why we split the two cases up in the first place. […] it was to not get error messages for the values of misc registers not being specified in devicetree -- To view, visit https://review.coreboot.org/c/coreboot/+/80774?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I232e60ef7ae672e18cc1837b8e6a0427d01c142b Gerrit-Change-Number: 80774 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Wed, 28 Feb 2024 13:55:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: Revert "lib: Explicitly declare heap as NOLOAD"
by Kapil Porwal (Code Review) 28 Feb '24

28 Feb '24

Attention is currently required from: Arthur Heymans, Caveh Jalali, Julius Werner, Subrata Banik. Kapil Porwal has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80775?usp=email ) Change subject: Revert "lib: Explicitly declare heap as NOLOAD" ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/80775?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8d49e2dc49cd2935a9d8023c989869ec9558039e Gerrit-Change-Number: 80775 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Wed, 28 Feb 2024 13:39:33 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: Revert "lib: Explicitly declare heap as NOLOAD"
by Subrata Banik (Code Review) 28 Feb '24

28 Feb '24

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80775?usp=email ) Change subject: Revert "lib: Explicitly declare heap as NOLOAD" ...................................................................... Revert "lib: Explicitly declare heap as NOLOAD" This reverts commit 99bf23c9e73c7492ee9d5c1f208bceedf3ff7cb5. This patch causes the boot regression at depthcharge with below error signature. Able to boot to OS after reverting this patch. ``` Starting depthcharge on Rex... WARNING: can't convert coreboot GPIOs, 'lid' won't be resampled at runtime! WARNING: can't convert coreboot GPIOs, 'power' won't be resampled at runtime! fw_config match found: AUDIO=MAX98360_ALC5682I_I2S Looking for NVMe Controller 0x30069a60 @ 00:06:00 libc/lp_vboot.c:25 vboot_get_context(): vboot workbuf could not be initialized, error: 0x10080030 Ready for GDB connection. ``` Change-Id: I8d49e2dc49cd2935a9d8023c989869ec9558039e Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/lib/program.ld 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/80775/1 diff --git a/src/lib/program.ld b/src/lib/program.ld index 6d72d9e..21f4be8 100644 --- a/src/lib/program.ld +++ b/src/lib/program.ld @@ -131,7 +131,7 @@ #endif #if ENV_HAS_HEAP_SECTION -.heap . (NOLOAD) : { +.heap . : { . = ALIGN(ARCH_POINTER_ALIGN_SIZE); _heap = .; . += CONFIG_HEAP_SIZE; -- To view, visit https://review.coreboot.org/c/coreboot/+/80775?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8d49e2dc49cd2935a9d8023c989869ec9558039e Gerrit-Change-Number: 80775 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[main]: mb/emulation/qemu-riscv: Change to -bios option
by Maximilian Brune (Code Review) 28 Feb '24

28 Feb '24

Attention is currently required from: Maximilian Brune, Philipp Hug, ron minnich. Hello Philipp Hug, build bot (Jenkins), ron minnich, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/80746?usp=email to look at the new patch set (#4). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: mb/emulation/qemu-riscv: Change to -bios option ...................................................................... mb/emulation/qemu-riscv: Change to -bios option This changes the virt target so that it can be run with the -bios option and a pflash backend for the flash. QEMU can now be run as follows: qemu -M virt -m 1G -nographic -bios build/coreboot.rom \ -drive if=pflash,file=./build/coreboot.rom,format=raw coreboot will start in DRAM, but still have a flash to put CBFS onto and to load subsequent stages and payload from. Probing ram size on riscv is currently not working therefore the RAM size stays fixed for now. Tested bootflow: coreboot -> OpenSBI -> Linux -> u-root Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> Change-Id: I009d97fa3e13068b91c604e987e50a65e525407d --- M Documentation/mainboard/emulation/qemu-riscv.md M src/mainboard/emulation/Kconfig M src/mainboard/emulation/qemu-riscv/Kconfig M src/mainboard/emulation/qemu-riscv/Makefile.mk A src/mainboard/emulation/qemu-riscv/cbmem.c A src/mainboard/emulation/qemu-riscv/chip.c M src/mainboard/emulation/qemu-riscv/devicetree.cb M src/mainboard/emulation/qemu-riscv/include/mainboard/addressmap.h M src/mainboard/emulation/qemu-riscv/mainboard.c M src/mainboard/emulation/qemu-riscv/memlayout.ld M src/mainboard/emulation/qemu-riscv/rom_media.c M src/mainboard/emulation/qemu-riscv/romstage.c 12 files changed, 115 insertions(+), 55 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/80746/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/80746?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I009d97fa3e13068b91c604e987e50a65e525407d Gerrit-Change-Number: 80746 Gerrit-PatchSet: 4 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: soc/intel/meteorlake: Select MRC_CACHE_USING_MRC_VERSION
by Paul Menzel (Code Review) 28 Feb '24

28 Feb '24

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Jincheng Li, Ronak Kanabar, Tarun. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80728?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: soc/intel/meteorlake: Select MRC_CACHE_USING_MRC_VERSION ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/80728/comment/32a75d0d_1618b295 : PS3, Line 12: Thank you for the update. I am sorry to bother, but commit messages should be self-contained. I have the impression, that you expect knowledge from the next commit. More background is needed, so the reviewer does not need to verify the correctness and get the whole picture. From the next change-set I84fdcfbf3c833a7ccb259a1a1d4be0bcfe291dc3 I gather `default y if UDK_VERSION >= 202302`. Why was it added like this? Why is this now only added to Meteor Lake and not all other SoCs? -- To view, visit https://review.coreboot.org/c/coreboot/+/80728?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I10594df7c8fdc5cfe9b68975e01ae65859735544 Gerrit-Change-Number: 80728 Gerrit-PatchSet: 3 Gerrit-Owner: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Wed, 28 Feb 2024 12:17:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[main]: cpu/x86/(sipi|smm): Pass on CR3 from ramstage
by Felix Held (Code Review) 28 Feb '24

28 Feb '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80335?usp=email ) ( 5 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: cpu/x86/(sipi|smm): Pass on CR3 from ramstage ...................................................................... cpu/x86/(sipi|smm): Pass on CR3 from ramstage To allow for more flexibility like generating page tables at runtime or page tables that are part of the ramstage, add a parameter to sipi_vector.S and smm_stub.S so that APs use the same page tables as the BSP during their initialization. Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Change-Id: I1250ea6f63c65228178ee66e06d988dadfcc2a37 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80335 Reviewed-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Jérémy Compostella <jeremy.compostella(a)intel.com> --- M src/cpu/x86/mp_init.c M src/cpu/x86/sipi_vector.S M src/cpu/x86/smm/smm_stub.S M src/include/cpu/x86/smm.h 4 files changed, 12 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved Jérémy Compostella: Looks good to me, but someone else must approve diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index d3af6ecc..b336e9f 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -98,6 +98,7 @@ uint32_t msr_table_ptr; uint32_t msr_count; uint32_t c_handler; + uint32_t cr3; atomic_t ap_count; } __packed; @@ -361,6 +362,7 @@ else sp->microcode_lock = 0; sp->c_handler = (uintptr_t)&ap_init; + sp->cr3 = read_cr3(); ap_count = &sp->ap_count; atomic_set(ap_count, 0); @@ -763,6 +765,7 @@ .cpu_save_state_size = save_state_size, .num_concurrent_save_states = 1, .handler = smm_do_relocation, + .cr3 = read_cr3(), }; if (smm_setup_relocation_handler(&smm_params)) { @@ -787,6 +790,7 @@ .num_cpus = num_cpus, .cpu_save_state_size = save_state_size, .num_concurrent_save_states = num_cpus, + .cr3 = read_cr3(), }; printk(BIOS_DEBUG, "Installing permanent SMM handler to 0x%08lx\n", smbase); diff --git a/src/cpu/x86/sipi_vector.S b/src/cpu/x86/sipi_vector.S index 923e398..b7d700f 100644 --- a/src/cpu/x86/sipi_vector.S +++ b/src/cpu/x86/sipi_vector.S @@ -38,6 +38,8 @@ .long 0 c_handler: .long 0 +cr3: +.long 0 ap_count: .long 0 @@ -224,7 +226,7 @@ #if ENV_X86_64 /* entry64.inc preserves ebx, esi, edi, ebp */ - setup_longmode $(CONFIG_ARCH_X86_64_PGTBL_LOC) + setup_longmode cr3 movabs c_handler, %eax call *%rax diff --git a/src/cpu/x86/smm/smm_stub.S b/src/cpu/x86/smm/smm_stub.S index 9f1f21d..9b4b966 100644 --- a/src/cpu/x86/smm/smm_stub.S +++ b/src/cpu/x86/smm/smm_stub.S @@ -23,6 +23,8 @@ .long 0 c_handler: .long 0 +cr3: +.long 0 /* apic_to_cpu_num is a table mapping the default APIC id to CPU num. If the * APIC id is found at the given index, the contiguous CPU number is index * into the table. */ @@ -196,7 +198,7 @@ #if ENV_X86_64 mov %ecx, %edi /* entry64.inc preserves ebx, esi, edi, ebp */ - setup_longmode $(CONFIG_ARCH_X86_64_PGTBL_LOC) + setup_longmode cr3 mov %edi, %ecx diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index beb88fa..a12065b 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -109,6 +109,7 @@ u32 stack_size; u32 stack_top; u32 c_handler; + u32 cr3; /* The apic_id_to_cpu provides a mapping from APIC id to CPU number. * The CPU number is indicated by the index into the array by matching * the default APIC id and value at the index. The stub loader @@ -165,6 +166,7 @@ size_t num_concurrent_save_states; smm_handler_t handler; + uint32_t cr3; }; /* All of these return 0 on success, < 0 on failure. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/80335?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1250ea6f63c65228178ee66e06d988dadfcc2a37 Gerrit-Change-Number: 80335 Gerrit-PatchSet: 7 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[main]: soc/intel/common/block/cse: Use IFWI build version for update check
by Subrata Banik (Code Review) 28 Feb '24

28 Feb '24

Attention is currently required from: Anil Kumar K, Jamie Ryu, Paul Menzel, Pratikkumar V Prajapati, Wonkyu Kim. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79413?usp=email ) Change subject: soc/intel/common/block/cse: Use IFWI build version for update check ...................................................................... Patch Set 18: (1 comment) File src/soc/intel/common/block/cse/cse_lite.c: https://review.coreboot.org/c/coreboot/+/79413/comment/9cf19301_5f708091 : PS18, Line 896: /* Read IFWI Build Version from CSE RW */ > i thought we already had this data available as part of `cse_info_in_cbmem->cse_fwp_version.cur_cse_fw_version`. just find `CBMEM_ID_CSE_INFO` and get the data > > we may not need to read this data again from IFWI. if this is IFWI version then line 899 may need some modification. -- To view, visit https://review.coreboot.org/c/coreboot/+/79413?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib95ffeabda01c66fcce35ca3065c06362c75d848 Gerrit-Change-Number: 79413 Gerrit-PatchSet: 18 Gerrit-Owner: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Dinesh Gehlot <digehlot(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Comment-Date: Wed, 28 Feb 2024 12:09:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: soc/intel/meteorlake: Select MRC_CACHE_USING_MRC_VERSION
by Subrata Banik (Code Review) 28 Feb '24

28 Feb '24

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Jincheng Li, Paul Menzel, Ronak Kanabar, Tarun. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80728?usp=email ) Change subject: soc/intel/meteorlake: Select MRC_CACHE_USING_MRC_VERSION ...................................................................... Patch Set 3: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/80728/comment/14a2f1a8_42dd5352 : PS2, Line 7: src/ > Done Acknowledged https://review.coreboot.org/c/coreboot/+/80728/comment/aba59893_d34fa377 : PS2, Line 8: > Done Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/80728?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I10594df7c8fdc5cfe9b68975e01ae65859735544 Gerrit-Change-Number: 80728 Gerrit-PatchSet: 3 Gerrit-Owner: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Wed, 28 Feb 2024 12:06:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Jincheng Li <jincheng.li(a)intel.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/google/skyrim/var/skyrim: Hide fingerprint reader from Windows OS
by Paul Menzel (Code Review) 28 Feb '24

28 Feb '24

Attention is currently required from: Felix Held, Jason Nien, Martin Roth, Matt DeVillier. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80711?usp=email ) Change subject: mb/google/skyrim/var/skyrim: Hide fingerprint reader from Windows OS ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/80711/comment/70d460e9_671bde15 : PS1, Line 9: is needed Sorry, I do not understand this. How can the fingerprint reader be used then? -- To view, visit https://review.coreboot.org/c/coreboot/+/80711?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia700aa4ccd478bc734db012e1419e566a5dcf493 Gerrit-Change-Number: 80711 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 28 Feb 2024 11:59:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit February 2024