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I'd like you to reexamine a change. Please visit
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Change subject: mb/google/brox: Handle bluetooth enable on devices
......................................................................
mb/google/brox: Handle bluetooth enable on devices
For devices that require CNVi Bluetooth select WIFI_BT_CNVI
in FW_CONFIG. Discrete Bluetooth devices need to select
WIFI_BT_PCIE.
BUG=b:319188820,b:325084796
BRANCH=None
TEST=Boot image on SKU1,SKU2 and check BT devices enumerate.
Change-Id: Iba008682fcfa7ddc1ec400649c8742c721666f1d
Signed-off-by: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com>
---
M src/mainboard/google/brox/variants/brox/overridetree.cb
M src/mainboard/google/brox/variants/brox/variant.c
2 files changed, 10 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/80564/5
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Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80500?usp=email )
Change subject: soc/alderlake/romstage: Set UsbTcPortEnPreMem UPD based on devicetree
......................................................................
Patch Set 2: Code-Review+1
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/80500/comment/b74b63c2_1b1ab49b :
PS2, Line 13:
> Not particularly visible, but what FSP does with these is the proper configuration of the sideband u […]
Thanks. Let's just put this into the commit message.
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I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/80564?usp=email
to look at the new patch set (#4).
Change subject: mb/google/brox: Handle bluetooth enable on devices
......................................................................
mb/google/brox: Handle bluetooth enable on devices
For devices that require CNVi Bluetooth select WIFI_BT_CNVI
in FW_CONFIG. Discrete Bluetooth devices need to select
WIFI_BT_PCIE.
BUG=b:319188820,b:325084796
BRANCH=None
TEST=Boot image on SKU1,SKU2 and check BT devices enumerate.
Change-Id: Iba008682fcfa7ddc1ec400649c8742c721666f1d
Signed-off-by: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com>
---
M src/mainboard/google/brox/variants/brox/overridetree.cb
M src/mainboard/google/brox/variants/brox/variant.c
2 files changed, 9 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/80564/4
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I'd like you to reexamine a change. Please visit
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The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: mb/google/brox: Handle bluetooth enable on devices
......................................................................
mb/google/brox: Handle bluetooth enable on devices
On devices that don't have CNVi Bluetooth use BT_DISCRETE and
that have CNVi Bluetooth use BT_CNVI with enable CNVi
in FW_CONFIG flag.
BUG=b:319188820,b:325084796
BRANCH=None
TEST=Boot image on SKU1,SKU2 and check BT devices enumerate.
Change-Id: Iba008682fcfa7ddc1ec400649c8742c721666f1d
Signed-off-by: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com>
---
M src/mainboard/google/brox/variants/brox/overridetree.cb
M src/mainboard/google/brox/variants/brox/variant.c
2 files changed, 9 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/80564/3
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Change subject: soc/alderlake/romstage: Set UsbTcPortEnPreMem UPD based on devicetree
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/80500/comment/89f45c7a_a06299f3 :
PS2, Line 13:
> Did you notice any difference in behavior?
Not particularly visible, but what FSP does with these is the proper configuration of the sideband use BSSB_LSx pins for the enabled Type-C ports, which might be important for some initialization of DCI debug and Tyep-C SubSystem overall.
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Change subject: riscv/mb/qemu: fix qemu invocation comment
......................................................................
Patch Set 12: Code-Review+2
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Change subject: soc/intel/mtl: Skip RW CBFS ucode update if RO is locked
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/80567/comment/6e9b3318_7bac1179 :
PS1, Line 16: 3. The kernel can still load microcode updates without affecting
: AP FW boot time.
:
How is the kernel faster than coreboot at loading microcode? Isn't this just moving the process of updating the microcode update to a later stage?
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Change subject: riscv/mb/qemu: fix qemu invocation comment
......................................................................
Patch Set 12: Code-Review+1
(1 comment)
Patchset:
PS5:
> thanks, added for qemu-riscv
Awesome, thanks! Please also mention it in the commit message.
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Change subject: soc/intel/jasperlake: select SOC_INTEL_COMMON_BLOCK_DTT
......................................................................
Patch Set 1: Code-Review+1
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Change subject: mb/intel/tglrvp: Drop selection of SOC_INTEL_COMMON_BLOCK_DTT
......................................................................
Patch Set 1: Code-Review+1
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