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Change subject: soc/intel/common/block/sata: Fix scope for SATA ACPI device
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
> I think `src/soc/intel/alderlake/acpi/sata. […]
done: CB:80562
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Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80562?usp=email )
Change subject: soc/intel/alderlake/acpi: Drop ACPI stub for SATA device
......................................................................
soc/intel/alderlake/acpi: Drop ACPI stub for SATA device
This is now generated by acpigen in the common/block/sata module.
Change-Id: Ic45a059f47a090aa1993e83884408a82826b30cf
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
---
D src/soc/intel/alderlake/acpi/sata.asl
1 file changed, 0 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/80562/1
diff --git a/src/soc/intel/alderlake/acpi/sata.asl b/src/soc/intel/alderlake/acpi/sata.asl
deleted file mode 100644
index 4e8f424..0000000
--- a/src/soc/intel/alderlake/acpi/sata.asl
+++ /dev/null
@@ -1,7 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-
-Device (SATA)
-{
- Name (_ADR, 0x00170000)
- Name (_DDN, "SATA Controller")
-}
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Change subject: soc/intel/common/block/dtt: Add ACPI stub for TCPU device
......................................................................
Patch Set 4:
(1 comment)
File src/soc/intel/common/block/dtt/dtt.c:
https://review.coreboot.org/c/coreboot/+/80553/comment/dfb8fa54_c86b3015 :
PS3, Line 26:
: /* Skip if DPTF driver in use */
: if (CONFIG(DRIVERS_INTEL_DPTF))
: return;
> will do
Done
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Change subject: soc/intel/common/block/dtt: Add ACPI stub for TCPU device
......................................................................
Patch Set 3:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/80553/comment/0c1ea338_79c4a50b :
PS3, Line 16: not use the Intel DPTF driver.
> I couldn't find such a reference in non-dptf code. Do you know where […]
the LPI constraint list in the PEPD object
File src/soc/intel/common/block/dtt/dtt.c:
https://review.coreboot.org/c/coreboot/+/80553/comment/84c35f69_500eb53c :
PS3, Line 26:
: /* Skip if DPTF driver in use */
: if (CONFIG(DRIVERS_INTEL_DPTF))
: return;
> +1 it would allow the linker to drop the acpi_device_scope() call.
will do
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Change subject: soc/intel/cannonlake: select SOC_INTEL_COMMON_BLOCK_DTT
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> `dtt.c` currently only hooks up scan_generic_bus(). Which shouldn't make […]
for boards which previously didn't select DTT *and* didn't select the Intel DPTF driver, they will now have the TCPU ACPI device generated so that the LPI constraint entry doesn't reference a non-existent object
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Change subject: superio/ite/it8659e: Add driver for ITE IT8659E
......................................................................
Patch Set 3: Code-Review+1
(1 comment)
Patchset:
PS3:
Not familiar enough with ACPI, but the rest seems good.
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Change subject: soc/alderlake/romstage: Set UsbTcPortEnPreMem UPD based on devicetree
......................................................................
Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/80500/comment/522af0ba_75f2e2d6 :
PS2, Line 13:
> Thanks. Let's just put this into the commit message.
Done
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Hello Kapil Porwal, Nick Vaccaro, Nico Huber, Subrata Banik, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/80500?usp=email
to look at the new patch set (#3).
Change subject: soc/alderlake/romstage: Set UsbTcPortEnPreMem UPD based on devicetree
......................................................................
soc/alderlake/romstage: Set UsbTcPortEnPreMem UPD based on devicetree
The UsbTcPortEn UPD for FSP-S is being set in ramstage, however the
equivalent FSP-M UPD, the UsbTcPortEnPreMem, was not being set.
Following the Meteor Lake example, set the UsbTcPortEnPreMem UPD
as well for Alder Lake.
Setting this FSP-M UPD will cause FSP to properly program sideband
use BSSB_LSx pins for the enabled Type-C ports. Required for proper
DCI debug and TCSS initialization flow.
Change-Id: If3b79167ec1769ddfb7d28a6c78a3e80bd10afe7
Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com>
---
M src/soc/intel/alderlake/romstage/fsp_params.c
1 file changed, 5 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/80500/3
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