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Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80567?usp=email )
Change subject: soc/intel/mtl: Skip RW CBFS ucode update if RO is locked
......................................................................
Patch Set 2:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/80567/comment/742cfa98_773a77ef :
PS1, Line 16: 3. The kernel can still load microcode updates without affecting
: AP FW boot time.
:
> > > How is the kernel faster than coreboot at loading microcode? Isn't this just moving the process of updating the microcode update to a later stage?
> >
> > you got it correct, there is nothing like kernel is faster than coreboot. we see two reasons to support this migration
> >
> > - microcode part of the RW CBFS is mostly for patching ucode hot fixes for production device which can be any way loaded by OS. Hence, it just moving the responsibility to OS as there is not much value of doing ucode loading from RW CBFS during boot. May be another 500ms later (by kernel) than what coreboot is doing today.
> >
> > - any attempt to update ucode part of RW CBFS requires firmware qualification by OEM and pushing the FW update for the device, which is costly (and FW update is not that frequent compared to the OS update). hence, atleast for the chromeos device, we don't push any ucode update for in-field device using AP FW rather we perfer to patch those using linux-firmware.
> >
> > In short, this commit msg line is just conveying that, any attempt to load ucode update by kernel doesn't impact AP FW aka BIOS boot time which we are measuring using `cbmem -t` and <1sec is critical goal for us to meet this KPI.
> >
> > I hope it explains the motivation behind pushing this CL.
>
> Thanks for explaining! I do get the argument to have the kernel do it as it's easier to update than the firmware. The boottime argument is a bit misleading: it needs to be done, whether by the kernel or by the firmware: it's just moving where it's done. Now things are ofc different if kernel has a newer version (as it gets updated more frequently you say), then this makes total sense as then both coreboot and kernel would be doing the same thing.
>
> Maybe add the OS/FW situation to the commit message?
done. updated the commit msg,
Patchset:
PS1:
> Is there something specific about mtl for this or does it make sense on more platforms?
nothing specific to MTL and we are planning to land this for other SOCs as well,.
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Hello Jakub Czapiga, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/80583?usp=email
to look at the new patch set (#2).
The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: Treewide: Fix incorrect SPDX license strings
......................................................................
Treewide: Fix incorrect SPDX license strings
These strings didn't match the license names exactly, so update them
to match.
Change-Id: Ib946eb15ca5fa64cbd6b657350b989b4a4c1b7b7
Signed-off-by: Martin Roth <gaumless(a)gmail.com>
---
M .clang-format
M payloads/libpayload/tests/libcbfs/cbfs-lookup-test.c
A retained-copyrights.txt
M src/vendorcode/amd/pi/Kconfig
M util/cbfstool/Makefile
M util/kconfig/Makefile
M util/kconfig/conf.c
M util/kconfig/confdata.c
M util/kconfig/expr.c
M util/kconfig/expr.h
M util/kconfig/gconf-cfg.sh
M util/kconfig/gconf.c
M util/kconfig/images.c
M util/kconfig/images.h
M util/kconfig/lexer.l
M util/kconfig/lexer.lex.c_shipped
M util/kconfig/list.h
M util/kconfig/lkc.h
M util/kconfig/lkc_proto.h
M util/kconfig/lxdialog/checklist.c
M util/kconfig/lxdialog/dialog.h
M util/kconfig/lxdialog/inputbox.c
M util/kconfig/lxdialog/menubox.c
M util/kconfig/lxdialog/textbox.c
M util/kconfig/lxdialog/util.c
M util/kconfig/lxdialog/yesno.c
M util/kconfig/mconf-cfg.sh
M util/kconfig/mconf.c
M util/kconfig/menu.c
M util/kconfig/merge_config.sh
M util/kconfig/nconf-cfg.sh
M util/kconfig/nconf.c
M util/kconfig/nconf.gui.c
M util/kconfig/nconf.h
M util/kconfig/parser.y
M util/kconfig/preprocess.c
M util/kconfig/qconf-cfg.sh
M util/kconfig/qconf.cc
M util/kconfig/qconf.h
M util/kconfig/streamline_config.pl
M util/kconfig/symbol.c
M util/kconfig/util.c
M util/lint/checkpatch.pl
M util/nvramtool/hexdump.c
M util/nvramtool/hexdump.h
M util/scripts/config
M util/scripts/parse-maintainers.pl
47 files changed, 138 insertions(+), 45 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/80583/2
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Shelley Chen has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80467?usp=email )
Change subject: mb/google/brox: Set PCH_EC_PCH_INT_ODL pin as IOAPIC
......................................................................
mb/google/brox: Set PCH_EC_PCH_INT_ODL pin as IOAPIC
Setting the EC interrupt GPIO as an APIC is able to solve many
problems that we are currently seeing:
1. Routing through the APIC make the IRQ# associated with this pin
unavailable to claim for other devices in the kernel. This is causing
EC interrupts to not work.
2. Since EC interrupt are not working, we are not able to flash the
EC from the DUT.
3. Also, the GPI_INT configuration does not allow us to set the
polarity of the GPIO, which means that it is by default set as active
high. As a result, we are seeing an excessive number of host command
interrupts to the EC. This disappears when we change the
configuration to APIC and set the polarity as INVERT.
BUG=b:319129926,b:324707182
BRANCH=None
TEST=1. After boot up, check if ec_cros_lpcs driver was successfully
registered. Look for the following string:
"cros_ec_lpcs GOOG0004:00: Chrome EC device registered"
2. Make sure can flash the EC image from the DUT
3. Make sure EC console is not getting continuous stream of host
commands.
Change-Id: I74bff88d2ddbaf1f4b085c31d582bd66e18c438a
Signed-off-by: Shelley Chen <shchen(a)google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80467
Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Ashish Kumar Mishra <ashish.k.mishra(a)intel.corp-partner.google.com>
---
M src/mainboard/google/brox/variants/baseboard/brox/gpio.c
1 file changed, 1 insertion(+), 1 deletion(-)
Approvals:
build bot (Jenkins): Verified
Karthik Ramasubramanian: Looks good to me, approved
Ashish Kumar Mishra: Looks good to me, but someone else must approve
diff --git a/src/mainboard/google/brox/variants/baseboard/brox/gpio.c b/src/mainboard/google/brox/variants/baseboard/brox/gpio.c
index 1464820..337fde1 100644
--- a/src/mainboard/google/brox/variants/baseboard/brox/gpio.c
+++ b/src/mainboard/google/brox/variants/baseboard/brox/gpio.c
@@ -140,7 +140,7 @@
PAD_NC(GPP_C7, NONE),
/* GPP_D0 : [NF1: ISH_GP0 NF2: BK0 NF5: SBK0 NF6: USB_C_GPP_D0] ==> PCH_EC_PCH_INT_ODL */
- PAD_CFG_GPI_INT_SWAPPED(GPP_D0, NONE, PLTRST, LEVEL),
+ PAD_CFG_GPI_APIC_LOW(GPP_D0, NONE, PLTRST),
/* GPP_D1 : [NF1: ISH_GP1 NF2: BK1 NF5: SBK1 NF6: USB_C_GPP_D1] ==> PCH_EC_PCH_WAKE_ODL */
PAD_CFG_GPI_IRQ_WAKE(GPP_D1, NONE, DEEP, EDGE_SINGLE, INVERT),
/* GPP_D2 : [NF1: ISH_GP2 NF2: BK2 NF5: SBK2 NF6: USB_C_GPP_D2] ==> ISH_ACCEL_DB_INT_L (NC) */
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Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79919?usp=email )
Change subject: soc/intel/jasperlake: Drop redundant PcieRpEnable
......................................................................
Patch Set 4: Code-Review+2
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Change subject: soc/intel/tigerlake: Drop redundant PcieRpEnable
......................................................................
Patch Set 5: Code-Review+2
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Change subject: soc/intel/mtl: Skip RW CBFS ucode update if RO is locked
......................................................................
Patch Set 1: Code-Review+2
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/80567/comment/af16a41a_6c9ad479 :
PS1, Line 16: 3. The kernel can still load microcode updates without affecting
: AP FW boot time.
:
> > How is the kernel faster than coreboot at loading microcode? Isn't this just moving the process of updating the microcode update to a later stage?
>
> you got it correct, there is nothing like kernel is faster than coreboot. we see two reasons to support this migration
>
> - microcode part of the RW CBFS is mostly for patching ucode hot fixes for production device which can be any way loaded by OS. Hence, it just moving the responsibility to OS as there is not much value of doing ucode loading from RW CBFS during boot. May be another 500ms later (by kernel) than what coreboot is doing today.
>
> - any attempt to update ucode part of RW CBFS requires firmware qualification by OEM and pushing the FW update for the device, which is costly (and FW update is not that frequent compared to the OS update). hence, atleast for the chromeos device, we don't push any ucode update for in-field device using AP FW rather we perfer to patch those using linux-firmware.
>
> In short, this commit msg line is just conveying that, any attempt to load ucode update by kernel doesn't impact AP FW aka BIOS boot time which we are measuring using `cbmem -t` and <1sec is critical goal for us to meet this KPI.
>
> I hope it explains the motivation behind pushing this CL.
Thanks for explaining! I do get the argument to have the kernel do it as it's easier to update than the firmware. The boottime argument is a bit misleading: it needs to be done, whether by the kernel or by the firmware: it's just moving where it's done. Now things are ofc different if kernel has a newer version (as it gets updated more frequently you say), then this makes total sense as then both coreboot and kernel would be doing the same thing.
Maybe add the OS/FW situation to the commit message?
Patchset:
PS1:
Is there something specific about mtl for this or does it make sense on more platforms?
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Change subject: riscv/mb/qemu: fix qemu invocation comment
......................................................................
Patch Set 12: Code-Review+2
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Hello Kapil Porwal, Nick Vaccaro, Subrata Banik, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: mb/intel/adlrvp: Include ADL-N ID 5
......................................................................
mb/intel/adlrvp: Include ADL-N ID 5
This patch adds support for using ADL N 4-core MCH ID 0x4618.
Signed-off-by: Sean Rhodes <sean(a)starlabs.systems>
Change-Id: I7b9fc64ccf8e2401dcd55607e8f09b348efb3182
---
M src/soc/intel/alderlake/vr_config.c
1 file changed, 2 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/80166/8
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Hello Kapil Porwal, Nick Vaccaro, Subrata Banik, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: soc/intel/alderlake: Include ADL-N ID 5 0x4618
......................................................................
soc/intel/alderlake: Include ADL-N ID 5 0x4618
This patch adds support for using ADL N 4-core MCH ID 0x4618.
Signed-off-by: Sean Rhodes <sean(a)starlabs.systems>
Change-Id: I3e4855ce93666c54ab35def9b58e4b13bc9a8672
---
M src/mainboard/intel/adlrvp/ramstage.c
M src/soc/intel/alderlake/bootblock/report_platform.c
M src/soc/intel/alderlake/chip.h
M src/soc/intel/alderlake/cpu.c
M src/soc/intel/alderlake/fsp_params.c
M src/soc/intel/alderlake/vr_config.c
6 files changed, 7 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/80488/3
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Change subject: soc/intel/common: Add ADL_N ID 5 0x4618
......................................................................
soc/intel/common: Add ADL_N ID 5 0x4618
This patch adds ADL N 4-core MCH ID 0x4618.
Signed-off-by: Sean Rhodes <sean(a)starlabs.systems>
Change-Id: I47bd8fa991a48d30be4975b7965f2c3c859836dd
---
M src/include/device/pci_ids.h
M src/soc/intel/common/block/systemagent/systemagent.c
2 files changed, 2 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/80487/2
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Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: I47bd8fa991a48d30be4975b7965f2c3c859836dd
Gerrit-Change-Number: 80487
Gerrit-PatchSet: 2
Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-MessageType: newpatchset