coreboot-gerrit December 2024

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[S] Change in coreboot[main]: drivers/uart: Replace 'unsigned long int' by 'unsigned long'
by Ariel Otilibili (Code Review) 27 Dec '24

27 Dec '24

Ariel Otilibili has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85784?usp=email ) Change subject: drivers/uart: Replace 'unsigned long int' by 'unsigned long' ...................................................................... drivers/uart: Replace 'unsigned long int' by 'unsigned long' As suggested by the linter: Prefer 'unsigned long' over 'unsigned long int' as the int is unnecessary Link: https://qa.coreboot.org/job/coreboot-untested-files/lastSuccessfulBuild/art… Change-Id: I1416a2f7d75a888dcaf0775894aced981800866f Signed-off-by: Ariel Otilibili <otilibil(a)eurecom.fr> --- M src/drivers/uart/uart8250io.c M src/drivers/uart/uart8250mem.c 2 files changed, 6 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/85784/1 diff --git a/src/drivers/uart/uart8250io.c b/src/drivers/uart/uart8250io.c index a7fc346..89ec229 100644 --- a/src/drivers/uart/uart8250io.c +++ b/src/drivers/uart/uart8250io.c @@ -26,14 +26,14 @@ static void uart8250_tx_byte(unsigned int base_port, unsigned char data) { - unsigned long int i = SINGLE_CHAR_TIMEOUT; + unsigned long i = SINGLE_CHAR_TIMEOUT; while (i-- && !uart8250_can_tx_byte(base_port)); outb(data, base_port + UART8250_TBR); } static void uart8250_tx_flush(unsigned int base_port) { - unsigned long int i = FIFO_TIMEOUT; + unsigned long i = FIFO_TIMEOUT; while (i-- && !(inb(base_port + UART8250_LSR) & UART8250_LSR_TEMT)); } @@ -44,7 +44,7 @@ static unsigned char uart8250_rx_byte(unsigned int base_port) { - unsigned long int i = SINGLE_CHAR_TIMEOUT; + unsigned long i = SINGLE_CHAR_TIMEOUT; while (i && !uart8250_can_rx_byte(base_port)) i--; diff --git a/src/drivers/uart/uart8250mem.c b/src/drivers/uart/uart8250mem.c index 19677a8..fcf031e 100644 --- a/src/drivers/uart/uart8250mem.c +++ b/src/drivers/uart/uart8250mem.c @@ -46,7 +46,7 @@ static void uart8250_mem_tx_byte(void *base, unsigned char data) { - unsigned long int i = SINGLE_CHAR_TIMEOUT; + unsigned long i = SINGLE_CHAR_TIMEOUT; while (i-- && !uart8250_mem_can_tx_byte(base)) udelay(1); uart8250_write(base, UART8250_TBR, data); @@ -54,7 +54,7 @@ static void uart8250_mem_tx_flush(void *base) { - unsigned long int i = FIFO_TIMEOUT; + unsigned long i = FIFO_TIMEOUT; while (i-- && !(uart8250_read(base, UART8250_LSR) & UART8250_LSR_TEMT)) udelay(1); } @@ -66,7 +66,7 @@ static unsigned char uart8250_mem_rx_byte(void *base) { - unsigned long int i = SINGLE_CHAR_TIMEOUT; + unsigned long i = SINGLE_CHAR_TIMEOUT; while (i && !uart8250_mem_can_rx_byte(base)) { udelay(1); i--; -- To view, visit https://review.coreboot.org/c/coreboot/+/85784?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1416a2f7d75a888dcaf0775894aced981800866f Gerrit-Change-Number: 85784 Gerrit-PatchSet: 1 Gerrit-Owner: Ariel Otilibili

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[XS] Change in coreboot[main]: intel/fsp1_1: Replace 'unsigned long int' by 'unsigned long'
by Ariel Otilibili (Code Review) 27 Dec '24

27 Dec '24

Ariel Otilibili has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85783?usp=email ) Change subject: intel/fsp1_1: Replace 'unsigned long int' by 'unsigned long' ...................................................................... intel/fsp1_1: Replace 'unsigned long int' by 'unsigned long' As suggested by the linter: Prefer 'unsigned long' over 'unsigned long int' as the int is unnecessary Link: https://qa.coreboot.org/job/coreboot-untested-files/lastSuccessfulBuild/art… Huang Jin <huang.jin(a)intel.com> Intel_Coreboot_Reviewers <intel_coreboot_reviewers(a)intel.com> Change-Id: I940528dc4f8cb9b2d441d0f0d181cccebd315255 Signed-off-by: Ariel Otilibili <otilibil(a)eurecom.fr> --- M src/drivers/intel/fsp1_1/raminit.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/85783/1 diff --git a/src/drivers/intel/fsp1_1/raminit.c b/src/drivers/intel/fsp1_1/raminit.c index 247df04..da71dd7 100644 --- a/src/drivers/intel/fsp1_1/raminit.c +++ b/src/drivers/intel/fsp1_1/raminit.c @@ -127,7 +127,7 @@ } else { fsp_reserved_bytes = fsp_memory->ResourceLength; printk(BIOS_DEBUG, "Reserving 0x%016lx bytes for FSP\n", - (unsigned long int)fsp_reserved_bytes); + (unsigned long)fsp_reserved_bytes); } /* Display SMM area */ -- To view, visit https://review.coreboot.org/c/coreboot/+/85783?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I940528dc4f8cb9b2d441d0f0d181cccebd315255 Gerrit-Change-Number: 85783 Gerrit-PatchSet: 1 Gerrit-Owner: Ariel Otilibili

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[XS] Change in coreboot[main]: arch/x86: Replace 'unsigned long int' by 'unsigned long'
by Ariel Otilibili (Code Review) 27 Dec '24

27 Dec '24

Ariel Otilibili has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85782?usp=email ) Change subject: arch/x86: Replace 'unsigned long int' by 'unsigned long' ...................................................................... arch/x86: Replace 'unsigned long int' by 'unsigned long' As suggested by the linter: Prefer 'unsigned long' over 'unsigned long int' as the int is unnecessary Link: https://qa.coreboot.org/job/coreboot-untested-files/lastSuccessfulBuild/art… Cc: "Jérémy Compostella" <jeremy.compostella(a)intel.com> Change-Id: Ida1de23830b0b67ab7fac635b02a4e99c65746f8 Signed-off-by: Ariel Otilibili <otilibil(a)eurecom.fr> --- M src/arch/x86/memset.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/85782/1 diff --git a/src/arch/x86/memset.c b/src/arch/x86/memset.c index 142dda3..4ab07ed 100644 --- a/src/arch/x86/memset.c +++ b/src/arch/x86/memset.c @@ -12,7 +12,7 @@ void *memset(void *dstpp, int c, size_t len) { int d0; - unsigned long int dstp = (unsigned long int)dstpp; + unsigned long dstp = (unsigned long)dstpp; #if (ENV_SEPARATE_ROMSTAGE && CONFIG(ASAN_IN_ROMSTAGE)) || \ (ENV_RAMSTAGE && CONFIG(ASAN_IN_RAMSTAGE)) -- To view, visit https://review.coreboot.org/c/coreboot/+/85782?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ida1de23830b0b67ab7fac635b02a4e99c65746f8 Gerrit-Change-Number: 85782 Gerrit-PatchSet: 1 Gerrit-Owner: Ariel Otilibili Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com>

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[S] Change in coreboot[main]: Fix up CFR's open issues
by Lean Sheng Tan (Code Review) 27 Dec '24

27 Dec '24

Attention is currently required from: Angel Pons, Felix Held, Werner Zeh. Lean Sheng Tan has posted comments on this change by Lean Sheng Tan. ( https://review.coreboot.org/c/coreboot/+/85780?usp=email ) Change subject: Fix up CFR's open issues ...................................................................... Patch Set 4: (2 comments) File src/drivers/option/cfr.c: https://review.coreboot.org/c/coreboot/+/85780/comment/c7bea721_6276dce1?us… : PS3, Line 32: char *data; > Remove this line Done https://review.coreboot.org/c/coreboot/+/85780/comment/88fdacee_1d665929?us… : PS3, Line 42: *data = current + sizeof(*cfr_str); > ```suggestion […] Fix applied. -- To view, visit https://review.coreboot.org/c/coreboot/+/85780?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id66808382b93e32c58024462c18b20c2a89d6d23 Gerrit-Change-Number: 85780 Gerrit-PatchSet: 4 Gerrit-Owner: Lean Sheng Tan <tanleansheng(a)outlook.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 26 Dec 2024 23:35:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com>

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[XS] Change in coreboot[main]: mb/google/rauru: Initialize SPM
by Yidi Lin (Code Review) 27 Dec '24

27 Dec '24

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yu-Ping Wu. Yidi Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85777?usp=email ) Change subject: mb/google/rauru: Initialize SPM ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85777?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idfa08a8aa44838e84bc69e2b717254a281796bf0 Gerrit-Change-Number: 85777 Gerrit-PatchSet: 1 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Thu, 26 Dec 2024 23:27:22 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: Fix up CFR's open issues
by Angel Pons (Code Review) 27 Dec '24

27 Dec '24

Attention is currently required from: Felix Held, Lean Sheng Tan, Werner Zeh. Angel Pons has posted comments on this change by Lean Sheng Tan. ( https://review.coreboot.org/c/coreboot/+/85780?usp=email ) Change subject: Fix up CFR's open issues ...................................................................... Patch Set 3: (2 comments) File src/drivers/option/cfr.c: https://review.coreboot.org/c/coreboot/+/85780/comment/38030de5_8892011e?us… : PS3, Line 32: char *data; Remove this line https://review.coreboot.org/c/coreboot/+/85780/comment/5887503f_0e5788eb?us… : PS3, Line 42: *data = current + sizeof(*cfr_str); ```suggestion char *data = current + sizeof(*cfr_str); ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/85780?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id66808382b93e32c58024462c18b20c2a89d6d23 Gerrit-Change-Number: 85780 Gerrit-PatchSet: 3 Gerrit-Owner: Lean Sheng Tan <tanleansheng(a)outlook.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lean Sheng Tan <tanleansheng(a)outlook.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 26 Dec 2024 23:18:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: soc/intel/pantherlake: Update the Thunderbolt lcap_port_base to 0x15
by Jérémy Compostella (Code Review) 26 Dec '24

26 Dec '24

Jérémy Compostella has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85781?usp=email ) Change subject: soc/intel/pantherlake: Update the Thunderbolt lcap_port_base to 0x15 ...................................................................... soc/intel/pantherlake: Update the Thunderbolt lcap_port_base to 0x15 On Panther Lake, the Thunderbolt port index exposed by the LCAP registers now begins at 0x15. The previous offset of 0x10 caused an issue that resulted in: - Temporary deactivation of Thunderbolt PCI devices during ramstage - Failure to generate critical ACPI SSDT power management data for the port This error led to instability in PCIe tunneling during power state transitions. Change-Id: I44f91f954a4ec06c56dcc90d97e7da2193e9acf2 Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> --- M src/soc/intel/pantherlake/pcie_rp.c 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/85781/1 diff --git a/src/soc/intel/pantherlake/pcie_rp.c b/src/soc/intel/pantherlake/pcie_rp.c index 1b302fd..7c51601 100644 --- a/src/soc/intel/pantherlake/pcie_rp.c +++ b/src/soc/intel/pantherlake/pcie_rp.c @@ -5,13 +5,13 @@ #include <soc/pcie.h> /* - * TBT's LCAP registers are returning port index which starts from 0x10 (Usually for other PCIe - * root ports index starts from 1). Thus keeping lcap_port_base 0x10 for TBT, so that coreboot's + * TBT's LCAP registers are returning port index which starts from 0x15 (Usually for other PCIe + * root ports index starts from 1). Thus keeping lcap_port_base 0x15 for TBT, so that coreboot's * PCIe remapping logic can return correct index (0-based) */ static const struct pcie_rp_group tbt_rp_groups[] = { - { .slot = PCI_DEV_SLOT_TBT, .count = CONFIG_MAX_TBT_ROOT_PORTS, .lcap_port_base = 0x10 }, + { .slot = PCI_DEV_SLOT_TBT, .count = CONFIG_MAX_TBT_ROOT_PORTS, .lcap_port_base = 0x15 }, { 0 } }; -- To view, visit https://review.coreboot.org/c/coreboot/+/85781?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I44f91f954a4ec06c56dcc90d97e7da2193e9acf2 Gerrit-Change-Number: 85781 Gerrit-PatchSet: 1 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com>

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[XL] Change in coreboot[main]: drivers/option: Add forms in cbtables
by Lean Sheng Tan (Code Review) 26 Dec '24

26 Dec '24

Attention is currently required from: Angel Pons. Lean Sheng Tan has posted comments on this change by Angel Pons. ( https://review.coreboot.org/c/coreboot/+/74121?usp=email ) Change subject: drivers/option: Add forms in cbtables ...................................................................... Patch Set 30: (5 comments) File Documentation/drivers/cfr.md: https://review.coreboot.org/c/coreboot/+/74121/comment/717cedcf_bddee4e2?us… : PS29, Line 211: CFR_OPTFLAG_GRAYOUT > to me CFR_OPTFLAG_INACTIVE also sounds better than CFR_OPTFLAG_GRAYOUT Done here: https://review.coreboot.org/c/coreboot/+/85780 File Documentation/drivers/cfr.md: https://review.coreboot.org/c/coreboot/+/74121/comment/8fe764e7_c163f03e?us… : PS30, Line 1: form representation > hmm, didn't we agree in a meeting that we wanted to get rid of this uefi terminology here which is a […] I think no one bothers to follow up or make new decision, so we decided to get the V1 in with this status quo, if someone wants to change it in future feels free to ;) https://review.coreboot.org/c/coreboot/+/74121/comment/635d5663_0790b505?us… : PS30, Line 29: ore > or https://review.coreboot.org/c/coreboot/+/85780 https://review.coreboot.org/c/coreboot/+/74121/comment/6b917595_b6fb6baf?us… : PS30, Line 69: immideatly > immediately https://review.coreboot.org/c/coreboot/+/85780 https://review.coreboot.org/c/coreboot/+/74121/comment/c3eed0fe_9f7c8eea?us… : PS30, Line 72: > the doc would be slightly easier to read if all tags were first defined and then used. […] Sorry I dont get it, what do you mean actually? -- To view, visit https://review.coreboot.org/c/coreboot/+/74121?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I304de7d26d79245a2e31a6d01f6c5643b31cb772 Gerrit-Change-Number: 74121 Gerrit-PatchSet: 30 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <tanleansheng(a)outlook.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Daniel Maslowski <info(a)orangecms.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Thu, 26 Dec 2024 21:33:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Werner Zeh <werner.zeh(a)siemens.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de>

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[S] Change in coreboot[main]: mb/prodrive/atlas: Remove the workaround for CLKREQ pins
by Lean Sheng Tan (Code Review) 26 Dec '24

26 Dec '24

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79021?usp=email ) ( 3 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/prodrive/atlas: Remove the workaround for CLKREQ pins ...................................................................... mb/prodrive/atlas: Remove the workaround for CLKREQ pins As Intel has provided fixes regarding CLKREQ pins issue with new UPD settings as described in commit b8abde7a8ef4 ("soc/intel/alderlake: Disable PCIe clock gating"), remove this WA as introduced by this commit 586b1c8da06f ("mb/prodrive/atlas: Add workaround for CLKREQ pins"). Signed-off-by: Lean Sheng Tan <sheng.tan(a)9elements.com> Change-Id: Icbab617428551accda66499b7c2a32b2fa8c1689 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79021 Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/prodrive/atlas/romstage_fsp_params.c 1 file changed, 0 insertions(+), 26 deletions(-) Approvals: Matt DeVillier: Looks good to me, approved build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve diff --git a/src/mainboard/prodrive/atlas/romstage_fsp_params.c b/src/mainboard/prodrive/atlas/romstage_fsp_params.c index ab47dd0..7d3d9b5 100644 --- a/src/mainboard/prodrive/atlas/romstage_fsp_params.c +++ b/src/mainboard/prodrive/atlas/romstage_fsp_params.c @@ -72,30 +72,4 @@ mcfg->CpuPcieRpClockReqMsgEnable[0] = 0; mcfg->CpuPcieRpClockReqMsgEnable[1] = 0; mcfg->CpuPcieRpClockReqMsgEnable[2] = 0; - - // shared clock - mcfg->PcieClkSrcUsage[0] = 0x80; - mcfg->PcieClkSrcClkReq[0] = 0xFF; - // i225 - mcfg->PcieClkSrcUsage[1] = 9; // RP 10 - mcfg->PcieClkSrcClkReq[1] = 1; - - // FIX Apparently Rootports don't like the idea of not having a clksrc and clkreq - // attached to it. For example if we set PcieClkSrcClkReq[1] above to 0xFF (unused) - // it will not come back out of L1. You can easily test this on windows by trying to - // update the i225 driver in device manager or use setpci in Linux to set Device in D3. - // The same applies to all other rootports no matter which devices are connected to it. - // Therefore we put each rootport (that does not have a clkreq, clksrc) - // to a not connected (not routed out) clksrc and clkreq. That seems to be a current FSP Bug. - // workaround and will be removed as soon as FSP is fixed. - mcfg->PcieClkSrcUsage[2] = 4; // Rootport 5 - mcfg->PcieClkSrcClkReq[2] = 0; - mcfg->PcieClkSrcUsage[3] = 5; // Rootport 6 - mcfg->PcieClkSrcClkReq[3] = 0; - mcfg->PcieClkSrcUsage[4] = 8; // Rootport 9 - mcfg->PcieClkSrcClkReq[4] = 0; - mcfg->PcieClkSrcUsage[5] = 6; // Rootport 7 - mcfg->PcieClkSrcClkReq[5] = 0; - mcfg->PcieClkSrcUsage[6] = 7; // Rootport 8 - mcfg->PcieClkSrcClkReq[6] = 0; } -- To view, visit https://review.coreboot.org/c/coreboot/+/79021?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icbab617428551accda66499b7c2a32b2fa8c1689 Gerrit-Change-Number: 79021 Gerrit-PatchSet: 5 Gerrit-Owner: Lean Sheng Tan <tanleansheng(a)outlook.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Lean Sheng Tan <tanleansheng(a)outlook.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[L] Change in coreboot[main]: util/intelp2m: Move remapping reset source to common
by Maxim Polyakov (Code Review) 26 Dec '24

26 Dec '24

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85731?usp=email to look at the new patch set (#7). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: util/intelp2m: Move remapping reset source to common ...................................................................... util/intelp2m: Move remapping reset source to common TEST: 'make test' = PASS Change-Id: I315541b12f5f1fdf7c97c2ff8ddd305e30a447cc Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M util/intelp2m/platforms/adl/macro.go M util/intelp2m/platforms/apl/macro.go M util/intelp2m/platforms/cnl/macro.go M util/intelp2m/platforms/common/common.go M util/intelp2m/platforms/common/macro.go M util/intelp2m/platforms/ebg/macro.go M util/intelp2m/platforms/jsl/macro.go M util/intelp2m/platforms/lbg/macro.go M util/intelp2m/platforms/mtl/macro.go M util/intelp2m/platforms/snr/macro.go M util/intelp2m/platforms/tgl/macro.go 11 files changed, 107 insertions(+), 147 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/85731/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/85731?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I315541b12f5f1fdf7c97c2ff8ddd305e30a447cc Gerrit-Change-Number: 85731 Gerrit-PatchSet: 7 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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2013

coreboot-gerrit December 2024