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Change subject: drivers/intel/fsp2_0: Add FSP-I and FSP-O
......................................................................
Patch Set 3: Code-Review+1
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83113/comment/66ff714c_2d34c5e8?us… :
PS3, Line 7: drivers/intel/fsp2_0: Add FSP-I and FSP-O
> drivers/intel/fsp2_0: Add FSP-I and FSP-O defines
https://review.coreboot.org/c/coreboot/+/83113/comment/a56e3db9_1353a7a9?us… :
PS3, Line 11:
Do we have a description for FSP-I?
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Change subject: Fix up CFR's open issues
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Patch Set 4:
(1 comment)
File src/drivers/option/cfr.c:
https://review.coreboot.org/c/coreboot/+/85780/comment/0545d4c3_b0cf3be4?us… :
PS4, Line 32: size_t padding;
Yeet
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Change subject: mb/prodrive/atlas: Add initial support for options
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Patch Set 28: Code-Review+1
(6 comments)
File src/mainboard/prodrive/atlas/Kconfig:
https://review.coreboot.org/c/coreboot/+/74122/comment/2d53df62_e59b2626?us… :
PS28, Line 16: select DRIVERS_OPTION_CFR_ENABLED
Does this mean "CFR force-enabled" or "CFR enabled by default"?
File src/mainboard/prodrive/atlas/cfr.c:
https://review.coreboot.org/c/coreboot/+/74122/comment/cbba2f82_5f89c1f7?us… :
PS28, Line 15: const struct sm_object *obj, struct sm_object *new
Is `obj` ever used?
https://review.coreboot.org/c/coreboot/+/74122/comment/94c36948_42819530?us… :
PS28, Line 27: new->sm_enum.default_value = false;
enum default value is an unsigned integer, IIRC
```suggestion
new->sm_enum.default_value = 0;
```
https://review.coreboot.org/c/coreboot/+/74122/comment/27b42e93_8bb439b6?us… :
PS28, Line 219: (const struct sm_object *[])
I wonder if casting is necessary
https://review.coreboot.org/c/coreboot/+/74122/comment/296ba380_ab95dc49?us… :
PS28, Line 247: &cpu,
: &main,
Should we reverse these so that Main is the first options page?
https://review.coreboot.org/c/coreboot/+/74122/comment/d89912b2_0b432604?us… :
PS28, Line 252: /*
: * TODO: Writing this by hand is extremely tedious. Introducing a DSL
: * (Domain-Specific Language) to describe options which is translated
: * into code at build time may be the way to go. Maybe expand SCONFIG
: * so that these can be devicetree options?
: */
Ah yes, I see this is still quite true
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Change subject: arch/x86/mmu: Port armv8 MMU to x86_64
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Patch Set 11: Code-Review+2
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Change subject: Fix up CFR's open issues
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Patch Set 4: Code-Review+1
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Change subject: arch/x86/mmu: Port armv8 MMU to x86_64
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Patch Set 11:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/79161/comment/bfdb3087_17973486?us… :
PS11, Line 16: DRAM and MMIO even beyond 4GiB.
> > Can we maybe expand the pt1G. […]
On SPR I need to access a BAR in high MMIO at `0x200ffff90000`. That would increase pt1G.S by factor 64 at least.
By mapping the whole address space ramstage size increases to 2501728 bytes. Not sure if it would fit into the stage cache, but since ACPI S3 isn't supported this is probably not a problem.
Having page tables in CBMEM would keep ramstage size and it should still fit into the stage cache or (as suggested) using BSS and generate the page tables at runtime.
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Change subject: util/cbfstool: Replace 'unsigned long int' by 'unsigned long'
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
Helllo @shuo.liu@intel.com; thanks for having looked at the patch. Let me know if there is any feedback.
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