coreboot-gerrit December 2024

coreboot-gerrit@coreboot.org

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[XS] Change in coreboot[main]: soc/mediatek/mt8196: Add audio base address definition
by Jarried Lin (Code Review) 02 Dec '24

02 Dec '24

Attention is currently required from: Darren Ye, Hung-Te Lin, Paul Menzel. Jarried Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85361?usp=email ) Change subject: soc/mediatek/mt8196: Add audio base address definition ...................................................................... Patch Set 6: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/85361/comment/79e7437b_4cc2130b?us… : PS5, Line 7: meidatek > me*di*atek Done -- To view, visit https://review.coreboot.org/c/coreboot/+/85361?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I07d272fddfe50e73adc6f4c7d401f3391b0c145d Gerrit-Change-Number: 85361 Gerrit-PatchSet: 6 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Darren Ye <darren.ye(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Darren Ye <darren.ye(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Mon, 02 Dec 2024 08:21:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

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[M] Change in coreboot[main]: mb/google/rauru: Add 2nd source TAS2563 amps to support beep
by Jarried Lin (Code Review) 02 Dec '24

02 Dec '24

Attention is currently required from: Hung-Te Lin, Paul Menzel, Yidi Lin, Yu-Ping Wu. Jarried Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85360?usp=email ) Change subject: mb/google/rauru: Add 2nd source TAS2563 amps to support beep ...................................................................... Patch Set 6: (1 comment) File src/mainboard/google/rauru/mainboard.c: https://review.coreboot.org/c/coreboot/+/85360/comment/c2a917bf_1a18bcb4?us… : PS5, Line 6: #include <gpio.h> > `soc/addressmap.h` is missing. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/85360?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I10cba7964d3847f2a74341b3130ff1e7bfd8d37a Gerrit-Change-Number: 85360 Gerrit-PatchSet: 6 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Darren Ye <darren.ye(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Mon, 02 Dec 2024 08:20:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com>

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[XS] Change in coreboot[main]: soc/mediatek/mt8196: Add audio base address definition
by Jarried Lin (Code Review) 02 Dec '24

02 Dec '24

Attention is currently required from: Darren Ye, Hung-Te Lin, Jarried Lin. Hello Darren Ye, Hung-Te Lin, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85361?usp=email to look at the new patch set (#6). Change subject: soc/mediatek/mt8196: Add audio base address definition ...................................................................... soc/mediatek/mt8196: Add audio base address definition Add audio base address definition. TEST=build pass BUG=b:357969183 Change-Id: I07d272fddfe50e73adc6f4c7d401f3391b0c145d Signed-off-by: Darren Ye <darren.ye(a)mediatek.corp-partner.google.com> --- M src/soc/mediatek/mt8196/include/soc/addressmap.h 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/85361/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/85361?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I07d272fddfe50e73adc6f4c7d401f3391b0c145d Gerrit-Change-Number: 85361 Gerrit-PatchSet: 6 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Darren Ye <darren.ye(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Darren Ye <darren.ye(a)mediatek.corp-partner.google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com>

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[M] Change in coreboot[main]: mb/google/rauru: Add 2nd source TAS2563 amps to support beep
by Jarried Lin (Code Review) 02 Dec '24

02 Dec '24

Attention is currently required from: Hung-Te Lin, Jarried Lin, Paul Menzel, Yu-Ping Wu. Hello Darren Ye, Hung-Te Lin, Paul Menzel, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85360?usp=email to look at the new patch set (#6). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mb/google/rauru: Add 2nd source TAS2563 amps to support beep ...................................................................... mb/google/rauru: Add 2nd source TAS2563 amps to support beep Derive the audio amplifier from FW_CONFIG, and set up I2C and I2S for TAS2563. Also pass the corresponding GPIO(s) to the payload. TEST=build pass and driver init ok BUG=b:357969183 Change-Id: I10cba7964d3847f2a74341b3130ff1e7bfd8d37a Signed-off-by: Darren Ye <darren.ye(a)mediatek.corp-partner.google.com> --- M src/mainboard/google/rauru/chromeos.c M src/mainboard/google/rauru/devicetree.cb M src/mainboard/google/rauru/gpio.h M src/mainboard/google/rauru/mainboard.c 4 files changed, 54 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/85360/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/85360?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I10cba7964d3847f2a74341b3130ff1e7bfd8d37a Gerrit-Change-Number: 85360 Gerrit-PatchSet: 6 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Darren Ye <darren.ye(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com>

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[M] Change in coreboot[main]: soc/mediatek/mt8196: Add booker driver
by Yu-Ping Wu (Code Review) 02 Dec '24

02 Dec '24

Attention is currently required from: Dehui Sun, Hung-Te Lin, Jarried Lin. Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85362?usp=email ) Change subject: soc/mediatek/mt8196: Add booker driver ...................................................................... Patch Set 5: (2 comments) File src/soc/mediatek/mt8196/booker.c: https://review.coreboot.org/c/coreboot/+/85362/comment/22566422_76d44d72?us… : PS5, Line 56: __func__ Align with BIOS_DEBUG. File src/soc/mediatek/mt8196/include/soc/booker.h: https://review.coreboot.org/c/coreboot/+/85362/comment/1fbd8b2f_bdf4c0ca?us… : PS5, Line 6: extern remove -- To view, visit https://review.coreboot.org/c/coreboot/+/85362?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6bde1e20137890addf18b23b47f17b1f63824b22 Gerrit-Change-Number: 85362 Gerrit-PatchSet: 5 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Dehui Sun <dehui.sun(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Dehui Sun <dehui.sun(a)mediatek.corp-partner.google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Mon, 02 Dec 2024 08:19:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: soc/mediatek/mt8195: Fix SCP register address
by Yu-Ping Wu (Code Review) 02 Dec '24

02 Dec '24

Yu-Ping Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85436?usp=email ) Change subject: soc/mediatek/mt8195: Fix SCP register address ...................................................................... soc/mediatek/mt8195: Fix SCP register address The parentheses are missing in the mtk_scp macro definition. The only usage is SET32_BITFIELDS(&mtk_scp->scp_clk_on_ctrl, SCP_CLK_ON_CTRL, 1); I guess that bit is already set by default, so there's no ULPOSC clock issue found so far. BUG=none TEST=none BRANCH=cherry Change-Id: I2dbb5c465ee60f0c4dce8ff77b8d3a39db42e4f5 Signed-off-by: Yu-Ping Wu <yupingso(a)chromium.org> --- M src/soc/mediatek/mt8195/include/soc/pmif.h 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/85436/1 diff --git a/src/soc/mediatek/mt8195/include/soc/pmif.h b/src/soc/mediatek/mt8195/include/soc/pmif.h index cec23d7..530b31e 100644 --- a/src/soc/mediatek/mt8195/include/soc/pmif.h +++ b/src/soc/mediatek/mt8195/include/soc/pmif.h @@ -134,7 +134,7 @@ check_member(mtk_scp_regs, scp_clk_on_ctrl, 0x6C); -#define mtk_scp ((struct mtk_scp_regs *)SCP_CFG_BASE + 0x21000) +#define mtk_scp ((struct mtk_scp_regs *)(SCP_CFG_BASE + 0x21000)) enum { PMIF_TARGET_FREQ_MHZ = 248, -- To view, visit https://review.coreboot.org/c/coreboot/+/85436?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2dbb5c465ee60f0c4dce8ff77b8d3a39db42e4f5 Gerrit-Change-Number: 85436 Gerrit-PatchSet: 1 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com>

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[XS] Change in coreboot[main]: drivers/usb/intel_bluetooth: Fix GBTE return value
by Paul Menzel (Code Review) 02 Dec '24

02 Dec '24

Attention is currently required from: Sean Rhodes. Paul Menzel has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/84989?usp=email ) Change subject: drivers/usb/intel_bluetooth: Fix GBTE return value ...................................................................... Patch Set 1: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/84989/comment/64aca3d3_5f071b0f?us… : PS1, Line 7: Fix GBTE return value Maybe extend: > … to use LOCAL0 https://review.coreboot.org/c/coreboot/+/84989/comment/7b99b53d_67c85fdc?us… : PS1, Line 11: Add the value before and after, and describe, if something starts working now? -- To view, visit https://review.coreboot.org/c/coreboot/+/84989?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I13263d479d1a4520abaf1b6b38514d021e7d4dc9 Gerrit-Change-Number: 84989 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Mon, 02 Dec 2024 08:14:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: soc/intel/xeon_sp: Remove lpc_lockdown_config
by Jincheng Li (Code Review) 02 Dec '24

02 Dec '24

Attention is currently required from: Christian Walter, Jincheng Li, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Michał Żygowski, Patrick Rudolph, Tim Chu. Hello Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Michał Żygowski, Patrick Rudolph, Shuo Liu, Tim Chu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85286?usp=email to look at the new patch set (#3). Change subject: soc/intel/xeon_sp: Remove lpc_lockdown_config ...................................................................... soc/intel/xeon_sp: Remove lpc_lockdown_config If CHIPSET_LOCKDOWN_COREBOOT is selected, lpc_lockdown_config() will be executed in common pch/lockdown firstly. Remove xeon_sp layer lpc_lockdown_config() to avoid duplication. The duplicated part are in src/soc/intel/common/pch/lockdown/lockdown.c: static void platform_lockdown_config(void *unused) { int chipset_lockdown; chipset_lockdown = get_lockdown_config(); /* SPI lock down configuration */ fast_spi_lockdown_cfg(chipset_lockdown); /* LPC/eSPI lock down configuration */ lpc_lockdown_config(chipset_lockdown); ... } Change-Id: Ibec389a6d55c7885def6896a0ea435514b75a323 Signed-off-by: Jincheng Li <jincheng.li(a)intel.com> --- M src/soc/intel/xeon_sp/lockdown.c 1 file changed, 0 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/85286/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/85286?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibec389a6d55c7885def6896a0ea435514b75a323 Gerrit-Change-Number: 85286 Gerrit-PatchSet: 3 Gerrit-Owner: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com>

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[XS] Change in coreboot[main]: soc/intel/xeon_xp: Fix lower ram range bug
by Paul Menzel (Code Review) 02 Dec '24

02 Dec '24

Attention is currently required from: Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Shuo Liu, Tim Chu, yuchi.chen(a)intel.com. Paul Menzel has posted comments on this change by yuchi.chen(a)intel.com. ( https://review.coreboot.org/c/coreboot/+/85434?usp=email ) Change subject: soc/intel/xeon_xp: Fix lower ram range bug ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/85434/comment/42084935_678ea69b?us… : PS2, Line 7: Fix lower ram range bug Maybe something more specific: > Remove 1 byte loss in lower RAM range (No idea if correct.) -- To view, visit https://review.coreboot.org/c/coreboot/+/85434?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia8147702aad496c431cf10b896d68a826c9e45b1 Gerrit-Change-Number: 85434 Gerrit-PatchSet: 2 Gerrit-Owner: yuchi.chen(a)intel.com Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: yuchi.chen(a)intel.com Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Mon, 02 Dec 2024 08:11:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: soc/meidatek/mt8196: Add audio base address definition
by Paul Menzel (Code Review) 02 Dec '24

02 Dec '24

Attention is currently required from: Darren Ye, Hung-Te Lin, Jarried Lin. Paul Menzel has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85361?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: soc/meidatek/mt8196: Add audio base address definition ...................................................................... Patch Set 5: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/85361/comment/a89fa744_9e3a446c?us… : PS5, Line 7: meidatek me*di*atek -- To view, visit https://review.coreboot.org/c/coreboot/+/85361?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I07d272fddfe50e73adc6f4c7d401f3391b0c145d Gerrit-Change-Number: 85361 Gerrit-PatchSet: 5 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Darren Ye <darren.ye(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Darren Ye <darren.ye(a)mediatek.corp-partner.google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Mon, 02 Dec 2024 08:10:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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coreboot-gerrit December 2024