coreboot-gerrit December 2024

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[S] Change in coreboot[main]: soc/intel/xeon_sp: Remove lpc_lockdown_config
by Patrick Rudolph (Code Review) 02 Dec '24

02 Dec '24

Attention is currently required from: Christian Walter, Jincheng Li, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Michał Żygowski, Tim Chu. Patrick Rudolph has posted comments on this change by Jincheng Li. ( https://review.coreboot.org/c/coreboot/+/85286?usp=email ) Change subject: soc/intel/xeon_sp: Remove lpc_lockdown_config ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85286?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibec389a6d55c7885def6896a0ea435514b75a323 Gerrit-Change-Number: 85286 Gerrit-PatchSet: 3 Gerrit-Owner: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Mon, 02 Dec 2024 12:05:40 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: soc/mediatek/mt8196: Add booker driver
by Jarried Lin (Code Review) 02 Dec '24

02 Dec '24

Attention is currently required from: Dehui Sun, Hung-Te Lin, Paul Menzel, Yidi Lin, Yu-Ping Wu. Jarried Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85362?usp=email ) Change subject: soc/mediatek/mt8196: Add booker driver ...................................................................... Patch Set 7: (7 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/85362/comment/ba7eef29_7f8e3d51?us… : PS1, Line 9: booker == CI-700 : But MTK booker does not fully comply with the CI-700 spec. The booker : only uses CHI protocol, while MTK booker does not support coherence. The : booker also uses other protocols such as AXI, which is to translate CHI : transactions into EMI's AXI transactions. : : Booker = Routing + Coherence + MTE + Debug : Currently, mt8196 booker only uses the functions of Routing&MTE&Debug. : : If downstream SLC needs CMO commands propagation from the DSU, it can : set the disable_cmo_prop = 0 in the por_sbsx_cfg_ctl register. When the : bit is programmed, the CI-700 must be idle. It's better to program it : before transactions go to CI-700. > Yes, I agree with your opinion. […] Done https://review.coreboot.org/c/coreboot/+/85362/comment/e593bd0b_629c78e1?us… : PS1, Line 20: It's better to program it : before transactions go to CI-700. > Okay, I'll make the changes later. […] Done Commit Message: https://review.coreboot.org/c/coreboot/+/85362/comment/c64c1ff5_d7d4d0c6?us… : PS6, Line 23: TEST=build pass > Please paste the new log messages, and please also document a way, how to test if the driver is oper […] Done File src/soc/mediatek/mt8196/booker.c: https://review.coreboot.org/c/coreboot/+/85362/comment/aafe39ac_d5d81a8c?us… : PS1, Line 16: NDE > This can be modified in the next release. […] Done https://review.coreboot.org/c/coreboot/+/85362/comment/53b16872_e0fc8beb?us… : PS1, Line 23: "ldr x0, =0x0a450a00\n" : "ldr x1, [x0]\n" : "ldr x2, =0x8\n" : "bic x1, x1, x2\n" : "str x1, [x0]\n" : : "ldr x0, =0x0ac50a00\n" : "ldr x1, [x0]\n" : "ldr x2, =0x8\n" : "bic x1, x1, x2\n" : "str x1, [x0]\n" : : "ldr x0, =0x0b450a00\n" : "ldr x1, [x0]\n" : "ldr x2, =0x8\n" : "bic x1, x1, x2\n" : "str x1, [x0]\n" : : "ldr x0, =0x0bc50a00\n" : "ldr x1, [x0]\n" : "ldr x2, =0x8\n" : "bic x1, x1, x2\n" : "str x1, [x0]\n" > Okay, it's better to use clrbits32(). Done File src/soc/mediatek/mt8196/booker.c: https://review.coreboot.org/c/coreboot/+/85362/comment/b8e6f700_27462615?us… : PS5, Line 56: __func__ > As a general comment, for each open comment left by reviewers, please either […] OK, we will only respond to comments that disagree with in the future. Thanks. File src/soc/mediatek/mt8196/include/soc/booker.h: https://review.coreboot.org/c/coreboot/+/85362/comment/aac8aa58_ff9333bf?us… : PS5, Line 6: extern > Okay, This can be modified in the next release. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/85362?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6bde1e20137890addf18b23b47f17b1f63824b22 Gerrit-Change-Number: 85362 Gerrit-PatchSet: 7 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Dehui Sun <dehui.sun(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Dehui Sun <dehui.sun(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Mon, 02 Dec 2024 12:05:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Dehui Sun <dehui.sun(a)mediatek.corp-partner.google.com> Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com>

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[S] Change in coreboot[main]: soc/intel/common: Drop locking function fast_spi_set_vcl
by Patrick Rudolph (Code Review) 02 Dec '24

02 Dec '24

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85437?usp=email ) Change subject: soc/intel/common: Drop locking function fast_spi_set_vcl ...................................................................... soc/intel/common: Drop locking function fast_spi_set_vcl Drop function fast_spi_set_vcl as the same code already exists as fast_spi_vscc0_lock() and is already run on xeon_sp. Change-Id: I86180c209e2d550c2bac3ace9cc344eabf950af0 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/intel/common/block/fast_spi/fast_spi.c M src/soc/intel/common/block/include/intelblocks/fast_spi.h M src/soc/intel/xeon_sp/ebg/lockdown.c M src/soc/intel/xeon_sp/ibl/lockdown.c 4 files changed, 0 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/85437/1 diff --git a/src/soc/intel/common/block/fast_spi/fast_spi.c b/src/soc/intel/common/block/fast_spi/fast_spi.c index 0a23e08..4551961 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi.c +++ b/src/soc/intel/common/block/fast_spi/fast_spi.c @@ -464,17 +464,6 @@ pci_or_config32(dev, SPI_BIOS_DECODE_EN, SPI_BIOS_DECODE_LOCK); } -/* Set FAST_SPIBAR + SPIBAR_SFDP0_VSCC0 (0xc4) Vendor Control Lock */ -void fast_spi_set_vcl(void) -{ - void *spibar = fast_spi_get_bar(); - uint32_t vcss; - - vcss = read32(spibar + SPIBAR_SFDP0_VSCC0); - vcss |= SPIBAR_SFDP0_VSCC0_VCL; - write32(spibar + SPIBAR_SFDP0_VSCC0, vcss); -} - void fast_spi_clear_outstanding_status(void) { void *spibar = fast_spi_get_bar(); diff --git a/src/soc/intel/common/block/include/intelblocks/fast_spi.h b/src/soc/intel/common/block/include/intelblocks/fast_spi.h index 46b4f48..716f16a 100644 --- a/src/soc/intel/common/block/include/intelblocks/fast_spi.h +++ b/src/soc/intel/common/block/include/intelblocks/fast_spi.h @@ -107,9 +107,5 @@ * Set FAST_SPIBAR BIOS Decode Lock bit */ void fast_spi_set_bde(void); -/* - * Set FAST_SPIBAR Vendor Component Lock bit. - */ -void fast_spi_set_vcl(void); #endif /* SOC_INTEL_COMMON_BLOCK_FAST_SPI_H */ diff --git a/src/soc/intel/xeon_sp/ebg/lockdown.c b/src/soc/intel/xeon_sp/ebg/lockdown.c index 694e4a2..4ced721 100644 --- a/src/soc/intel/xeon_sp/ebg/lockdown.c +++ b/src/soc/intel/xeon_sp/ebg/lockdown.c @@ -13,6 +13,5 @@ { if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) { fast_spi_set_bde(); - fast_spi_set_vcl(); } } diff --git a/src/soc/intel/xeon_sp/ibl/lockdown.c b/src/soc/intel/xeon_sp/ibl/lockdown.c index 694e4a2..4ced721 100644 --- a/src/soc/intel/xeon_sp/ibl/lockdown.c +++ b/src/soc/intel/xeon_sp/ibl/lockdown.c @@ -13,6 +13,5 @@ { if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) { fast_spi_set_bde(); - fast_spi_set_vcl(); } } -- To view, visit https://review.coreboot.org/c/coreboot/+/85437?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I86180c209e2d550c2bac3ace9cc344eabf950af0 Gerrit-Change-Number: 85437 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com>

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[M] Change in coreboot[main]: soc/mediatek/mt8196: Add booker driver
by Jarried Lin (Code Review) 02 Dec '24

02 Dec '24

Attention is currently required from: Dehui Sun, Hung-Te Lin, Jarried Lin, Yidi Lin. Hello Dehui Sun, Hung-Te Lin, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85362?usp=email to look at the new patch set (#7). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/mediatek/mt8196: Add booker driver ...................................................................... soc/mediatek/mt8196: Add booker driver The MTK booker mainly uses CHI protocol, but does't supports coherence (which is achieved through ACP solution). Additionally, the booker also uses other protocols such as AXI, which translates CHI transactions into EMI's AXI transactions. Currently, the mt8196 booker only uses the functions of SLC CMO Routing. If downstream SLC needs CMO command propagation from the DSU, it can set bit[3] (disable_cmo_prop) to 0 in the por_sbsx_cfg_ctl register of each SBSX node. TEST=build pass, check boot log with: [booker_init] AP hash rule: 0xbe00. BUG=b:317009620 Signed-off-by: Dehui Sun <dehui.sun(a)mediatek.corp-partner.google.com> Change-Id: I6bde1e20137890addf18b23b47f17b1f63824b22 --- M src/soc/mediatek/mt8196/Makefile.mk A src/soc/mediatek/mt8196/booker.c M src/soc/mediatek/mt8196/bootblock.c A src/soc/mediatek/mt8196/include/soc/booker.h 4 files changed, 50 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/85362/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/85362?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6bde1e20137890addf18b23b47f17b1f63824b22 Gerrit-Change-Number: 85362 Gerrit-PatchSet: 7 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Dehui Sun <dehui.sun(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Dehui Sun <dehui.sun(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com>

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[L] Change in coreboot[main]: vc/intel/fsp: Update PTL FSP headers from 2382_01 to 2431.00
by Subrata Banik (Code Review) 02 Dec '24

02 Dec '24

Attention is currently required from: Alok Agarwal, Bora Guvendik, Jérémy Compostella, Ronak Kanabar, Vikrant L Jadeja, srinivas.kulkarni(a)intel.com. Subrata Banik has posted comments on this change by Alok Agarwal. ( https://review.coreboot.org/c/coreboot/+/85149?usp=email ) Change subject: vc/intel/fsp: Update PTL FSP headers from 2382_01 to 2431.00 ...................................................................... Patch Set 8: (1 comment) File src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspmUpd.h: https://review.coreboot.org/c/coreboot/+/85149/comment/e6a33442_bab91ed3?us… : PS7, Line 2387: : /** Offset 0x0976 - VR Fast Vmode ICC Limit support : Voltage Regulator Fast Vmode ICC Limit. A value of 400 = 100A. A value of 0 corresponds : to feature disabled (no reactive protection). This value represents the current : threshold where the VR would initiate reactive protection if Fast Vmode is enabled. : The value is represented in 1/4 A increments. Range 0-2040. [0] for IA, [1] for : GT, [2] for SA, [3] through [5] are Reserved. : **/ : UINT16 IccLimit[6]; > this is hand edited header file IMO because after creating the FSP partial header for FSP 2431.00, I don't see this UPD existed inside FSP partial header I have submitted the original FSP partial header into coreboot -- To view, visit https://review.coreboot.org/c/coreboot/+/85149?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1c1fed8f7ba9d25fdce5bbac3a9687800db33613 Gerrit-Change-Number: 85149 Gerrit-PatchSet: 8 Gerrit-Owner: Alok Agarwal <alok.agarwal(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: srinivas.kulkarni(a)intel.com Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Alok Agarwal <alok.agarwal(a)intel.com> Gerrit-Attention: srinivas.kulkarni(a)intel.com Gerrit-Comment-Date: Mon, 02 Dec 2024 11:33:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[L] Change in coreboot[main]: vc/intel/fsp: Update PTL FSP headers from 2382_01 to 2431.00
by Subrata Banik (Code Review) 02 Dec '24

02 Dec '24

Attention is currently required from: Alok Agarwal, Bora Guvendik, Jérémy Compostella, Ronak Kanabar, Subrata Banik, Vikrant L Jadeja, srinivas.kulkarni(a)intel.com. Subrata Banik has uploaded a new patch set (#8) to the change originally created by Alok Agarwal. ( https://review.coreboot.org/c/coreboot/+/85149?usp=email ) The following approvals got outdated and were removed: Code-Review+1 by srinivas.kulkarni(a)intel.com, Code-Review-1 by Subrata Banik, Verified+1 by build bot (Jenkins) Change subject: vc/intel/fsp: Update PTL FSP headers from 2382_01 to 2431.00 ...................................................................... vc/intel/fsp: Update PTL FSP headers from 2382_01 to 2431.00 Update generated FSP headers for Panther Lake from 2431.00 Changes include: - Update in FspmUpd.h : Adjusted offsets and updated comments. - FspsUpd.h: added ThcInterruptPinMuxing, ThcMode and ThcWakeOnTouch UPDs - MemInfoHob.h : Updated comments BUG=b:378789201 TEST=Able to build google/fatcat Change-Id: I1c1fed8f7ba9d25fdce5bbac3a9687800db33613 Signed-off-by: alokagar <alok.agarwal(a)intel.com> Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspmUpd.h M src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspsUpd.h M src/vendorcode/intel/fsp/fsp2_0/pantherlake/MemInfoHob.h 3 files changed, 234 insertions(+), 219 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/85149/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/85149?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1c1fed8f7ba9d25fdce5bbac3a9687800db33613 Gerrit-Change-Number: 85149 Gerrit-PatchSet: 8 Gerrit-Owner: Alok Agarwal <alok.agarwal(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: srinivas.kulkarni(a)intel.com Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Alok Agarwal <alok.agarwal(a)intel.com> Gerrit-Attention: srinivas.kulkarni(a)intel.com

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[L] Change in coreboot[main]: vc/intel/fsp: Update PTL FSP headers from 2382_01 to 2431.00
by Subrata Banik (Code Review) 02 Dec '24

02 Dec '24

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[L] Change in coreboot[main]: vc/intel/fsp: Update PTL FSP headers from 2382_01 to 2431.00
by Subrata Banik (Code Review) 02 Dec '24

02 Dec '24

Attention is currently required from: Alok Agarwal, Bora Guvendik, Jérémy Compostella, Ronak Kanabar, Vikrant L Jadeja. Subrata Banik has posted comments on this change by Alok Agarwal. ( https://review.coreboot.org/c/coreboot/+/85149?usp=email ) Change subject: vc/intel/fsp: Update PTL FSP headers from 2382_01 to 2431.00 ...................................................................... Patch Set 7: (1 comment) File src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspmUpd.h: https://review.coreboot.org/c/coreboot/+/85149/comment/4773857e_af428319?us… : PS7, Line 2387: : /** Offset 0x0976 - VR Fast Vmode ICC Limit support : Voltage Regulator Fast Vmode ICC Limit. A value of 400 = 100A. A value of 0 corresponds : to feature disabled (no reactive protection). This value represents the current : threshold where the VR would initiate reactive protection if Fast Vmode is enabled. : The value is represented in 1/4 A increments. Range 0-2040. [0] for IA, [1] for : GT, [2] for SA, [3] through [5] are Reserved. : **/ : UINT16 IccLimit[6]; this is hand edited header file IMO because after creating the FSP partial header for FSP 2431.00, I don't see this UPD existed inside FSP partial header -- To view, visit https://review.coreboot.org/c/coreboot/+/85149?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1c1fed8f7ba9d25fdce5bbac3a9687800db33613 Gerrit-Change-Number: 85149 Gerrit-PatchSet: 7 Gerrit-Owner: Alok Agarwal <alok.agarwal(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: srinivas.kulkarni(a)intel.com Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Alok Agarwal <alok.agarwal(a)intel.com> Gerrit-Comment-Date: Mon, 02 Dec 2024 11:25:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XL] Change in coreboot[main]: soc/mediatek/mt8196: Add PMIF and PMIC driver support
by Jarried Lin (Code Review) 02 Dec '24

02 Dec '24

Attention is currently required from: Hung-Te Lin, Paul Menzel, Yidi Lin, Yu-Ping Wu. Jarried Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85126?usp=email ) Change subject: soc/mediatek/mt8196: Add PMIF and PMIC driver support ...................................................................... Patch Set 8: (4 comments) File src/soc/mediatek/mt8196/include/soc/spm.h: https://review.coreboot.org/c/coreboot/+/85126/comment/06ba955b_6ea58913?us… : PS6, Line 645: u32 sys_timer_latch_l[16]; > Array usage is wrong. Should be a single array of structs of 2 u32 members. Done File src/soc/mediatek/mt8196/pmif_clk.c: https://review.coreboot.org/c/coreboot/+/85126/comment/878ddb63_057669b8?us… : PS6, Line 188: ret |= pmif_check_vlpck_freq(PMIF_VLPCK_TARGET_FREQ_MHZ); > extra space after = Done File src/soc/mediatek/mt8196/pmif_spmi.c: https://review.coreboot.org/c/coreboot/+/85126/comment/9485da14_49b13632?us… : PS7, Line 183: __func__, dev->slvid, rdata); > Align Done https://review.coreboot.org/c/coreboot/+/85126/comment/c27443c6_5ea20e26?us… : PS7, Line 216: cali_data[i].dly, cali_data[i].pol, read32(&reg->mst_sampl)); > Align Done -- To view, visit https://review.coreboot.org/c/coreboot/+/85126?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I232015f45735ee5278b09d0352410617a1565177 Gerrit-Change-Number: 85126 Gerrit-PatchSet: 8 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Mon, 02 Dec 2024 11:19:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com>

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[XL] Change in coreboot[main]: soc/mediatek/mt8196: Add PMIF and PMIC driver support
by Jarried Lin (Code Review) 02 Dec '24

02 Dec '24

Attention is currently required from: Hung-Te Lin, Jarried Lin, Paul Menzel, Yidi Lin. Hello Hope Wang, Hung-Te Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85126?usp=email to look at the new patch set (#8). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/mediatek/mt8196: Add PMIF and PMIC driver support ...................................................................... soc/mediatek/mt8196: Add PMIF and PMIC driver support Implement PMIF driver for communication between SoC and PMIC. Develop SPMI driver for communication over the SPMI bus. Add necessary configurations and base addresses to support PMIF. TEST=build pass BUG=b:317009620 Change-Id: I232015f45735ee5278b09d0352410617a1565177 Signed-off-by: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> --- M src/soc/mediatek/mt8196/Makefile.mk M src/soc/mediatek/mt8196/include/soc/addressmap.h A src/soc/mediatek/mt8196/include/soc/pmif.h A src/soc/mediatek/mt8196/include/soc/spm.h A src/soc/mediatek/mt8196/pmif_clk.c A src/soc/mediatek/mt8196/pmif_init.c A src/soc/mediatek/mt8196/pmif_spmi.c 7 files changed, 1,732 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/85126/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/85126?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I232015f45735ee5278b09d0352410617a1565177 Gerrit-Change-Number: 85126 Gerrit-PatchSet: 8 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com>

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