coreboot-gerrit December 2024

coreboot-gerrit@coreboot.org

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[XS] Change in coreboot[main]: soc/intel/common/cnvi: Nit - fix path in comment
by Nicholas Sudsgaard (Code Review) 02 Dec '24

02 Dec '24

Attention is currently required from: Sean Rhodes. Nicholas Sudsgaard has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/84991?usp=email ) Change subject: soc/intel/common/cnvi: Nit - fix path in comment ...................................................................... Patch Set 1: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/84991/comment/e45ce09f_be1bbf2d?us… : PS1, Line 7: Nit - fix path in comment : Giving a little bit more information in the title would be nice: "Fix GBTE path in comment". nit: I don't think it's necessary to mention "Nit" in a commit message. 😊 -- To view, visit https://review.coreboot.org/c/coreboot/+/84991?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If1e5d70a23c2a139ef3ee4970db2e5d528c2661e Gerrit-Change-Number: 84991 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Mon, 02 Dec 2024 14:05:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[XL] Change in coreboot[main]: soc/intel/xeon_sp: Add PCU PCI drivers
by Patrick Rudolph (Code Review) 02 Dec '24

02 Dec '24

Attention is currently required from: Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Tim Chu. Patrick Rudolph has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/85316?usp=email ) Change subject: soc/intel/xeon_sp: Add PCU PCI drivers ...................................................................... Patch Set 5: (1 comment) File src/soc/intel/xeon_sp/cpx/cpu.c: https://review.coreboot.org/c/coreboot/+/85316/comment/52407b93_4301b9a9?us… : PS4, Line 121: msr.lo |= BIT31; /* Lock it */ > Should this be a separate patch with some comment of its context? Done in https://review.coreboot.org/c/coreboot/+/85439/1 -- To view, visit https://review.coreboot.org/c/coreboot/+/85316?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib4a58b80a1c9fd766946b17c11c629a9df79c573 Gerrit-Change-Number: 85316 Gerrit-PatchSet: 5 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Mon, 02 Dec 2024 13:30:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com>

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[S] Change in coreboot[main]: mb/ocp/tiogapass: Implement mainboard_dimm_slot_exists
by Patrick Rudolph (Code Review) 02 Dec '24

02 Dec '24

Attention is currently required from: Johnny Lin, Morgan Jang, Patrick Rudolph. Hello Johnny Lin, Morgan Jang, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85318?usp=email to look at the new patch set (#5). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mb/ocp/tiogapass: Implement mainboard_dimm_slot_exists ...................................................................... mb/ocp/tiogapass: Implement mainboard_dimm_slot_exists The board has 12 slots, each holding one DDR4 ECC RDIMM, on each socket. Implement mainboard_dimm_slot_exists accordingly to advertise all slots as SMBIOS type 17. Change-Id: I31cb4a89aa11258ac04eb69a0e9c86f258280484 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/mainboard/ocp/tiogapass/romstage.c 1 file changed, 17 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/85318/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/85318?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I31cb4a89aa11258ac04eb69a0e9c86f258280484 Gerrit-Change-Number: 85318 Gerrit-PatchSet: 5 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Morgan Jang <Morgan_Jang(a)wiwynn.com>

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[M] Change in coreboot[main]: soc/intel/xeon_sp: Advertise DIMMs on skylake_sp as well
by Patrick Rudolph (Code Review) 02 Dec '24

02 Dec '24

Attention is currently required from: Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Shuo Liu, Tim Chu. Hello Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Shuo Liu, Tim Chu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85319?usp=email to look at the new patch set (#5). The following approvals got outdated and were removed: Code-Review+2 by Shuo Liu, Verified+1 by build bot (Jenkins) The change is no longer submittable: Code-Review and Verified are unsatisfied now. Change subject: soc/intel/xeon_sp: Advertise DIMMs on skylake_sp as well ...................................................................... soc/intel/xeon_sp: Advertise DIMMs on skylake_sp as well Add the MEMMAP_DIMM_DEVICE_INFO_STRUCT for skylake_sp and let common code fill in the SMBIOS type 17 entries for all slots and found DIMMs. This also allows to build dimm.c unconditionally on all xeon_sp socs. Test: On ocp/tiogapass all DIMMs and slots are visible in SMBIOS. Change-Id: I686b1e3ef946240785111f86a5f23a109a6a52ad Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/intel/xeon_sp/Makefile.mk M src/soc/intel/xeon_sp/cpx/Makefile.mk M src/soc/intel/xeon_sp/gnr/Makefile.mk M src/soc/intel/xeon_sp/skx/romstage.c M src/soc/intel/xeon_sp/spr/Makefile.mk M src/vendorcode/intel/fsp/fsp2_0/skylake_sp/hob_memmap.h 6 files changed, 73 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/85319/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/85319?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I686b1e3ef946240785111f86a5f23a109a6a52ad Gerrit-Change-Number: 85319 Gerrit-PatchSet: 5 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com>

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[S] Change in coreboot[main]: soc/intel/xeon_sp/skx: Fix CPU init
by Patrick Rudolph (Code Review) 02 Dec '24

02 Dec '24

Attention is currently required from: Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Shuo Liu, Tim Chu. Patrick Rudolph has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/85289?usp=email ) Change subject: soc/intel/xeon_sp/skx: Fix CPU init ...................................................................... Patch Set 3: (1 comment) Patchset: PS2: > TESTED = tiogapass? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/85289?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If08ef5150b104b0c2329fcb64a0476ce641c831c Gerrit-Change-Number: 85289 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Mon, 02 Dec 2024 13:29:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com>

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[XS] Change in coreboot[main]: soc/intel/xeon_sp/cpx: Fix register lock
by Patrick Rudolph (Code Review) 02 Dec '24

02 Dec '24

Attention is currently required from: Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Shuo Liu, Tim Chu. Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85439?usp=email ) Change subject: soc/intel/xeon_sp/cpx: Fix register lock ...................................................................... soc/intel/xeon_sp/cpx: Fix register lock Do not use a define for a PCI register to lock a MSR. The defines will be moved in the following commit to it's own header, preventing the use in CPX CPU init. Change-Id: I76a8ae13dbd942291aacbb4bd84140be156bc563 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/intel/xeon_sp/cpx/cpu.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/85439/1 diff --git a/src/soc/intel/xeon_sp/cpx/cpu.c b/src/soc/intel/xeon_sp/cpx/cpu.c index d90b8b5..4af20f1 100644 --- a/src/soc/intel/xeon_sp/cpx/cpu.c +++ b/src/soc/intel/xeon_sp/cpx/cpu.c @@ -118,7 +118,7 @@ /* The MSRs and CSRS have the same register layout. Use the CSRS bit definitions Lock Turbo. Did FSP-S set this up??? */ msr = rdmsr(MSR_TURBO_ACTIVATION_RATIO); - msr.lo |= (TURBO_ACTIVATION_RATIO_LOCK); + msr.lo |= BIT31; /* Lock it */ wrmsr(MSR_TURBO_ACTIVATION_RATIO, msr); } -- To view, visit https://review.coreboot.org/c/coreboot/+/85439?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I76a8ae13dbd942291aacbb4bd84140be156bc563 Gerrit-Change-Number: 85439 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com>

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[S] Change in coreboot[main]: soc/intel/xeon_sp/skx: Fix CPU init
by Patrick Rudolph (Code Review) 02 Dec '24

02 Dec '24

Attention is currently required from: Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Shuo Liu, Tim Chu. Hello Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Shuo Liu, Tim Chu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85289?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Code-Review+2 by Christian Walter, Code-Review+2 by Shuo Liu, Verified+1 by build bot (Jenkins) The change is no longer submittable: Code-Review and Verified are unsatisfied now. Change subject: soc/intel/xeon_sp/skx: Fix CPU init ...................................................................... soc/intel/xeon_sp/skx: Fix CPU init Move CPU init closer to other SoC and CPX. FSP-S only is aware of socket 0, thus all cores must rerun all settings already done by FSP, in order to set up socket 1 as well. FSP sets the following on socket0: - Set BIT20 in MSR_VR_MISC_CONFIG - Set LTR_IIO_DISABLE in MSR_POWER_CTL Lock the following MSRs: - MSR_SNC_CONFIG - MSR_CONFIG_TDP_CONTROL - MSR_FEATURE_CONFIG - MSR_TURBO_ACTIVATION_RATIO Also do the following as done on other SoCs: - Configure VMX and lock it - Enable LAPIC TPRs (fixes MWAIT support) - Honor CONFIG_SET_MSR_AESNI_LOCK_BIT - Set TCC thermal target as set in devicetree Fixes 8 second wakeup time from LAPIC interrupts when in MWAIT. TEST: Booted on ocp/tiogapass to Linux 6.9 with all cores in ACPI C6, no boot delay or hung tasks could be found. Change-Id: If08ef5150b104b0c2329fcb64a0476ce641c831c Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/intel/common/block/cpu/cpulib.c M src/soc/intel/xeon_sp/include/soc/msr.h M src/soc/intel/xeon_sp/skx/cpu.c 3 files changed, 36 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/85289/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/85289?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If08ef5150b104b0c2329fcb64a0476ce641c831c Gerrit-Change-Number: 85289 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com>

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[M] Change in coreboot[main]: soc/mediatek/mt8196: Add booker driver
by Jarried Lin (Code Review) 02 Dec '24

02 Dec '24

Attention is currently required from: Dehui Sun, Hung-Te Lin, Paul Menzel, Yidi Lin, Yu-Ping Wu. Hello Dehui Sun, Hung-Te Lin, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85362?usp=email to look at the new patch set (#9). Change subject: soc/mediatek/mt8196: Add booker driver ...................................................................... soc/mediatek/mt8196: Add booker driver The MTK booker mainly uses CHI protocol, but doesn't support coherence (which is achieved through ACP solution). Additionally, the booker also uses other protocols such as AXI, which translates CHI transactions into EMI's AXI transactions. Currently, the mt8196 booker only uses the functions of SLC CMO Routing. If downstream SLC needs CMO command propagation from the DSU, it can set bit[3] (disable_cmo_prop) to 0 in the por_sbsx_cfg_ctl register of each SBSX node. TEST=build pass, check boot log with: [booker_init] AP hash rule: 0xbe00. BUG=b:317009620 Signed-off-by: Dehui Sun <dehui.sun(a)mediatek.corp-partner.google.com> Change-Id: I6bde1e20137890addf18b23b47f17b1f63824b22 --- M src/soc/mediatek/mt8196/Makefile.mk A src/soc/mediatek/mt8196/booker.c M src/soc/mediatek/mt8196/bootblock.c A src/soc/mediatek/mt8196/include/soc/booker.h 4 files changed, 50 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/85362/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/85362?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6bde1e20137890addf18b23b47f17b1f63824b22 Gerrit-Change-Number: 85362 Gerrit-PatchSet: 9 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Dehui Sun <dehui.sun(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Dehui Sun <dehui.sun(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com>

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[M] Change in coreboot[main]: soc/mediatek/mt8196: Add booker driver
by Jarried Lin (Code Review) 02 Dec '24

02 Dec '24

Attention is currently required from: Hung-Te Lin, Paul Menzel, Yidi Lin, Yu-Ping Wu. Hello Dehui Sun, Hung-Te Lin, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85362?usp=email to look at the new patch set (#8). Change subject: soc/mediatek/mt8196: Add booker driver ...................................................................... soc/mediatek/mt8196: Add booker driver The MTK booker mainly uses CHI protocol, but doesn't supports coherence (which is achieved through ACP solution). Additionally, the booker also uses other protocols such as AXI, which translates CHI transactions into EMI's AXI transactions. Currently, the mt8196 booker only uses the functions of SLC CMO Routing. If downstream SLC needs CMO command propagation from the DSU, it can set bit[3] (disable_cmo_prop) to 0 in the por_sbsx_cfg_ctl register of each SBSX node. TEST=build pass, check boot log with: [booker_init] AP hash rule: 0xbe00. BUG=b:317009620 Signed-off-by: Dehui Sun <dehui.sun(a)mediatek.corp-partner.google.com> Change-Id: I6bde1e20137890addf18b23b47f17b1f63824b22 --- M src/soc/mediatek/mt8196/Makefile.mk A src/soc/mediatek/mt8196/booker.c M src/soc/mediatek/mt8196/bootblock.c A src/soc/mediatek/mt8196/include/soc/booker.h 4 files changed, 50 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/85362/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/85362?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6bde1e20137890addf18b23b47f17b1f63824b22 Gerrit-Change-Number: 85362 Gerrit-PatchSet: 8 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Dehui Sun <dehui.sun(a)mediatek.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com>

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[XS] Change in coreboot[main]: [WIP] mb/google/rex/var/kanix: Add Fn key scancode
by Tyler Wang (Code Review) 02 Dec '24

02 Dec '24

Tyler Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85438?usp=email ) Change subject: [WIP] mb/google/rex/var/kanix: Add Fn key scancode ...................................................................... [WIP] mb/google/rex/var/kanix: Add Fn key scancode The Fn key on kanix emits a scancode of 94 (0x5e). BUG=none TEST=none Change-Id: Ia693813dafe1bd35840dfb892827598a7ca9c88f Signed-off-by: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> --- M src/mainboard/google/rex/Kconfig 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/85438/1 diff --git a/src/mainboard/google/rex/Kconfig b/src/mainboard/google/rex/Kconfig index 73f28f3..f12910b 100644 --- a/src/mainboard/google/rex/Kconfig +++ b/src/mainboard/google/rex/Kconfig @@ -1,5 +1,8 @@ ## SPDX-License-Identifier: GPL-2.0-only +config ACPI_FNKEY_GEN_SCANCODE + default 94 if BOARD_GOOGLE_KANIX + config BOARD_GOOGLE_REX_COMMON def_bool n select BOARD_ROMSIZE_KB_32768 -- To view, visit https://review.coreboot.org/c/coreboot/+/85438?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia693813dafe1bd35840dfb892827598a7ca9c88f Gerrit-Change-Number: 85438 Gerrit-PatchSet: 1 Gerrit-Owner: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com>

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coreboot-gerrit December 2024