coreboot-gerrit December 2024

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[XS] Change in coreboot[main]: soc/mediatek/mt8196: Require DRAM blob to exist
by Yidi Lin (Code Review) 03 Dec '24

03 Dec '24

Attention is currently required from: Hung-Te Lin, Yu-Ping Wu. Yidi Lin has posted comments on this change by Yu-Ping Wu. ( https://review.coreboot.org/c/coreboot/+/85441?usp=email ) Change subject: soc/mediatek/mt8196: Require DRAM blob to exist ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85441?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib902dc4778f34a144dddf847c283fe77d4c776f6 Gerrit-Change-Number: 85441 Gerrit-PatchSet: 2 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Tue, 03 Dec 2024 01:52:02 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: Update blobs submodule to upstream main
by Yidi Lin (Code Review) 03 Dec '24

03 Dec '24

Attention is currently required from: Yu-Ping Wu. Yidi Lin has posted comments on this change by Yu-Ping Wu. ( https://review.coreboot.org/c/coreboot/+/85444?usp=email ) Change subject: Update blobs submodule to upstream main ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85444?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia9bf331e4482d7b2a231f4b67552eea80207018e Gerrit-Change-Number: 85444 Gerrit-PatchSet: 1 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Tue, 03 Dec 2024 01:41:40 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: intel/common/block: Fix PL4 programming
by Jérémy Compostella (Code Review) 03 Dec '24

03 Dec '24

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Jérémy Compostella, Kapil Porwal, Subrata Banik, Tarun. Hello Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Subrata Banik, Tarun, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85244?usp=email to look at the new patch set (#8). Change subject: intel/common/block: Fix PL4 programming ...................................................................... intel/common/block: Fix PL4 programming When variant_update_cpu_power_limits() programs PL4, it systematically sets the first entry of the power_limits_config SoC chip data structure, while the current SoC SKU may be tied to another entry. This commit introduces a new soc_get_sku_power_limits() API that variant_update_cpu_power_limits() uses to retrieve the correct power limits entry. This function must be supported by the SoC code and return a pointer to the current SKU SoC power limits data structure. Luckily, this bug did not lead to any issues as it has only been used with SKUs whose power limits are in the first entry or to program a PL4 value identical to the default value. This CL also updates the documentation of variant_update_cpu_power_limits() to fix a typo and provide some extra details on the performed operations. BUG=b:380408956 TEST=TBD Change-Id: I32de8a24a2b5aee3eb5a6eee2d1d91e203085e65 Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> --- M src/soc/intel/common/block/include/intelblocks/power_limit.h M src/soc/intel/common/block/power_limit/power_limit.c M src/soc/intel/meteorlake/systemagent.c 3 files changed, 52 insertions(+), 29 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/85244/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/85244?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I32de8a24a2b5aee3eb5a6eee2d1d91e203085e65 Gerrit-Change-Number: 85244 Gerrit-PatchSet: 8 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com>

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[XS] Change in coreboot[main]: Update blobs submodule to upstream main
by Yu-Ping Wu (Code Review) 03 Dec '24

03 Dec '24

Yu-Ping Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85444?usp=email ) Change subject: Update blobs submodule to upstream main ...................................................................... Update blobs submodule to upstream main Updating from commit id 45f1b757402f: 2024-08-29 11:51:27 +0200 - (soc/intel/raptorlake: Add microcode for 06-b7-01) to commit id 14f8fcc1b426: 2024-11-28 05:07:49 +0000 - (soc/mediatek/mt8196: Update SSPM firmware to v2.0) This brings in 8 new commits: 14f8fcc1b426 soc/mediatek/mt8196: Update SSPM firmware to v2.0 754f7ad6c808 soc/mediatek/mt8196: Add dram.elf version 0.3.0 for DRAM calibration 612f93620740 3rdparty/blobs/mb/google/guybrush: Update signed PSP verstage binaries 3180f6d462a0 3rdparty/blobs/mb/google/zork: Update signed PSP verstage binaries eb48279e69eb 3rdparty/blobs/mb/google/zork: Update PSP signing token 002ee2ca6e04 soc/mediatek/mt8196: Add MCUPM firmware v1.0 ce5fcc5a745e soc/mediatek/mt8196: Add dpm.pm and dpm.dm version 1.0 ae17d7f52c68 soc/mediatek/mt8196: Add SSPM firmware v1.0 Change-Id: Ia9bf331e4482d7b2a231f4b67552eea80207018e Signed-off-by: Yu-Ping Wu <yupingso(a)chromium.org> --- M 3rdparty/blobs 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/85444/1 diff --git a/3rdparty/blobs b/3rdparty/blobs index 45f1b75..14f8fcc 160000 --- a/3rdparty/blobs +++ b/3rdparty/blobs @@ -1 +1 @@ -Subproject commit 45f1b757402f9a0ae8a4e021a8f5745318515308 +Subproject commit 14f8fcc1b426cb0884a21a9b715da6e0c1c7f434 -- To view, visit https://review.coreboot.org/c/coreboot/+/85444?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia9bf331e4482d7b2a231f4b67552eea80207018e Gerrit-Change-Number: 85444 Gerrit-PatchSet: 1 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com>

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[M] Change in coreboot[main]: intel/common/block: Fix PL4 programming
by Jérémy Compostella (Code Review) 03 Dec '24

03 Dec '24

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Jérémy Compostella, Kapil Porwal, Subrata Banik, Tarun. Hello Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Subrata Banik, Tarun, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85244?usp=email to look at the new patch set (#7). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: intel/common/block: Fix PL4 programming ...................................................................... intel/common/block: Fix PL4 programming When variant_update_cpu_power_limits() programs PL4, it systematically set the first entry of the power_limits_config SoC chip data structure while the current SoC SKU may be tied to another entry. This commit introduces a new soc_get_sku_power_limits() API that variant_update_cpu_power_limits() uses to retrieve the right power limits entry. This function shall be supported by the SoC code and return a pointer to the current SKU SoC power limits data structure. Luckily, this bug did not lead to any issue as it has only been used with SKU which power limits are in the first entry or to program a PL4 value identical to the default value. This CL also update the documentation of variant_update_cpu_power_limits() to fix a typo and provide some extra details on the performed operations. BUG=b:380408956 TEST=TBD Change-Id: I32de8a24a2b5aee3eb5a6eee2d1d91e203085e65 Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> --- M src/soc/intel/common/block/include/intelblocks/power_limit.h M src/soc/intel/common/block/power_limit/power_limit.c M src/soc/intel/meteorlake/systemagent.c 3 files changed, 52 insertions(+), 29 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/85244/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/85244?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I32de8a24a2b5aee3eb5a6eee2d1d91e203085e65 Gerrit-Change-Number: 85244 Gerrit-PatchSet: 7 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com>

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[M] Change in coreboot[main]: soc/intel/pantherlake: Add soc_get_sku_power_limits() support
by Jérémy Compostella (Code Review) 03 Dec '24

03 Dec '24

Jérémy Compostella has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85443?usp=email ) Change subject: soc/intel/pantherlake: Add soc_get_sku_power_limits() support ...................................................................... soc/intel/pantherlake: Add soc_get_sku_power_limits() support soc_get_sku_power_limits() implementation is required to use variant_update_cpu_power_limits() which we would like to leverage for Google fatcat missing battery use-case. BUG=b:377798581 TEST=TBD Change-Id: Ib89979e7933da62c8ddfec09ecf27f86b7ac0e09 Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> --- M src/soc/intel/pantherlake/systemagent.c 1 file changed, 38 insertions(+), 26 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/85443/1 diff --git a/src/soc/intel/pantherlake/systemagent.c b/src/soc/intel/pantherlake/systemagent.c index e7a0701..1fa558a 100644 --- a/src/soc/intel/pantherlake/systemagent.c +++ b/src/soc/intel/pantherlake/systemagent.c @@ -137,25 +137,33 @@ sa_add_fixed_mmio_resources(dev, resource_cnt, cfg_rsrc, count); } -static void configure_tdp(struct device *dev) +static u16 get_sa_pci_id(void) { - struct soc_power_limits_config *soc_config; + static u16 sa_pci_id; struct device *sa; - uint16_t sa_pci_id; - u8 tdp; - size_t i; - bool config_tdp = false; + + if (sa_pci_id) + return sa_pci_id; + + sa = pcidev_path_on_root(PCI_DEVFN_ROOT); + sa_pci_id = sa ? pci_read_config16(sa, PCI_DEVICE_ID) : 0xffff; + + return sa_pci_id; +} + +struct soc_power_limits_config *soc_get_sku_power_limits(void) +{ struct soc_intel_pantherlake_config *config; + u16 sa_pci_id; + u8 tdp; config = config_of_soc(); /* Get System Agent PCI ID */ - sa = pcidev_path_on_root(PCI_DEVFN_ROOT); - sa_pci_id = sa ? pci_read_config16(sa, PCI_DEVICE_ID) : 0xFFFF; - - if (sa_pci_id == 0xFFFF) { + sa_pci_id = get_sa_pci_id(); + if (sa_pci_id == 0xffff) { printk(BIOS_WARNING, "Unknown SA PCI Device!\n"); - return; + return NULL; } tdp = get_cpu_tdp(); @@ -164,22 +172,26 @@ * Choose power limits configuration based on the CPU SA PCI ID and * CPU TDP value. */ - for (i = 0; i < ARRAY_SIZE(cpuid_to_ptl); i++) { - if (sa_pci_id == cpuid_to_ptl[i].cpu_id && - tdp == cpuid_to_ptl[i].cpu_tdp) { - soc_config = &config->power_limits_config[cpuid_to_ptl[i].limits]; - set_power_limits(MOBILE_SKU_PL1_TIME_SEC, soc_config); - config_tdp = true; - printk(BIOS_DEBUG, "Configured power limits for SA PCI ID: 0x%4x\n", - sa_pci_id); - break; - } - } + for (size_t i = 0; i < ARRAY_SIZE(cpuid_to_ptl); i++) + if (sa_pci_id == cpuid_to_ptl[i].cpu_id && tdp == cpuid_to_ptl[i].cpu_tdp) + return &config->power_limits_config[cpuid_to_ptl[i].limits]; - if (!config_tdp) { - printk(BIOS_WARNING, "Skipped power limits configuration for SA PCI ID: 0x%4x\n", - sa_pci_id); - return; + return NULL; +} + +static void configure_tdp(struct device *dev) +{ + struct soc_power_limits_config *power_limits; + + power_limits = soc_get_sku_power_limits(); + if (power_limits) { + set_power_limits(MOBILE_SKU_PL1_TIME_SEC, power_limits); + printk(BIOS_DEBUG, "Configured power limits for SA PCI ID: 0x%4x\n", + get_sa_pci_id()); + } else { + printk(BIOS_WARNING, + "Skipped power limits configuration for SA PCI ID: 0x%4x\n", + get_sa_pci_id()); } } -- To view, visit https://review.coreboot.org/c/coreboot/+/85443?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib89979e7933da62c8ddfec09ecf27f86b7ac0e09 Gerrit-Change-Number: 85443 Gerrit-PatchSet: 1 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com>

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[XS] Change in coreboot[main]: mb/google/fatcat: Remove unnecessary prototype
by Jérémy Compostella (Code Review) 03 Dec '24

03 Dec '24

Jérémy Compostella has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85442?usp=email ) Change subject: mb/google/fatcat: Remove unnecessary prototype ...................................................................... mb/google/fatcat: Remove unnecessary prototype BUG=b:377798581 TEST=fatcat board build is successful Change-Id: I5d71e9edde0ecbd7aaf316cd754a6ebcff9da77a Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> --- M src/mainboard/google/fatcat/variants/baseboard/include/baseboard/variants.h 1 file changed, 0 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/85442/1 diff --git a/src/mainboard/google/fatcat/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/fatcat/variants/baseboard/include/baseboard/variants.h index 581ba51..2a70408 100644 --- a/src/mainboard/google/fatcat/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/fatcat/variants/baseboard/include/baseboard/variants.h @@ -25,9 +25,6 @@ bool variant_is_half_populated(void); void variant_update_soc_chip_config(struct soc_intel_pantherlake_config *config); -/* Get soc power limit config struct for current CPU sku */ -struct soc_power_limits_config *variant_get_soc_power_limit_config(void); - enum s0ix_entry { S0IX_EXIT, S0IX_ENTRY, -- To view, visit https://review.coreboot.org/c/coreboot/+/85442?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5d71e9edde0ecbd7aaf316cd754a6ebcff9da77a Gerrit-Change-Number: 85442 Gerrit-PatchSet: 1 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com>

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[M] Change in coreboot[main]: intel/common/block: Fix PL4 programming
by Jérémy Compostella (Code Review) 03 Dec '24

03 Dec '24

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Jérémy Compostella, Kapil Porwal, Subrata Banik, Tarun. Jérémy Compostella has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/85244?usp=email ) Change subject: intel/common/block: Fix PL4 programming ...................................................................... Patch Set 5: (1 comment) Patchset: PS5: @subratabanik@google.com, could someone on your side test this ? I tested a similar change on fatcat. -- To view, visit https://review.coreboot.org/c/coreboot/+/85244?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I32de8a24a2b5aee3eb5a6eee2d1d91e203085e65 Gerrit-Change-Number: 85244 Gerrit-PatchSet: 5 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Tue, 03 Dec 2024 00:51:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[M] Change in coreboot[main]: intel/common/block: Fix PL4 programming
by Jérémy Compostella (Code Review) 03 Dec '24

03 Dec '24

Attention is currently required from: Subrata Banik. Jérémy Compostella has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/85244?usp=email ) Change subject: intel/common/block: Fix PL4 programming ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/85244?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I32de8a24a2b5aee3eb5a6eee2d1d91e203085e65 Gerrit-Change-Number: 85244 Gerrit-PatchSet: 5 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Comment-Date: Tue, 03 Dec 2024 00:50:25 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: soc/mediatek/mt8196: Require DRAM blob to exist
by Yu-Ping Wu (Code Review) 03 Dec '24

03 Dec '24

Yu-Ping Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85441?usp=email ) Change subject: soc/mediatek/mt8196: Require DRAM blob to exist ...................................................................... soc/mediatek/mt8196: Require DRAM blob to exist The SoC won't be able to boot without dram.elf. Therefore, we should always expect the file to exist in build time. BUG=none TEST=emerge-rauru coreboot BRANCH=none Change-Id: Ib902dc4778f34a144dddf847c283fe77d4c776f6 Signed-off-by: Yu-Ping Wu <yupingso(a)chromium.org> --- M src/soc/mediatek/mt8196/Makefile.mk 1 file changed, 2 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/85441/1 diff --git a/src/soc/mediatek/mt8196/Makefile.mk b/src/soc/mediatek/mt8196/Makefile.mk index c0b4914..e68cb8c 100644 --- a/src/soc/mediatek/mt8196/Makefile.mk +++ b/src/soc/mediatek/mt8196/Makefile.mk @@ -59,9 +59,8 @@ $(DRAM_CBFS)-file := $(MT8196_BLOB_DIR)/dram.elf $(DRAM_CBFS)-type := stage $(DRAM_CBFS)-compression := $(CBFS_PRERAM_COMPRESS_FLAG) -ifneq ($(wildcard $($(DRAM_CBFS)-file)),) - cbfs-files-y += $(DRAM_CBFS) -endif +cbfs-files-y += $(DRAM_CBFS) + $(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin ./util/mtkheader/gen-bl-img.py mt8196 sf $< $@ -- To view, visit https://review.coreboot.org/c/coreboot/+/85441?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib902dc4778f34a144dddf847c283fe77d4c776f6 Gerrit-Change-Number: 85441 Gerrit-PatchSet: 1 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com>

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coreboot-gerrit December 2024