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Change subject: util/amdfwtool: Add binary parsing
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Patch Set 8:
(1 comment)
File util/amdfwtool/amdfwtool.c:
https://review.coreboot.org/c/coreboot/+/84373/comment/8129c3a3_da005fa2?us… :
PS8, Line 263: { .type = AMD_FW_MINIMSMU, .subprog = 0, .level = PSP_BOTH | PSP_LVL2_AB },
: { .type = AMD_FW_MINIMSMU, .subprog = 1, .level = PSP_BOTH | PSP_LVL2_AB },
> Dropping "Instance" seems like it could potentially be a problem.
this adds the inst=0, subprog=1 case, but drops the inst=1, subprog=0 case
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Change subject: util/amdfwtool: Add binary parsing
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Patch Set 8:
(4 comments)
Patchset:
PS8:
Since this gets used across SOC generations, I'd really like to see a sampling of successful tests with this patch. Will see if Felix can help.
File util/amdfwtool/amdfwtool.c:
https://review.coreboot.org/c/coreboot/+/84373/comment/fc901a4d_f5568ef0?us… :
PS8, Line 263: { .type = AMD_FW_MINIMSMU, .subprog = 0, .level = PSP_BOTH | PSP_LVL2_AB },
: { .type = AMD_FW_MINIMSMU, .subprog = 1, .level = PSP_BOTH | PSP_LVL2_AB },
Dropping "Instance" seems like it could potentially be a problem.
https://review.coreboot.org/c/coreboot/+/84373/comment/fafb60f0_521aca35?us… :
PS8, Line 324: { .type = AMD_BIOS_APOB_NV, .level = BDT_BOTH },
Are you sure this is required? Or maybe it became a requirement on glinda? IIRC we've traditionally kept Level 1 as minimal as possible.
https://review.coreboot.org/c/coreboot/+/84373/comment/9e245410_398e269c?us… :
PS8, Line 381: { .type = AMD_BIOS_MP2_CFG, .level = BDT_BOTH },
Same as above.
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Change subject: drivers/spi: add RPMC support
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Patch Set 10: Code-Review+2
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Change subject: drivers/pc80/pc/keyboard.c: Add function to change a command byte bit
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Patch Set 3: Code-Review+2
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Change subject: vendorcode/amd/fsp/glinda: port usb_phy_config structure
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Patch Set 7: Code-Review+2
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/84435/comment/afbf0536_f90d3ee0?us… :
PS5, Line 11: Reviewed-by: Anand Vaikar <a.vaikar2021(a)gmail.com>
: Reviewed-by: Ritul Guru <ritul.bits(a)gmail.com>
: Tested-by: Satya Sreenivas L <Satya.SreenivasL(a)amd.com>
:
> I didn't know that tool existed. Thanks for the pointer. […]
I suspected I meant the comment for the AMD folks. But glad you know about it too, now 😊
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Change subject: soc/amd/glinda: Update MCA banks
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Patch Set 2: Code-Review+2
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Change subject: util/crossgcc: Add libstdcxx target
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Patch Set 8:
(2 comments)
Patchset:
PS5:
> Honestly I feel like any modular solution we come up with is going to be more complex than this 48 l […]
It's also not doing anything unreasonable. We're adding support for an additional library that could be useful to upstream and other projects. I added it in a way that wouldn't affect any other builds, and would only be called as needed.
File util/crossgcc/buildgcc:
https://review.coreboot.org/c/coreboot/+/85275/comment/040f0fa8_a5f0ba20?us… :
PS8, Line 784: @
> POSIX `sh` doesn't actually have arrays AFAIK.
Ack, I was using bash locally. I'll update.
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