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Change subject: ec/google/chromeec: Add debug timestamp for host EC commands
......................................................................
Patch Set 9:
(1 comment)
File src/ec/google/chromeec/ec_lpc.c:
https://review.coreboot.org/c/coreboot/+/85326/comment/d7ba54e3_41a8f99b?us… :
PS9, Line 286: printk
> > Please call stopwatch_tick() before accessing sw.current. […]
The absolute timestamp isn't really meant to be accessed at all. Is there a reason to print it here (rather than just the duration)? coreboot timers aren't guaranteed to start at 0 at boot, so absolute timer values are basically meaningless anyway.
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Change subject: mb/asrock: Add ASRock H370m-ITX support (Coffee Lake)
......................................................................
Patch Set 16:
(4 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/65225/comment/f95e72d7_3d19b5dd?us… :
PS15, Line 8:
> > `Possible unwrapped commit description (prefer a maximum 72 chars per line)` […]
Done
https://review.coreboot.org/c/coreboot/+/65225/comment/b1ed5621_45b3b57a?us… :
PS15, Line 9: Ubuntu 24.04
> Please also add the Linux kernel version.
Done
https://review.coreboot.org/c/coreboot/+/65225/comment/0c49f21b_d86ecf27?us… :
PS15, Line 9: IOS
> Please add the version.
Done
https://review.coreboot.org/c/coreboot/+/65225/comment/2a95f67b_53708c6f?us… :
PS15, Line 11: the
> The
Done
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Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/65225?usp=email
to look at the new patch set (#16).
Change subject: mb/asrock: Add ASRock H370m-ITX support (Coffee Lake)
......................................................................
mb/asrock: Add ASRock H370m-ITX support (Coffee Lake)
I tested my code on a Intel i3-9100F under
Ubuntu 24.04 and Windows 10 with SeaBIOS.
following things are working flawlessly:
* all PCIe slots
* all USB ports
* VGA init in SeaBIOS (discrete nvida gpu)
* WiFi and onboard sound
* both Ethernet ports
* all SATA ports (besides m.2)
what was not tested:
* front audio jacks
whats not working:
* suspend to ram, it won't poweroff correctly
* edk2 with Windows 10+
* m.2 sata port/pcie is working
romstage changes:
* corrects resistor cfg (see 573387)
* removes unused dq/dqs mappings
* adds default config for Asrock H370M-ITX
* uses devicetree pci aliases
* removes unncesseray keys in devicetree.cb
* rename Makefile.inc to Makefile.mk
* load gpio config after FSP-S init
* move gpio_table to C file
Change-Id: I79302247311471153ebbba991081365d9265791b
Signed-off-by: Max Fritz <antischmock(a)googlemail.com>
---
A configs/config.asrock_h370m_itx
A src/mainboard/asrock/h370m/Kconfig
A src/mainboard/asrock/h370m/Kconfig.name
A src/mainboard/asrock/h370m/Makefile.mk
A src/mainboard/asrock/h370m/board_info.txt
A src/mainboard/asrock/h370m/bootblock.c
A src/mainboard/asrock/h370m/cmos.default
A src/mainboard/asrock/h370m/cmos.layout
A src/mainboard/asrock/h370m/devicetree.cb
A src/mainboard/asrock/h370m/dsdt.asl
A src/mainboard/asrock/h370m/gpio.c
A src/mainboard/asrock/h370m/include/gpio.h
A src/mainboard/asrock/h370m/ramstage.c
A src/mainboard/asrock/h370m/romstage.c
14 files changed, 915 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/65225/16
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Change subject: mb/asrock: Add ASRock H370m-ITX support (Coffee Lake)
......................................................................
Patch Set 15:
(5 comments)
Patchset:
PS15:
Nice. Thank you.
Any idea, where the user *6d6178667269747a* denoted as Owner of this change-set is?
Commit Message:
https://review.coreboot.org/c/coreboot/+/65225/comment/e91af852_5efe8eef?us… :
PS15, Line 8:
> `Possible unwrapped commit description (prefer a maximum 72 chars per line)`
Please fix.
https://review.coreboot.org/c/coreboot/+/65225/comment/af361068_531eaaf0?us… :
PS15, Line 9: IOS
Please add the version.
https://review.coreboot.org/c/coreboot/+/65225/comment/507d1971_03de54ff?us… :
PS15, Line 9: Ubuntu 24.04
Please also add the Linux kernel version.
https://review.coreboot.org/c/coreboot/+/65225/comment/1cf32d38_f04bcf0a?us… :
PS15, Line 11: the
The
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Change subject: soc/intel/common/cnvi: Fix GBTE path in comment
......................................................................
Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/84991/comment/3f78ba9d_6e85c6d9?us… :
PS1, Line 7: Nit - fix path in comment
:
> Giving a little bit more information in the title would be nice: "Fix GBTE path in comment". […]
Done
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Change subject: drivers/soundwire/alc711: Add common Kconfig for ALC7xx soundwire codecs
......................................................................
Patch Set 7:
(2 comments)
File src/drivers/soundwire/alc711/alc711.c:
https://review.coreboot.org/c/coreboot/+/85282/comment/f0944230_3ae9cdc6?us… :
PS7, Line 110: config->alc711_address[dev->path.generic.id].version = SOUNDWIRE_VERSION_1_1;
: config->alc711_address[dev->path.generic.id].class = MIPI_CLASS_NONE;
: } else {
: config->alc711_address[dev->path.generic.id].version = SOUNDWIRE_VERSION_1_2;
: config->alc711_address[dev->path.generic.id].class = MIPI_CLASS_SDCA;
Please set these in the devicetree itself.
File src/drivers/soundwire/alc711/chip.h:
https://review.coreboot.org/c/coreboot/+/85282/comment/775ae108_1417b21d?us… :
PS7, Line 13: [MAX_SNDW_LINKS]
In your previous iteration of the change, there was only one instance of the alc711_address. Why do we need 4 instances now based on dev->path.generic.id?
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Change subject: drivers/usb/intel_bluetooth: Fix GBTE to return Local0
......................................................................
Patch Set 4:
(4 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/84989/comment/56981efb_25bebd00?us… :
PS1, Line 7: Fix GBTE return value
> Maybe extend: […]
Done
https://review.coreboot.org/c/coreboot/+/84989/comment/aa3ac5c4_3c3c0229?us… :
PS1, Line 9: `acpigen_soc_get_tx_gpio` will put the result into LOCAL0, rather than
> nit: Local0
Done
https://review.coreboot.org/c/coreboot/+/84989/comment/88156f59_824524ef?us… :
PS1, Line 11:
> Add the value before and after, and describe, if something starts working now?
Done
File src/drivers/usb/acpi/intel_bluetooth.c:
https://review.coreboot.org/c/coreboot/+/84989/comment/71adb0ed_dd2c0e7e?us… :
PS1, Line 329:
> This is not needed as you use `acpigen_write_return_*` instead.
Done
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Hello build bot (Jenkins),
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Change subject: drivers/usb/intel_bluetooth: Fix GBTE to return Local0
......................................................................
drivers/usb/intel_bluetooth: Fix GBTE to return Local0
`acpigen_soc_get_tx_gpio` will put the result into Local0, rather than
emitting it as a byte so adjust the function accordingly.
Change-Id: I13263d479d1a4520abaf1b6b38514d021e7d4dc9
Signed-off-by: Sean Rhodes <sean(a)starlabs.systems>
---
M src/drivers/usb/acpi/intel_bluetooth.c
1 file changed, 5 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/84989/4
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Change subject: mb/google/fatcat: Update Soundwire codec address based on devicetree
......................................................................
Patch Set 3:
(2 comments)
File src/mainboard/google/fatcat/variants/fatcat/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/85440/comment/41ab6ded_b4b27353?us… :
PS3, Line 627: register "alc711_address[1].part_id" = "0x0722"
Move it next to `register register "desc" = ""Headset Codec"` line. There is no probe based DT initialization. All the DT structures are initialized statically. Probe just probes and enables the devices at run-time.
https://review.coreboot.org/c/coreboot/+/85440/comment/d65afef9_e9742b2c?us… :
PS3, Line 632: register "alc711_address[3].part_id" = "0x0721"
Same comment as above.
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Change subject: util/amdfwtool: Add binary parsing
......................................................................
Patch Set 8:
(1 comment)
File util/amdfwtool/amdfwtool.c:
https://review.coreboot.org/c/coreboot/+/84373/comment/0b8ab5f0_081021b8?us… :
PS8, Line 324: { .type = AMD_BIOS_APOB_NV, .level = BDT_BOTH },
> Are you sure this is required? Or maybe it became a requirement on glinda? IIRC we've traditionall […]
iirc glinda doesn't use/have a level 1 bios directory table
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