coreboot-gerrit December 2024

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[S] Change in coreboot[main]: mb/google/brya/var/uldrenite: Generate RAM ID and SPD file
by John Su (Code Review) 03 Dec '24

03 Dec '24

John Su has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85447?usp=email ) Change subject: mb/google/brya/var/uldrenite: Generate RAM ID and SPD file ...................................................................... mb/google/brya/var/uldrenite: Generate RAM ID and SPD file Add the support RAM parts for uldrenite. Here is the ram part number list: DRAM Part Name ID to assign H9JCNNNBK3MLYR-N6E 0 (0000) K3KL6L60GM-MGCT 1 (0001) K3KL8L80CM-MGCT 2 (0010) MT62F1G32D2DS-026 WT:B 2 (0010) H58G56CK8BX146 3 (0011) BUG=b:380789023 BRANCH=None TEST=emerge-nissa coreboot Change-Id: I8003f693e1d8fa049a0e508078ce29b5bb39f2ef Signed-off-by: John Su <john_su(a)compal.corp-partner.google.com> --- M src/mainboard/google/brya/variants/uldrenite/memory/Makefile.mk M src/mainboard/google/brya/variants/uldrenite/memory/dram_id.generated.txt M src/mainboard/google/brya/variants/uldrenite/memory/mem_parts_used.txt 3 files changed, 15 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/85447/1 diff --git a/src/mainboard/google/brya/variants/uldrenite/memory/Makefile.mk b/src/mainboard/google/brya/variants/uldrenite/memory/Makefile.mk index d92ecdc..20c07f5 100644 --- a/src/mainboard/google/brya/variants/uldrenite/memory/Makefile.mk +++ b/src/mainboard/google/brya/variants/uldrenite/memory/Makefile.mk @@ -3,4 +3,8 @@ # Generated by: # util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/uldrenite/memory src/mainboard/google/brya/variants/uldrenite/memory/mem_parts_used.txt -SPD_SOURCES = placeholder +SPD_SOURCES = +SPD_SOURCES += spd/lp5/set-0/spd-1.hex # ID = 0(0b0000) Parts = H9JCNNNBK3MLYR-N6E +SPD_SOURCES += spd/lp5/set-0/spd-9.hex # ID = 1(0b0001) Parts = K3KL6L60GM-MGCT +SPD_SOURCES += spd/lp5/set-0/spd-7.hex # ID = 2(0b0010) Parts = K3KL8L80CM-MGCT, MT62F1G32D2DS-026 WT:B +SPD_SOURCES += spd/lp5/set-0/spd-11.hex # ID = 3(0b0011) Parts = H58G56CK8BX146 diff --git a/src/mainboard/google/brya/variants/uldrenite/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/uldrenite/memory/dram_id.generated.txt index 7cbcfb3..d1fe3d9 100644 --- a/src/mainboard/google/brya/variants/uldrenite/memory/dram_id.generated.txt +++ b/src/mainboard/google/brya/variants/uldrenite/memory/dram_id.generated.txt @@ -4,3 +4,8 @@ # util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/uldrenite/memory src/mainboard/google/brya/variants/uldrenite/memory/mem_parts_used.txt DRAM Part Name ID to assign +H9JCNNNBK3MLYR-N6E 0 (0000) +K3KL6L60GM-MGCT 1 (0001) +K3KL8L80CM-MGCT 2 (0010) +MT62F1G32D2DS-026 WT:B 2 (0010) +H58G56CK8BX146 3 (0011) diff --git a/src/mainboard/google/brya/variants/uldrenite/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/uldrenite/memory/mem_parts_used.txt index 2499005..3f143af 100644 --- a/src/mainboard/google/brya/variants/uldrenite/memory/mem_parts_used.txt +++ b/src/mainboard/google/brya/variants/uldrenite/memory/mem_parts_used.txt @@ -9,3 +9,8 @@ # See util/spd_tools/README.md for more details and instructions. # Part Name +H9JCNNNBK3MLYR-N6E +K3KL6L60GM-MGCT +K3KL8L80CM-MGCT +MT62F1G32D2DS-026 WT:B +H58G56CK8BX146 -- To view, visit https://review.coreboot.org/c/coreboot/+/85447?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8003f693e1d8fa049a0e508078ce29b5bb39f2ef Gerrit-Change-Number: 85447 Gerrit-PatchSet: 1 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com>

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[XS] Change in coreboot[main]: soc/mediatek/mt8195: Fix SCP register address
by Yu-Ping Wu (Code Review) 03 Dec '24

03 Dec '24

Yu-Ping Wu has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85436?usp=email ) Change subject: soc/mediatek/mt8195: Fix SCP register address ...................................................................... soc/mediatek/mt8195: Fix SCP register address The parentheses are missing in the mtk_scp macro definition. The only usage is SET32_BITFIELDS(&mtk_scp->scp_clk_on_ctrl, SCP_CLK_ON_CTRL, 1); I guess that bit is already set by default, so there's no ULPOSC clock issue found so far. BUG=none TEST=none BRANCH=cherry Change-Id: I2dbb5c465ee60f0c4dce8ff77b8d3a39db42e4f5 Signed-off-by: Yu-Ping Wu <yupingso(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85436 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yidi Lin <yidilin(a)google.com> --- M src/soc/mediatek/mt8195/include/soc/pmif.h 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Yidi Lin: Looks good to me, approved diff --git a/src/soc/mediatek/mt8195/include/soc/pmif.h b/src/soc/mediatek/mt8195/include/soc/pmif.h index cec23d7..530b31e 100644 --- a/src/soc/mediatek/mt8195/include/soc/pmif.h +++ b/src/soc/mediatek/mt8195/include/soc/pmif.h @@ -134,7 +134,7 @@ check_member(mtk_scp_regs, scp_clk_on_ctrl, 0x6C); -#define mtk_scp ((struct mtk_scp_regs *)SCP_CFG_BASE + 0x21000) +#define mtk_scp ((struct mtk_scp_regs *)(SCP_CFG_BASE + 0x21000)) enum { PMIF_TARGET_FREQ_MHZ = 248, -- To view, visit https://review.coreboot.org/c/coreboot/+/85436?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2dbb5c465ee60f0c4dce8ff77b8d3a39db42e4f5 Gerrit-Change-Number: 85436 Gerrit-PatchSet: 2 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XL] Change in coreboot[main]: soc/mediatek/mt8196: Add PMIF and PMIC driver support
by Jarried Lin (Code Review) 03 Dec '24

03 Dec '24

Attention is currently required from: Hung-Te Lin, Jarried Lin, Paul Menzel, Yidi Lin, Yu-Ping Wu. Hello Hope Wang, Hung-Te Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85126?usp=email to look at the new patch set (#12). Change subject: soc/mediatek/mt8196: Add PMIF and PMIC driver support ...................................................................... soc/mediatek/mt8196: Add PMIF and PMIC driver support Implement PMIF driver for communication between SoC and PMIC. Develop SPMI driver for communication over the SPMI bus. Add necessary configurations and base addresses to support PMIF and fix low probability boot failure issue. TEST=build pass BUG=b:317009620, b:361174333 Change-Id: I232015f45735ee5278b09d0352410617a1565177 Signed-off-by: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> --- M src/soc/mediatek/mt8196/Makefile.mk M src/soc/mediatek/mt8196/include/soc/addressmap.h A src/soc/mediatek/mt8196/include/soc/pmif.h A src/soc/mediatek/mt8196/include/soc/spm.h A src/soc/mediatek/mt8196/pmif_clk.c A src/soc/mediatek/mt8196/pmif_init.c A src/soc/mediatek/mt8196/pmif_spmi.c 7 files changed, 1,750 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/85126/12 -- To view, visit https://review.coreboot.org/c/coreboot/+/85126?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I232015f45735ee5278b09d0352410617a1565177 Gerrit-Change-Number: 85126 Gerrit-PatchSet: 12 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com>

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[XL] Change in coreboot[main]: soc/mediatek/mt8196: Add PMIF and PMIC driver support
by Jarried Lin (Code Review) 03 Dec '24

03 Dec '24

Attention is currently required from: Hung-Te Lin, Jarried Lin, Paul Menzel, Yidi Lin, Yu-Ping Wu. Hello Hope Wang, Hung-Te Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85126?usp=email to look at the new patch set (#11). Change subject: soc/mediatek/mt8196: Add PMIF and PMIC driver support ...................................................................... soc/mediatek/mt8196: Add PMIF and PMIC driver support Implement PMIF driver for communication between SoC and PMIC. Develop SPMI driver for communication over the SPMI bus. Add necessary configurations and base addresses to support PMIF. TEST=build pass BUG=b:317009620 Change-Id: I232015f45735ee5278b09d0352410617a1565177 Signed-off-by: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> --- M src/soc/mediatek/mt8196/Makefile.mk M src/soc/mediatek/mt8196/include/soc/addressmap.h A src/soc/mediatek/mt8196/include/soc/pmif.h A src/soc/mediatek/mt8196/include/soc/spm.h A src/soc/mediatek/mt8196/pmif_clk.c A src/soc/mediatek/mt8196/pmif_init.c A src/soc/mediatek/mt8196/pmif_spmi.c 7 files changed, 1,750 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/85126/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/85126?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I232015f45735ee5278b09d0352410617a1565177 Gerrit-Change-Number: 85126 Gerrit-PatchSet: 11 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com>

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[XL] Change in coreboot[main]: soc/mediatek/mt8196: Add PMIF and PMIC driver support
by Jarried Lin (Code Review) 03 Dec '24

03 Dec '24

Attention is currently required from: Hung-Te Lin, Jarried Lin, Paul Menzel, Yidi Lin, Yu-Ping Wu. Hello Hope Wang, Hung-Te Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85126?usp=email to look at the new patch set (#10). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: soc/mediatek/mt8196: Add PMIF and PMIC driver support ...................................................................... soc/mediatek/mt8196: Add PMIF and PMIC driver support Implement PMIF driver for communication between SoC and PMIC. Develop SPMI driver for communication over the SPMI bus. Add necessary configurations and base addresses to support PMIF. TEST=build pass BUG=b:317009620 Change-Id: I232015f45735ee5278b09d0352410617a1565177 Signed-off-by: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> --- M src/soc/mediatek/mt8196/Makefile.mk M src/soc/mediatek/mt8196/include/soc/addressmap.h A src/soc/mediatek/mt8196/include/soc/pmif.h A src/soc/mediatek/mt8196/include/soc/spm.h A src/soc/mediatek/mt8196/pmif_clk.c A src/soc/mediatek/mt8196/pmif_init.c A src/soc/mediatek/mt8196/pmif_spmi.c 7 files changed, 1,749 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/85126/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/85126?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I232015f45735ee5278b09d0352410617a1565177 Gerrit-Change-Number: 85126 Gerrit-PatchSet: 10 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com>

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[XL] Change in coreboot[main]: soc/mediatek/mt8196: Add PMIF and PMIC driver support
by Jarried Lin (Code Review) 03 Dec '24

03 Dec '24

Attention is currently required from: Hung-Te Lin, Jarried Lin, Paul Menzel, Yidi Lin, Yu-Ping Wu. Hello Hope Wang, Hung-Te Lin, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85126?usp=email to look at the new patch set (#9). The following approvals got outdated and were removed: Code-Review+2 by Yidi Lin, Verified+1 by build bot (Jenkins) The change is no longer submittable: Code-Review and Verified are unsatisfied now. Change subject: soc/mediatek/mt8196: Add PMIF and PMIC driver support ...................................................................... soc/mediatek/mt8196: Add PMIF and PMIC driver support Implement PMIF driver for communication between SoC and PMIC. Develop SPMI driver for communication over the SPMI bus. Add necessary configurations and base addresses to support PMIF. TEST=build pass BUG=b:317009620 Change-Id: I232015f45735ee5278b09d0352410617a1565177 Signed-off-by: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> --- M src/soc/mediatek/mt8196/Makefile.mk M src/soc/mediatek/mt8196/include/soc/addressmap.h A src/soc/mediatek/mt8196/include/soc/pmif.h A src/soc/mediatek/mt8196/include/soc/spm.h A src/soc/mediatek/mt8196/pmif_clk.c A src/soc/mediatek/mt8196/pmif_init.c A src/soc/mediatek/mt8196/pmif_spmi.c 7 files changed, 1,749 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/85126/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/85126?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I232015f45735ee5278b09d0352410617a1565177 Gerrit-Change-Number: 85126 Gerrit-PatchSet: 9 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com>

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[XS] Change in coreboot[main]: soc/mediatek/mt8195: Fix SCP register address
by Yidi Lin (Code Review) 03 Dec '24

03 Dec '24

Attention is currently required from: Hung-Te Lin, Yu-Ping Wu. Yidi Lin has posted comments on this change by Yu-Ping Wu. ( https://review.coreboot.org/c/coreboot/+/85436?usp=email ) Change subject: soc/mediatek/mt8195: Fix SCP register address ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85436?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2dbb5c465ee60f0c4dce8ff77b8d3a39db42e4f5 Gerrit-Change-Number: 85436 Gerrit-PatchSet: 1 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Tue, 03 Dec 2024 09:37:08 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: mb/google/rauru: Add 2nd source TAS2563 amps to support beep
by Yidi Lin (Code Review) 03 Dec '24

03 Dec '24

Yidi Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85360?usp=email ) Change subject: mb/google/rauru: Add 2nd source TAS2563 amps to support beep ...................................................................... mb/google/rauru: Add 2nd source TAS2563 amps to support beep Derive the audio amplifier from FW_CONFIG, and set up I2C and I2S for TAS2563. Also pass the corresponding GPIO(s) to the payload. TEST=build pass and driver init ok BUG=b:357969183 Change-Id: I10cba7964d3847f2a74341b3130ff1e7bfd8d37a Signed-off-by: Darren Ye <darren.ye(a)mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85360 Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yidi Lin <yidilin(a)google.com> --- M src/mainboard/google/rauru/chromeos.c M src/mainboard/google/rauru/devicetree.cb M src/mainboard/google/rauru/gpio.h M src/mainboard/google/rauru/mainboard.c 4 files changed, 54 insertions(+), 2 deletions(-) Approvals: Yu-Ping Wu: Looks good to me, approved Yidi Lin: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/google/rauru/chromeos.c b/src/mainboard/google/rauru/chromeos.c index 7f2fd05..f530396 100644 --- a/src/mainboard/google/rauru/chromeos.c +++ b/src/mainboard/google/rauru/chromeos.c @@ -2,6 +2,7 @@ #include <boot/coreboot_tables.h> #include <drivers/tpm/cr50.h> +#include <fw_config.h> #include <gpio.h> #include "gpio.h" @@ -24,9 +25,7 @@ { struct lb_gpio chromeos_gpios[] = { { GPIO_XHCI_INIT_DONE.id, ACTIVE_HIGH, -1, "XHCI init done" }, - { GPIO_EN_SPKR.id, ACTIVE_HIGH, -1, "speaker enable" }, { GPIO_EC_AP_INT_ODL.id, ACTIVE_LOW, -1, "EC interrupt" }, - { GPIO_BEEP_ON_OD.id, ACTIVE_HIGH, -1, "beep enable" }, { GPIO_GSC_AP_INT_ODL.id, ACTIVE_HIGH, -1, "TPM interrupt" }, }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); @@ -37,6 +36,20 @@ }; lb_add_gpios(gpios, sd_card_gpios, ARRAY_SIZE(sd_card_gpios)); } + + struct lb_gpio nau8318_gpios[] = { + {GPIO_EN_SPKR.id, ACTIVE_HIGH, -1, "speaker enable"}, + {GPIO_BEEP_ON_OD.id, ACTIVE_HIGH, -1, "beep enable"}, + }; + + struct lb_gpio smartamp_gpios[] = { + {GPIO_EN_SPKR.id, ACTIVE_LOW, -1, "speaker reset"}, + }; + + if (fw_config_probe(FW_CONFIG(AUDIO_AMP, AMP_TAS2563))) + lb_add_gpios(gpios, smartamp_gpios, ARRAY_SIZE(smartamp_gpios)); + else + lb_add_gpios(gpios, nau8318_gpios, ARRAY_SIZE(nau8318_gpios)); } int cr50_plat_irq_status(void) diff --git a/src/mainboard/google/rauru/devicetree.cb b/src/mainboard/google/rauru/devicetree.cb index df65b3f..7f6dc59 100644 --- a/src/mainboard/google/rauru/devicetree.cb +++ b/src/mainboard/google/rauru/devicetree.cb @@ -1,5 +1,12 @@ ## SPDX-License-Identifier: GPL-2.0-only +fw_config + field AUDIO_AMP 28 29 + option AMP_NAU8318 0 + option AMP_TAS2563 1 + end +end + chip soc/mediatek/mt8196 device cpu_cluster 0 on end diff --git a/src/mainboard/google/rauru/gpio.h b/src/mainboard/google/rauru/gpio.h index d513dceab..6191e05 100644 --- a/src/mainboard/google/rauru/gpio.h +++ b/src/mainboard/google/rauru/gpio.h @@ -16,6 +16,10 @@ #define GPIO_AP_FP_FW_UP_STRAP GPIO(EINT27) #define GPIO_EN_PWR_FP GPIO(PERIPHERAL_EN3) +#define GPIO_I2SI4_BCK GPIO(I2SIN1_BCK) +#define GPIO_I2SI4_LRCK GPIO(I2SIN1_LRCK) +#define GPIO_I2SO4_D0 GPIO(I2SOUT1_DO) + void setup_chromeos_gpios(void); #endif diff --git a/src/mainboard/google/rauru/mainboard.c b/src/mainboard/google/rauru/mainboard.c index 94a257f..9c238c7 100644 --- a/src/mainboard/google/rauru/mainboard.c +++ b/src/mainboard/google/rauru/mainboard.c @@ -2,14 +2,41 @@ #include <console/console.h> #include <device/device.h> +#include <fw_config.h> #include <gpio.h> +#include <soc/addressmap.h> #include <soc/bl31.h> #include <soc/dpm_v2.h> +#include <soc/gpio_common.h> +#include <soc/i2c.h> #include <soc/pcie.h> #include <soc/usb.h> #include "gpio.h" +#define AFE_SE_SECURE_CON1 (AUDIO_BASE + 0x5634) + +static void configure_i2s(void) +{ + /* Switch to normal mode */ + write32p(AFE_SE_SECURE_CON1, 0x0); + + /* SoC I2S */ + gpio_set_mode(GPIO_I2SI4_BCK, GPIO_FUNC(I2SIN1_BCK, I2SIN4_BCK)); + gpio_set_mode(GPIO_I2SI4_LRCK, GPIO_FUNC(I2SIN1_LRCK, I2SIN4_LRCK)); + gpio_set_mode(GPIO_I2SO4_D0, GPIO_FUNC(I2SOUT1_DO, I2SOUT4_DATA0)); +} + +static void configure_audio(void) +{ + if (fw_config_probe(FW_CONFIG(AUDIO_AMP, AMP_TAS2563))) { + mtk_i2c_bus_init(I2C3, I2C_SPEED_FAST); + configure_i2s(); + } + + printk(BIOS_INFO, "%s: done\n", __func__); +} + static void power_on_fpmcu(void) { /* Power on the fingerprint MCU */ @@ -26,6 +53,7 @@ { setup_usb_host(); power_on_fpmcu(); + configure_audio(); if (dpm_init()) printk(BIOS_ERR, "dpm init failed, DVFS may not work\n"); -- To view, visit https://review.coreboot.org/c/coreboot/+/85360?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I10cba7964d3847f2a74341b3130ff1e7bfd8d37a Gerrit-Change-Number: 85360 Gerrit-PatchSet: 7 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Darren Ye <darren.ye(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: soc/mediatek/mt8196: Add audio base address definition
by Yidi Lin (Code Review) 03 Dec '24

03 Dec '24

Yidi Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85361?usp=email ) ( 5 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/mediatek/mt8196: Add audio base address definition ...................................................................... soc/mediatek/mt8196: Add audio base address definition Add audio base address definition. TEST=build pass BUG=b:357969183 Change-Id: I07d272fddfe50e73adc6f4c7d401f3391b0c145d Signed-off-by: Darren Ye <darren.ye(a)mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85361 Reviewed-by: Yidi Lin <yidilin(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/soc/mediatek/mt8196/include/soc/addressmap.h 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: Yu-Ping Wu: Looks good to me, approved build bot (Jenkins): Verified Yidi Lin: Looks good to me, approved diff --git a/src/soc/mediatek/mt8196/include/soc/addressmap.h b/src/soc/mediatek/mt8196/include/soc/addressmap.h index 24cea8f..6130e24 100644 --- a/src/soc/mediatek/mt8196/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8196/include/soc/addressmap.h @@ -139,6 +139,7 @@ UFSHCI_BASE = IO_PHYS + 0x06810000, SSR_TOP_BASE = IO_PHYS + 0x08000000, APINFRA_SSR_AO_DEBUG_BASE = IO_PHYS + 0x080F1000, + AUDIO_BASE = IO_PHYS + 0x0A110000, VLPCFG_BASE = IO_PHYS + 0x0C001000, SCP_BASE = IO_PHYS + 0x0C004000, SCP_PBUS_BASE = IO_PHYS + 0x0C00D000, -- To view, visit https://review.coreboot.org/c/coreboot/+/85361?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I07d272fddfe50e73adc6f4c7d401f3391b0c145d Gerrit-Change-Number: 85361 Gerrit-PatchSet: 7 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Darren Ye <darren.ye(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

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[M] Change in coreboot[main]: soc/mediatek/mt8196: Add booker driver
by Yidi Lin (Code Review) 03 Dec '24

03 Dec '24

Attention is currently required from: Dehui Sun, Hung-Te Lin, Jarried Lin, Paul Menzel, Yu-Ping Wu. Yidi Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85362?usp=email ) Change subject: soc/mediatek/mt8196: Add booker driver ...................................................................... Patch Set 9: (5 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/85362/comment/a4b5fcb5_8c177b2d?us… : PS9, Line 9: The MTK booker The MediaTek booker (the customized ARM CI-700) https://review.coreboot.org/c/coreboot/+/85362/comment/b930f878_0828526c?us… : PS9, Line 15: it can `it needs to` ? https://review.coreboot.org/c/coreboot/+/85362/comment/c1d3b805_bbd82d55?us… : PS9, Line 15: it can : set bit[3] (disable_cmo_prop) to 0 in the por_sbsx_cfg_ctl register of : each SBSX node. Does it mean that we need to set the bit 3 (disable_cmo_prop) to `0` in order to propagate the CMO command from DSU ? File src/soc/mediatek/mt8196/booker.c: https://review.coreboot.org/c/coreboot/+/85362/comment/0c93ef0d_a009b184?us… : PS9, Line 11: MCUSYS_PAR_WRAP_BASE just use `MCUCFG_BASE` https://review.coreboot.org/c/coreboot/+/85362/comment/db410e5e_dca3d215?us… : PS9, Line 13: 0x00450000 + 0x0A00 please define this -- To view, visit https://review.coreboot.org/c/coreboot/+/85362?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6bde1e20137890addf18b23b47f17b1f63824b22 Gerrit-Change-Number: 85362 Gerrit-PatchSet: 9 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Dehui Sun <dehui.sun(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Dehui Sun <dehui.sun(a)mediatek.corp-partner.google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Tue, 03 Dec 2024 08:53:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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