coreboot-gerrit December 2024

coreboot-gerrit@coreboot.org

1 participants
3018 discussions

[S] Change in coreboot[main]: mb/trulo/var/uldrenite: Configure audio (max9360a, rt5682)
by John Su (Code Review) 16 Dec '24

16 Dec '24

Attention is currently required from: Dinesh Gehlot, Jayvik Desai, Nick Vaccaro, Paul Menzel. Hello Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85600?usp=email to look at the new patch set (#5). Change subject: mb/trulo/var/uldrenite: Configure audio (max9360a, rt5682) ...................................................................... mb/trulo/var/uldrenite: Configure audio (max9360a, rt5682) 1. Enable HDA driver 2. Add spkr_tplg = max98360a 3. Add jack_tplg = rt5682 BUG=b:380789023 TEST=emerge-nissa coreboot Change-Id: I8f78a8641de23eadb03348a31574045702b40554 Signed-off-by: John Su <john_su(a)compal.corp-partner.google.com> --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/variants/uldrenite/Makefile.mk M src/mainboard/google/brya/variants/uldrenite/overridetree.cb 3 files changed, 18 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/85600/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/85600?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8f78a8641de23eadb03348a31574045702b40554 Gerrit-Change-Number: 85600 Gerrit-PatchSet: 5 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org>

1 0

[S] Change in coreboot[main]: mb/trulo/var/uldrenite: Configure audio (max9360a, rt5682) 1. Enable ...
by John Su (Code Review) 16 Dec '24

16 Dec '24

Attention is currently required from: Dinesh Gehlot, Jayvik Desai, Nick Vaccaro, Paul Menzel. John Su has posted comments on this change by John Su. ( https://review.coreboot.org/c/coreboot/+/85600?usp=email ) Change subject: mb/trulo/var/uldrenite: Configure audio (max9360a, rt5682) 1. Enable HDA driver 2. Add spkr_tplg = max98360a 3. Add jack_tplg = rt5682 ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/85600/comment/762a6488_2ca031ff?us… : PS3, Line 7: Configure audio > Maybe: […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/85600?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8f78a8641de23eadb03348a31574045702b40554 Gerrit-Change-Number: 85600 Gerrit-PatchSet: 4 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Mon, 16 Dec 2024 07:07:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

1 0

[S] Change in coreboot[main]: mb/trulo/var/uldrenite: Configure audio (max9360a, rt5682) 1. Enable ...
by John Su (Code Review) 16 Dec '24

16 Dec '24

Attention is currently required from: Dinesh Gehlot, Jayvik Desai, John Su, Nick Vaccaro. Hello Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85600?usp=email to look at the new patch set (#4). Change subject: mb/trulo/var/uldrenite: Configure audio (max9360a, rt5682) 1. Enable HDA driver 2. Add spkr_tplg = max98360a 3. Add jack_tplg = rt5682 ...................................................................... mb/trulo/var/uldrenite: Configure audio (max9360a, rt5682) 1. Enable HDA driver 2. Add spkr_tplg = max98360a 3. Add jack_tplg = rt5682 BUG=b:380789023 TEST=emerge-nissa coreboot Change-Id: I8f78a8641de23eadb03348a31574045702b40554 Signed-off-by: John Su <john_su(a)compal.corp-partner.google.com> --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/variants/uldrenite/Makefile.mk M src/mainboard/google/brya/variants/uldrenite/overridetree.cb 3 files changed, 18 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/85600/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/85600?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8f78a8641de23eadb03348a31574045702b40554 Gerrit-Change-Number: 85600 Gerrit-PatchSet: 4 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org>

1 0

[XS] Change in coreboot[main]: mb/google/brox: Enable LPC Generic Memory Range on Brox [WIP]
by Subrata Banik (Code Review) 16 Dec '24

16 Dec '24

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85604?usp=email ) Change subject: mb/google/brox: Enable LPC Generic Memory Range on Brox [WIP] ...................................................................... mb/google/brox: Enable LPC Generic Memory Range on Brox [WIP] This change enables the LPC Generic Memory Range (GMR) feature for the Brox platform by selecting `EC_GOOGLE_CHROMEEC_LPC_GENERIC_MEMORY_RANGE` in the Kconfig file. This allows the Chrome EC to expose the LPC GMR address range to the OS layer. Change-Id: If5b63e897a72eddf5eba1c94699c65ef90eb8b54 Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/mainboard/google/brox/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/85604/1 diff --git a/src/mainboard/google/brox/Kconfig b/src/mainboard/google/brox/Kconfig index 11bcfe6..03826ad 100644 --- a/src/mainboard/google/brox/Kconfig +++ b/src/mainboard/google/brox/Kconfig @@ -15,6 +15,7 @@ select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_BOARDID select EC_GOOGLE_CHROMEEC_ESPI + select EC_GOOGLE_CHROMEEC_LPC_GENERIC_MEMORY_RANGE select EC_GOOGLE_CHROMEEC_SKUID select ENABLE_TCSS_USB_DETECTION if !(SOC_INTEL_TCSS_USE_PDC_PMC_USBC_MUX_CONFIGURATION || CHROMEOS) select FW_CONFIG -- To view, visit https://review.coreboot.org/c/coreboot/+/85604?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If5b63e897a72eddf5eba1c94699c65ef90eb8b54 Gerrit-Change-Number: 85604 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com>

1 0

[S] Change in coreboot[main]: ec/google/chromeec: Publish LPC GMR address range via CREC _CRS
by Subrata Banik (Code Review) 16 Dec '24

16 Dec '24

Attention is currently required from: Boris Mittelberg, Caveh Jalali. Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85603?usp=email ) Change subject: ec/google/chromeec: Publish LPC GMR address range via CREC _CRS ...................................................................... ec/google/chromeec: Publish LPC GMR address range via CREC _CRS This change allows the Chrome EC (CREC) ACPI device to publish the LPC Generic Memory Range (GMR) address range using the _CRS method. The Google CREC driver can now parse this information to determine the MMIO address map, enabling access to the LPC GMR register space. This addresses the issue where the CREC driver was unable to automatically determine the LPC GMR base address. Change-Id: Ib3ea3e2a482f9eceaa8c15e38b7e708b156bc978 Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/ec/google/chromeec/Kconfig M src/ec/google/chromeec/acpi/cros_ec.asl 2 files changed, 31 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/85603/1 diff --git a/src/ec/google/chromeec/Kconfig b/src/ec/google/chromeec/Kconfig index f0418ff..eae1fc6 100644 --- a/src/ec/google/chromeec/Kconfig +++ b/src/ec/google/chromeec/Kconfig @@ -167,6 +167,12 @@ If unsure, say N. +config EC_GOOGLE_CHROMEEC_LPC_GENERIC_MEMORY_RANGE + def_bool n + help + Select this option to access LPC GMR (Generic Memory Range) Register to + implement MMIO based communication between EC and AP firmware. + endif # EC_GOOGLE_CHROMEEC source "src/ec/google/chromeec/*/Kconfig" diff --git a/src/ec/google/chromeec/acpi/cros_ec.asl b/src/ec/google/chromeec/acpi/cros_ec.asl index 5b5229b..85cadd1 100644 --- a/src/ec/google/chromeec/acpi/cros_ec.asl +++ b/src/ec/google/chromeec/acpi/cros_ec.asl @@ -1,5 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#if CONFIG(EC_GOOGLE_CHROMEEC_LPC_GENERIC_MEMORY_RANGE) +#define LPC_GMR_SIZE 0x10000 +#endif + Device (CREC) { Name (_HID, "GOOG0004") @@ -19,26 +23,32 @@ #define EC_SYNC_SHARE_TYPE Exclusive #endif -#ifdef EC_ENABLE_SYNC_IRQ - Name (_CRS, ResourceTemplate () +#if defined(EC_ENABLE_SYNC_IRQ) || defined(EC_ENABLE_SYNC_IRQ_GPIO) + Method (_CRS, 0x0, NotSerialized) { - Interrupt (ResourceConsumer, Level, ActiveLow, - EC_SYNC_SHARE_TYPE) + Name (RBUF, ResourceTemplate() { - EC_SYNC_IRQ - } - }) +#ifdef EC_ENABLE_SYNC_IRQ + Interrupt (ResourceConsumer, Level, ActiveLow, EC_SYNC_SHARE_TYPE) { EC_SYNC_IRQ } #endif #ifdef EC_ENABLE_SYNC_IRQ_GPIO - Name (_CRS, ResourceTemplate () - { - GpioInt (Level, ActiveLow, EC_SYNC_SHARE_TYPE, PullDefault, - 0x0000, "\\_SB.GPIO", 0x00, ResourceConsumer, ,) - { - EC_SYNC_IRQ - } - }) + GpioInt (Level, ActiveLow, EC_SYNC_SHARE_TYPE, PullDefault, + 0x0000, "\\_SB.GPIO", 0x00, ResourceConsumer, ,) + { + EC_SYNC_IRQ + } +#endif + +#if CONFIG(EC_GOOGLE_CHROMEEC_LPC_GENERIC_MEMORY_RANGE) + Memory32Fixed (ReadWrite, 0, 0, MADR) + CreateDWordField (RBUF, MADR._BAS, BAS0) + CreateDWordField (RBUF, MADR._LEN, LEN0) + BAS0 = \_SB.PCI0.LPCB.GLGM() + LEN0 = LPC_GMR_SIZE +#endif + Return (RBUF) + } #endif #ifdef EC_ENABLE_MKBP_DEVICE -- To view, visit https://review.coreboot.org/c/coreboot/+/85603?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib3ea3e2a482f9eceaa8c15e38b7e708b156bc978 Gerrit-Change-Number: 85603 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Boris Mittelberg <bmbm(a)google.com>

1 0

[S] Change in coreboot[main]: soc/intel/cmn/acpi: Add ACPI method to get LGMR address
by Subrata Banik (Code Review) 16 Dec '24

16 Dec '24

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85602?usp=email ) Change subject: soc/intel/cmn/acpi: Add ACPI method to get LGMR address ...................................................................... soc/intel/cmn/acpi: Add ACPI method to get LGMR address This patch adds an ACPI method to get the LPC Generic Memory Range (LGMR) address. This is necessary for platforms that need to access the LGMR from OS driver. The new method, called GLGM, reads the LGMR address from the LPC PCI configuration space (offset 0x98) and returns it as a 32-bit value. BUG=b:354066052 TEST=Able to build and boot google/brox. Change-Id: I4322cee2c608e550e233c45c68958e8a4046c361 Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/soc/intel/common/block/acpi/acpi/lpc.asl 1 file changed, 16 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/85602/1 diff --git a/src/soc/intel/common/block/acpi/acpi/lpc.asl b/src/soc/intel/common/block/acpi/acpi/lpc.asl index c4a7dd3..3e8f5a5 100644 --- a/src/soc/intel/common/block/acpi/acpi/lpc.asl +++ b/src/soc/intel/common/block/acpi/acpi/lpc.asl @@ -9,6 +9,22 @@ Name (_ADR, 0x001f0000) Name (_DDN, "LPC Bus Device") + OperationRegion (LPCP, PCI_Config, 0x00, 0x100) + Field (LPCP, DWordAcc, NoLock, Preserve) + { + Offset(0x98), /* LGMR */ + LGEN, 1, /* Enable */ + , 15, + LADR, 16, /* MADDR [31:16] */ + } + + /* Get LGMR */ + Method (GLGM, 0, Serialized) + { + Local0 = LADR << 16 + Return (Local0) + } + /* DMA Controller */ Device (DMAC) { -- To view, visit https://review.coreboot.org/c/coreboot/+/85602?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4322cee2c608e550e233c45c68958e8a4046c361 Gerrit-Change-Number: 85602 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com>

1 0

[XL] Change in coreboot[main]: soc/meidatek/mt8196: Add SPM loader
by Yu-Ping Wu (Code Review) 16 Dec '24

16 Dec '24

Attention is currently required from: Ccong Chen, Hung-Te Lin, Wenzhen Yu. Yu-Ping Wu has posted comments on this change by Ccong Chen. ( https://review.coreboot.org/c/coreboot/+/85599?usp=email ) Change subject: soc/meidatek/mt8196: Add SPM loader ...................................................................... Patch Set 1: (27 comments) File src/soc/mediatek/common/Kconfig: https://review.coreboot.org/c/coreboot/+/85599/comment/e069fada_d0f5aafe?us… : PS1, Line 122: spm version2 SPM version 2 File src/soc/mediatek/common/spm.c: https://review.coreboot.org/c/coreboot/+/85599/comment/45085fe6_47b49329?us… : PS1, Line 71: /* In the new SOC design, this part has been simplified */ Remove this comment (same below). The difference should be explained in the commit message and the Kconfig file instead. File src/soc/mediatek/mt8196/include/soc/addressmap.h: https://review.coreboot.org/c/coreboot/+/85599/comment/0425c294_9b555ef1?us… : PS1, Line 146: SCP_BASE Just use `SPM_BASE`. Also see CB:85521. File src/soc/mediatek/mt8196/include/soc/pll.h: https://review.coreboot.org/c/coreboot/+/85599/comment/c238f838_ea691eb5?us… : PS1, Line 140: _0 Why `_0`? How many config registers do we have? If we have 8, please write `clk_scp_cfg[8]` here and remove `reserved3`. File src/soc/mediatek/mt8196/include/soc/spm.h: https://review.coreboot.org/c/coreboot/+/85599/comment/d4de2bbe_a77322a9?us… : PS1, Line 12: 0x10001060 `(INFRACFG_AO_BASE + ...)` https://review.coreboot.org/c/coreboot/+/85599/comment/a780e9c6_e3db69ea?us… : PS1, Line 13: 0x1c001108 Should we define a structure for `VLPCFG_BASE`? https://review.coreboot.org/c/coreboot/+/85599/comment/3cea9617_7537c318?us… : PS1, Line 69: 0x003FFE20 Keep it lower case in this patch. We should change all of these to upper case in a separate patch. https://review.coreboot.org/c/coreboot/+/85599/comment/ce5f0965_72678e4e?us… : PS1, Line 85: PCM_WDT_TIMEOUT What's the unit? https://review.coreboot.org/c/coreboot/+/85599/comment/7fdd53dd_e9950655?us… : PS1, Line 87: AP_WDT_TIMEOUT_SUSPEND Append unit such as `_MS`. https://review.coreboot.org/c/coreboot/+/85599/comment/ab3de88e_ae1242bd?us… : PS1, Line 201: u8 reg_apifr_mem_apsrc_req_mask_b; Is the original register definition wrong? If that's the case, please split the "fixing" part into a separate patch. https://review.coreboot.org/c/coreboot/+/85599/comment/499f236b_68660876?us… : PS1, Line 635: u32 reserved0[5]; Revert these unrelated changes. File src/soc/mediatek/mt8196/spm.c: https://review.coreboot.org/c/coreboot/+/85599/comment/2bda3f63_6c18d874?us… : PS1, Line 10: one space only https://review.coreboot.org/c/coreboot/+/85599/comment/0c7b549b_727d22c1?us… : PS1, Line 17: remove extra blank lnie. https://review.coreboot.org/c/coreboot/+/85599/comment/307d4001_5b343027?us… : PS1, Line 26: /* TODO: replace with common regs structure if they have been defined */ Remove this comment if common structures are not defined already. https://review.coreboot.org/c/coreboot/+/85599/comment/2196756a_65fd484d?us… : PS1, Line 731: ( remove https://review.coreboot.org/c/coreboot/+/85599/comment/bd073c0f_68823a6b?us… : PS1, Line 735: ( remove https://review.coreboot.org/c/coreboot/+/85599/comment/300ff288_f86d6ccb?us… : PS1, Line 738: status Remove if not used. https://review.coreboot.org/c/coreboot/+/85599/comment/0c147d9e_15b4a986?us… : PS1, Line 738: en Do you mean `enable`? https://review.coreboot.org/c/coreboot/+/85599/comment/d9632b33_f0d305c8?us… : PS1, Line 738: int bool https://review.coreboot.org/c/coreboot/+/85599/comment/44dde7ad_1f52dc3c?us… : PS1, Line 740: unsigned int u32 https://review.coreboot.org/c/coreboot/+/85599/comment/1a5615de_4cc60a9e?us… : PS1, Line 743: clrbits32(&mtk_spm->spm_ack_chk_con_3, SPM_ACK_CHK_3_CON_CLR_ALL); : setbits32(&mtk_spm->spm_ack_chk_con_3, SPM_ACK_CHK_3_CON_EN); Can this be done in one `clrsetbits32` call? https://review.coreboot.org/c/coreboot/+/85599/comment/9327a057_d59c8b23?us… : PS1, Line 755: SPM_ACK_CHK_3_CON_HW_MODE_TRIG Align https://review.coreboot.org/c/coreboot/+/85599/comment/59ca9edb_84575848?us… : PS1, Line 782: ( Space before `(` https://review.coreboot.org/c/coreboot/+/85599/comment/bd8a5acc_c9a5d95b?us… : PS1, Line 791: i I https://review.coreboot.org/c/coreboot/+/85599/comment/82edbb2a_9e70f6dd?us… : PS1, Line 794: ( remove https://review.coreboot.org/c/coreboot/+/85599/comment/245efb43_682b82c4?us… : PS1, Line 797: ( remove https://review.coreboot.org/c/coreboot/+/85599/comment/725aac4c_a48cd688?us… : PS1, Line 861: SPM_REGWR_CFG_KEY | REG_SPM_APB_INTERNAL_EN_LSB | Align -- To view, visit https://review.coreboot.org/c/coreboot/+/85599?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie09346f46cb734c74776b760485e7f35d4357e5e Gerrit-Change-Number: 85599 Gerrit-PatchSet: 1 Gerrit-Owner: Ccong Chen <ot_ccong.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Wenzhen Yu <wenzhen.yu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Wenzhen Yu <wenzhen.yu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Ccong Chen <ot_ccong.chen(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Mon, 16 Dec 2024 06:50:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

1 0

[XS] Change in coreboot[main]: soc/intel/pantherlake: Decrease CRASHLOG_NODES_COUNT to 1
by Sowmya Aralguppe (Code Review) 16 Dec '24

16 Dec '24

Attention is currently required from: Kapil Porwal, Paul Menzel, Pranava Y N, Subrata Banik. Sowmya Aralguppe has posted comments on this change by Sowmya Aralguppe. ( https://review.coreboot.org/c/coreboot/+/85531?usp=email ) Change subject: soc/intel/pantherlake: Decrease CRASHLOG_NODES_COUNT to 1 ...................................................................... Patch Set 7: (1 comment) Patchset: PS6: > if I remember correctly then you were trying to enable crashlog for all notes (total 5) but now you […] There are only 3 dielets in LNL/PTL on base Die 1) GT die - self contained has its own storage - collected by PUNIT. 2) Compute Die 3) PCD die Hence we only have Compute Die in LNL/PTL unlike MTL which had different SRAM's for different Dielets. If we iterate more than what is programmed in the header by BIOS - crashlog decoding will have error .hence wanted to limit it to 1 More Details - taken from LNL FAS 15.3.2 LNL Dis-aggregation CrashLog LNL is considered as a "self-contained" compared to MTL's disaggregated Crashlog dielets architecture. The fundamental difference is that MTL's Crashlog as a disaggregated package where the CPU and PCH are combined is full system from system perspective that is implemented on a different dielets. Each die controls its SRAM without impacting SOC die as well as PM Support. LNL is unified and only the Graphics part i.e. GCD-die considered as a "self-contained" disaggregated element. In general CCF and Atom modules on the Compute die and the uncore and PCH on the SOC die. Given the long term direction of dielets changing and potentially the SOC die to be re-used, crashlog storage will also be disaggregated per dielet. The PUnit will be the master Crashlog unit for the SOC-North and dielets and PMC will continue to be the SOC-south (PCH) crashlog unit. 15.3.3 Crashlog Storage For LNL 24KB needed for Crashlog in SRAM on the Punit. GCD uses its own storage on the Compute die. To recall, in MTL the Telemetry and Crashlog contents being split on a separate SRAMs to allow the crashlog SRAM to survive global reset. That was wired by Crashlog SRAM being on the VNNAON rail. However, for LNL they are expected to be in the same memory space. -- To view, visit https://review.coreboot.org/c/coreboot/+/85531?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I209366d324c95b7a32afdcfb792c34d927a0508e Gerrit-Change-Number: 85531 Gerrit-PatchSet: 7 Gerrit-Owner: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Mon, 16 Dec 2024 06:46:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

1 0

[XS] Change in coreboot[main]: util/mtkheader: Add GFH header for mt8189 bootblock code
by Vince Liu (Code Review) 16 Dec '24

16 Dec '24

Attention is currently required from: Hung-Te Lin, Paul Menzel. Vince Liu has posted comments on this change by Vince Liu. ( https://review.coreboot.org/c/coreboot/+/85598?usp=email ) Change subject: util/mtkheader: Add GFH header for mt8189 bootblock code ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/85598/comment/e601612c_44f7317d?us… : PS1, Line 9: Set bootblock load address for bootROM. > Where is the value documented? Some datasheet? We don't have any documentation describing this address. -- To view, visit https://review.coreboot.org/c/coreboot/+/85598?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I47078272880a89e81c851ede307cdc306b1c79ac Gerrit-Change-Number: 85598 Gerrit-PatchSet: 1 Gerrit-Owner: Vince Liu <vince-wl.liu(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Mon, 16 Dec 2024 06:39:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

1 0

[L] Change in coreboot[main]: mb/asrock: Add ASRock H370m-ITX support (Coffee Lake)
by Paul Menzel (Code Review) 16 Dec '24

16 Dec '24

Attention is currently required from: Name of user not set #1004406. Paul Menzel has posted comments on this change by Name of user not set #1004406. ( https://review.coreboot.org/c/coreboot/+/65225?usp=email ) Change subject: mb/asrock: Add ASRock H370m-ITX support (Coffee Lake) ...................................................................... Patch Set 20: (1 comment) Patchset: PS20: > should i fix the suspend and m. […] In my opinion these issues could be fixed in follow-up commits. -- To view, visit https://review.coreboot.org/c/coreboot/+/65225?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I79302247311471153ebbba991081365d9265791b Gerrit-Change-Number: 65225 Gerrit-PatchSet: 20 Gerrit-Owner: Name of user not set #1004406 Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Name of user not set #1004406 Gerrit-Comment-Date: Mon, 16 Dec 2024 06:27:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Name of user not set #1004406

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit December 2024