coreboot-gerrit December 2024

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[main]: commonlib: Refactor CSE sync eventLog
by Kapil Porwal (Code Review) 18 Dec '24

18 Dec '24

Attention is currently required from: Dinesh Gehlot, Karthik Ramasubramanian, Subrata Banik. Kapil Porwal has posted comments on this change by Dinesh Gehlot. ( https://review.coreboot.org/c/coreboot/+/85622?usp=email ) Change subject: commonlib: Refactor CSE sync eventLog ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85622?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia5db3ffb43b2ceac821de72ef9e88ed62e617d41 Gerrit-Change-Number: 85622 Gerrit-PatchSet: 1 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Wed, 18 Dec 2024 10:51:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: util/cbfstool: eliminate late sign of life event
by Kapil Porwal (Code Review) 18 Dec '24

18 Dec '24

Attention is currently required from: Dinesh Gehlot, Karthik Ramasubramanian, Subrata Banik. Kapil Porwal has posted comments on this change by Dinesh Gehlot. ( https://review.coreboot.org/c/coreboot/+/85621?usp=email ) Change subject: util/cbfstool: eliminate late sign of life event ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85621?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I53baecb3ca0cef5e0e18732e02832e8331e000d0 Gerrit-Change-Number: 85621 Gerrit-PatchSet: 1 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Wed, 18 Dec 2024 10:50:42 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: src/soc/intel/cmn/blk/cse: Log cse sync information
by Kapil Porwal (Code Review) 18 Dec '24

18 Dec '24

Attention is currently required from: Dinesh Gehlot, Paul Menzel, Subrata Banik. Kapil Porwal has posted comments on this change by Dinesh Gehlot. ( https://review.coreboot.org/c/coreboot/+/85219?usp=email ) Change subject: src/soc/intel/cmn/blk/cse: Log cse sync information ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85219?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idece841c2b069d7688afc258470667ed2851a282 Gerrit-Change-Number: 85219 Gerrit-PatchSet: 3 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Wed, 18 Dec 2024 10:50:02 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: soc/intel: Log CSE Sync Early Sign of Life event from a better place
by Kapil Porwal (Code Review) 18 Dec '24

18 Dec '24

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Jayvik Desai, Karthik Ramasubramanian, Nick Vaccaro, Subrata Banik, Tarun. Kapil Porwal has posted comments on this change by Karthik Ramasubramanian. ( https://review.coreboot.org/c/coreboot/+/85111?usp=email ) Change subject: soc/intel: Log CSE Sync Early Sign of Life event from a better place ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85111?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iaa0dbb87ddde69dc3f4a9e058fc6bed8711b29e7 Gerrit-Change-Number: 85111 Gerrit-PatchSet: 5 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Wed, 18 Dec 2024 10:44:30 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[L] Change in coreboot[main]: mainboard: Add MiTAC Computing Whitestone-2 (LGA-4677)
by Mark Chang (Code Review) 18 Dec '24

18 Dec '24

Mark Chang has posted comments on this change by Mark Chang. ( https://review.coreboot.org/c/coreboot/+/85532?usp=email ) Change subject: mainboard: Add MiTAC Computing Whitestone-2 (LGA-4677) ...................................................................... Patch Set 8: (1 comment) Patchset: PS8: > Thanks @mark.chang@mitaccomputing. […] Thanks @sheng.tan@9elements.com, @shuo.liu@intel.com, @th3fanbus@gmail.com and @paulepanter@mailbox.org for the great help to review our modification. -- To view, visit https://review.coreboot.org/c/coreboot/+/85532?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icf625cf8e9c76ef08411614c15ee43d0c459b905 Gerrit-Change-Number: 85532 Gerrit-PatchSet: 8 Gerrit-Owner: Mark Chang <mark.chang(a)mitaccomputing.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: niehaitao(a)bytedance.com Gerrit-Reviewer: yuchi.chen(a)intel.com Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Wilson-MiTACComputing <wilson.chien(a)mitaccomputing.com> Gerrit-Comment-Date: Wed, 18 Dec 2024 10:38:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Lean Sheng Tan <sheng.tan(a)9elements.com>

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[S] Change in coreboot[main]: mb/google/nissa/var/telith: Modify PLD for typeC and typeA
by Kapil Porwal (Code Review) 18 Dec '24

18 Dec '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Ginger Zhang, Jayvik Desai, Kun Liu, Nick Vaccaro, Subrata Banik. Kapil Porwal has posted comments on this change by Kun Liu. ( https://review.coreboot.org/c/coreboot/+/85618?usp=email ) Change subject: mb/google/nissa/var/telith: Modify PLD for typeC and typeA ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85618?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifc5cd7c8e61b20632d2dcf4b7b2d506c42162063 Gerrit-Change-Number: 85618 Gerrit-PatchSet: 2 Gerrit-Owner: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Ginger Zhang <zhangqingchun(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Ginger Zhang <zhangqingchun(a)huaqin.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Wed, 18 Dec 2024 10:26:39 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XL] Change in coreboot[main]: soc/meidatek/mt8196: Add SPM loader
by Ccong Chen (Code Review) 18 Dec '24

18 Dec '24

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yidi Lin, Yu-Ping Wu. Ccong Chen has posted comments on this change by Ccong Chen. ( https://review.coreboot.org/c/coreboot/+/85599?usp=email ) Change subject: soc/meidatek/mt8196: Add SPM loader ...................................................................... Patch Set 5: (1 comment) File src/soc/mediatek/mt8196/include/soc/spm.h: https://review.coreboot.org/c/coreboot/+/85599/comment/0b6a2652_e191ac22?us… : PS5, Line 642: u32 reserved3; > Revert these unrelated changes. Please fix all similar cases in this file. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/85599?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie09346f46cb734c74776b760485e7f35d4357e5e Gerrit-Change-Number: 85599 Gerrit-PatchSet: 5 Gerrit-Owner: Ccong Chen <ot_ccong.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-CC: Wenzhen Yu <wenzhen.yu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Wed, 18 Dec 2024 09:58:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com>

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[XL] Change in coreboot[main]: soc/meidatek/mt8196: Add SPM loader
by Ccong Chen (Code Review) 18 Dec '24

18 Dec '24

Attention is currently required from: Ccong Chen, Hung-Te Lin, Jarried Lin, Yidi Lin. Hello Hung-Te Lin, Wenzhen Yu, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85599?usp=email to look at the new patch set (#6). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: soc/meidatek/mt8196: Add SPM loader ...................................................................... soc/meidatek/mt8196: Add SPM loader This patch adds support for loading SPM firmware from CBFS to SPM SRAM and fix the SPM register definitions. SPM needs its own firmware to enable SPM suspend/resume function which turns off several resources such as DRAM/mainpll/26M clk when linux system suspend. coreboot log: CBFS: Found 'spm_firmware.pm' @0xadf00 size 0x5a60 in mcache @0xfffdd3c mtk_init_mcu: Loaded (and reset) spm_firmware.pm in 3 msecs (30080 byt) TEST=build pass BUG=348147674 Change-Id: Ie09346f46cb734c74776b760485e7f35d4357e5e Signed-off-by: Wenzhen Yu <wenzhen.yu(a)mediatek.corp-partner.google.com> --- M src/soc/mediatek/common/Kconfig M src/soc/mediatek/common/spm.c M src/soc/mediatek/mt8196/Kconfig M src/soc/mediatek/mt8196/Makefile.mk M src/soc/mediatek/mt8196/include/soc/addressmap.h M src/soc/mediatek/mt8196/include/soc/pll.h M src/soc/mediatek/mt8196/include/soc/spm.h A src/soc/mediatek/mt8196/spm.c 8 files changed, 1,349 insertions(+), 172 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/85599/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/85599?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie09346f46cb734c74776b760485e7f35d4357e5e Gerrit-Change-Number: 85599 Gerrit-PatchSet: 6 Gerrit-Owner: Ccong Chen <ot_ccong.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-CC: Wenzhen Yu <wenzhen.yu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Ccong Chen <ot_ccong.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com>

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[L] Change in coreboot[main]: soc/mediatek/mt8196: Add GPUEB support
by Jarried Lin (Code Review) 18 Dec '24

18 Dec '24

Attention is currently required from: Andy Hsu. Hello Andy Hsu, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/85654?usp=email to review the following change. Change subject: soc/mediatek/mt8196: Add GPUEB support ...................................................................... soc/mediatek/mt8196: Add GPUEB support GPUEB is a micro-processor used for GPU power management. It is also responsible for controlling GPU DVFS and GPU thermal throttling. This gpueb load flow adds 47ms to the boot time. coreboot log: CBFS: Found 'tinysys-gpueb-RV33_A.mkpt_fw.img' @0x84740 size 0x29736 in mcache @0xfffdd374 Loaded (and reset) tinysys-gpueb-RV33_A.mkpt_fw.img in 47 msecs. TEST=Boot ok BUG=b:317009620 Signed-off-by: Andy.Hsu <andy.hsu(a)mediatek.corp-partner.google.com> Change-Id: I0f10dfc753f73df97ea08a4c23e97de416832be2 --- M src/soc/mediatek/common/include/soc/symbols.h M src/soc/mediatek/mt8196/Kconfig M src/soc/mediatek/mt8196/Makefile.mk A src/soc/mediatek/mt8196/gpueb.c M src/soc/mediatek/mt8196/include/soc/addressmap.h A src/soc/mediatek/mt8196/include/soc/gpueb.h A src/soc/mediatek/mt8196/include/soc/gpueb_priv.h M src/soc/mediatek/mt8196/include/soc/memlayout.ld M src/soc/mediatek/mt8196/soc.c 9 files changed, 669 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/85654/1 diff --git a/src/soc/mediatek/common/include/soc/symbols.h b/src/soc/mediatek/common/include/soc/symbols.h index 065c300..46a9d9a 100644 --- a/src/soc/mediatek/common/include/soc/symbols.h +++ b/src/soc/mediatek/common/include/soc/symbols.h @@ -7,5 +7,7 @@ DECLARE_REGION(dram_dma) DECLARE_REGION(resv_mem_optee) +DECLARE_REGION(resv_mem_gpu) +DECLARE_REGION(resv_mem_gpueb) #endif /* _SOC_MEDIATEK_COMMON_SYMBOLS_H_ */ diff --git a/src/soc/mediatek/mt8196/Kconfig b/src/soc/mediatek/mt8196/Kconfig index 2133dbb..33422f1 100644 --- a/src/soc/mediatek/mt8196/Kconfig +++ b/src/soc/mediatek/mt8196/Kconfig @@ -45,4 +45,10 @@ help The file name of the MediaTek SSPM firmware. +config GPUEB_FIRMWARE + string + default "tinysys-gpueb-RV33_A.mkpt_fw.img" + help + The file name of the MediaTek GPUEB firmware. + endif diff --git a/src/soc/mediatek/mt8196/Makefile.mk b/src/soc/mediatek/mt8196/Makefile.mk index 6987ff5..bb86717 100644 --- a/src/soc/mediatek/mt8196/Makefile.mk +++ b/src/soc/mediatek/mt8196/Makefile.mk @@ -42,6 +42,7 @@ ramstage-y += dramc_info.c ramstage-y += ../common/early_init.c ramstage-y += ../common/emi.c +ramstage-y += gpueb.c ramstage-y += l2c_ops.c ramstage-y += ../common/mcu.c ramstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c @@ -66,7 +67,8 @@ mcu-firmware-files := \ $(CONFIG_DPM_DM_FIRMWARE) \ $(CONFIG_DPM_PM_FIRMWARE) \ - $(CONFIG_SSPM_FIRMWARE) + $(CONFIG_SSPM_FIRMWARE) \ + $(CONFIG_GPUEB_FIRMWARE) $(foreach fw, $(call strip_quotes,$(mcu-firmware-files)), \ $(eval $(fw)-file := $(MT8196_BLOB_DIR)/$(fw)) \ diff --git a/src/soc/mediatek/mt8196/gpueb.c b/src/soc/mediatek/mt8196/gpueb.c new file mode 100644 index 0000000..0f233a8 --- /dev/null +++ b/src/soc/mediatek/mt8196/gpueb.c @@ -0,0 +1,422 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ + +/* + * These values are used by MediaTek internally. + * We can find these registers in "CODA_GPU_RPC_202306081135". + * The setting values are provided by MediaTek designers. + */ + +#include <arch/barrier.h> +#include <cbfs.h> +#include <console/console.h> +#include <delay.h> +#include <device/mmio.h> +#include <halt.h> +#include <soc/gpueb.h> +#include <soc/mcu_common.h> +#include <soc/symbols.h> +#include <timer.h> + +static struct auto_dma_fw_header auto_dma_fw[PT_FW_NUM]; + +static void gpu_reset(void) +{ + /* Reset MFG before normal boot */ + write32p(MFG_RPC_MFG36_PWR_CON, MFG_PWR_OFF_VALUE0); + write32p(MFG_RPC_MFG35_PWR_CON, MFG_PWR_OFF_VALUE0); + write32p(MFG_RPC_MFG34_PWR_CON, MFG_PWR_OFF_VALUE0); + write32p(MFG_RPC_MFG33_PWR_CON, MFG_PWR_OFF_VALUE0); + write32p(MFG_RPC_MFG32_PWR_CON, MFG_PWR_OFF_VALUE0); + write32p(MFG_RPC_MFG31_PWR_CON, MFG_PWR_OFF_VALUE0); + write32p(MFG_RPC_MFG30_PWR_CON, MFG_PWR_OFF_VALUE0); + write32p(MFG_RPC_MFG29_PWR_CON, MFG_PWR_OFF_VALUE0); + write32p(MFG_RPC_MFG28_PWR_CON, MFG_PWR_OFF_VALUE0); + write32p(MFG_RPC_MFG27_PWR_CON, MFG_PWR_OFF_VALUE0); + write32p(MFG_RPC_MFG26_PWR_CON, MFG_PWR_OFF_VALUE0); + write32p(MFG_RPC_MFG25_PWR_CON, MFG_PWR_OFF_VALUE0); + write32p(MFG_RPC_MFG20_PWR_CON, MFG_PWR_OFF_VALUE0); + write32p(MFG_RPC_MFG19_PWR_CON, MFG_PWR_OFF_VALUE0); + write32p(MFG_RPC_MFG18_PWR_CON, MFG_PWR_OFF_VALUE0); + write32p(MFG_RPC_MFG17_PWR_CON, MFG_PWR_OFF_VALUE0); + write32p(MFG_RPC_MFG16_PWR_CON, MFG_PWR_OFF_VALUE0); + write32p(MFG_RPC_MFG15_PWR_CON, MFG_PWR_OFF_VALUE0); + write32p(MFG_RPC_MFG14_PWR_CON, MFG_PWR_OFF_VALUE0); + write32p(MFG_RPC_MFG13_PWR_CON, MFG_PWR_OFF_VALUE0); + write32p(MFG_RPC_MFG12_PWR_CON, MFG_PWR_OFF_VALUE0); + write32p(MFG_RPC_MFG11_PWR_CON, MFG_PWR_OFF_VALUE0); + write32p(MFG_RPC_MFG10_PWR_CON, MFG_PWR_OFF_VALUE0); + write32p(MFG_RPC_MFG9_PWR_CON, MFG_PWR_OFF_VALUE0); + write32p(MFG_RPC_MFG23_PWR_CON, MFG_PWR_OFF_VALUE0); + write32p(MFG_RPC_MFG8_PWR_CON, MFG_PWR_OFF_VALUE0); + write32p(MFG_RPC_MFG7_PWR_CON, MFG_PWR_OFF_VALUE0); + write32p(MFG_RPC_MFG5_PWR_CON, MFG_PWR_OFF_VALUE0); + write32p(MFG_RPC_MFG4_PWR_CON, MFG_PWR_OFF_VALUE0); + write32p(MFG_RPC_MFG3_PWR_CON, MFG_PWR_OFF_VALUE0); + write32p(MFG_RPC_MFG2_PWR_CON, MFG_PWR_OFF_VALUE0); + write32p(MFG_RPC_MFG37_PWR_CON, MFG_PWR_OFF_VALUE1); + write32p(MFG_RPC_MFG1_PWR_CON, MFG_PWR_OFF_VALUE2); + write32p(SPM_MFG0_PWR_CON, SPM_MFG_PWR_OFF_VALUE); + write32p(MFG_RPC_MFG0_PWR_CON, MFG_PWR_OFF_VALUE3); + write32p(MFG_GHPM_CFG0_CON, 0x0); + write32p(MFG_RPC_GHPM_CFG13_CON, 0x0); + write32p(MFG_RPCTOP_DUMMY_REG_0, 0x0); +} + +static bool is_mfg0_power_on(void) +{ + return (read32p(MFG0_PWR_CON) & MFG0_PWR_ACK_BIT) == MFG0_PWR_ACK_BIT; +} + +static u32 get_mfg0_pwr_con(void) +{ + return read32p(MFG_RPC_MFG0_PWR_CON); +} + +static void gpueb_dump_register(void) +{ + DUMP_REG(MFG_RPC_MFG0_PWR_CON); + DUMP_REG(SPM_MFG0_PWR_CON); + DUMP_REG(MFG_RPC_SLV_SLP_PROT_RDY_STA); +} + +static void gpueb_print_exp_status(void) +{ + printk(BIOS_ERR, "%s: Request mainpll polling ack: failed\n", __func__); + printk(BIOS_ERR, "%s: MFG0_PWR_CON = %#x\n", __func__, get_mfg0_pwr_con()); + DUMP_REG(MFG_RPC_AO_CLK_CFG); + DUMP_REG(MAINPLL_SEL); + DUMP_REG(MFG_SODI_VRF18); + DUMP_REG(GPUEB_BUSPLL_RES_STA_GPR); + DUMP_REG(MFG_RPC_GHPM_CFG13_CON); + DUMP_REG(MFG_GHPM_RO2_CON); + DUMP_REG(SPM_REQ_STA_9); +} + +static bool wait_status_ready(uintptr_t status_reg, uint32_t mask, + uint32_t expect, uint32_t count) +{ + uint32_t i = 0; + + do { + udelay(MTCMOS_DELAY_TIME_US); + if ((read32p(status_reg) & mask) == expect) + return true; + i++; + } while (i < count); + + gpueb_dump_register(); + return false; +} + +static void request_resource(void) +{ + setbits32p(MFG_RPC_GHPM_CFG13_CON, RESOURCE_BITS); + if (!wait_status_ready(MFG_GHPM_RO2_CON, RESOURCE_ACK_BITS, RESOURCE_ACK_BITS, 50)) { + gpueb_print_exp_status(); + halt(); + } +} + +static void gpueb_do_state_power_on(enum mfg0_power_state power) +{ + if (power != POWER_ON) + die("%s: Error (power_state=%d).\n", __func__, power); + + setbits32p(MFG_RPC_MFG0_PWR_CON, BIT(2)); + if (!wait_status_ready(MFG_RPC_MFG0_PWR_CON, BIT(30), BIT(30), 50)) + return; + + udelay(50); + setbits32p(MFG_RPC_MFG0_PWR_CON, BIT(3)); + if (!wait_status_ready(MFG_RPC_MFG0_PWR_CON, GENMASK(31, 30), GENMASK(31, 30), 1000)) + return; + + clrbits32p(MFG_RPC_MFG0_PWR_CON, BIT(4)); + clrbits32p(MFG_RPC_MFG0_PWR_CON, BIT(1)); + setbits32p(MFG_RPC_MFG0_PWR_CON, BIT(0)); + clrbits32p(MFG_RPC_MFG0_PWR_CON, BIT(8)); + if (!wait_status_ready(MFG_RPC_MFG0_PWR_CON, BIT(12), 0, 1000)) + return; + + setbits32p(MFG_RPC_MFG0_PWR_CON, BIT(21)); + clrbits32p(MFG_RPC_MFG0_PWR_CON, BIT(22)); + write32p(MFGSYS_PROTECT_EN_CLR_0, GENMASK(31, 25) | GENMASK(19, 16) | GENMASK(3, 0)); + if (!wait_status_ready(MFGSYS_PROTECT_EN_STA_0, + GENMASK(31, 26) | BIT(7) | GENMASK(3, 0), 0, 1000)) + return; + + write32p(MFG_RPC_SLV_SLP_PROT_EN_CLR, BIT(0)); + if (!wait_status_ready(MFG_RPC_SLV_SLP_PROT_RDY_STA, BIT(0), 0, 1000)) + return; + + write32p(MFG_RPC_SLV_SLP_PROT_EN_CLR, BIT(1)); + if (!wait_status_ready(MFG_RPC_SLV_SLP_PROT_RDY_STA, BIT(1), 0, 1000)) + return; + + write32p(MFG_RPC_SLV_WAY_EN_SET, BIT(0)); + wait_status_ready(MFG_RPC_SLV_CTRL_UPDATE, BIT(0), BIT(0), 1000); +} + +static void gpueb_do_state_power_off(enum mfg0_power_state power) +{ + if (power != POWER_OFF) + die("%s: Error (power_state=%d).\n", __func__, power); + + write32p(MFG_RPC_SLV_WAY_EN_CLR, BIT(0)); + if (!wait_status_ready(MFG_RPC_SLV_CTRL_UPDATE, BIT(0), BIT(0), 1000)) + return; + + write32p(MFG_RPC_SLV_SLP_PROT_EN_SET, BIT(1)); + if (!wait_status_ready(MFG_RPC_SLV_SLP_PROT_RDY_STA, BIT(1), BIT(1), 1000)) + return; + + write32p(MFG_RPC_SLV_SLP_PROT_EN_SET, BIT(0)); + if (!wait_status_ready(MFG_RPC_SLV_SLP_PROT_RDY_STA, BIT(0), BIT(0), 1000)) + return; + + write32p(MFGSYS_PROTECT_EN_SET_0, GENMASK(31, 25) | GENMASK(3, 0)); + if (!wait_status_ready(MFGSYS_PROTECT_EN_STA_0, + GENMASK(31, 26) | BIT(7) | GENMASK(3, 0), + GENMASK(31, 26) | BIT(7) | GENMASK(3, 0), 1000)) + return; + + setbits32p(MFG_RPC_MFG0_PWR_CON, BIT(22)); + clrbits32p(MFG_RPC_MFG0_PWR_CON, BIT(21)); + udelay(1); + setbits32p(MFG_RPC_MFG0_PWR_CON, BIT(8)); + if (!wait_status_ready(MFG_RPC_MFG0_PWR_CON, BIT(12), BIT(12), 500)) + return; + + setbits32p(MFG_RPC_MFG0_PWR_CON, BIT(1)); + setbits32p(MFG_RPC_MFG0_PWR_CON, BIT(4)); + clrbits32p(MFG_RPC_MFG0_PWR_CON, BIT(0)); + clrbits32p(MFG_RPC_MFG0_PWR_CON, BIT(2)); + clrbits32p(MFG_RPC_MFG0_PWR_CON, BIT(3)); + wait_status_ready(MFG_RPC_MFG0_PWR_CON, GENMASK(31, 30), 0, 500); +} + +static void mfg0_rpc_ctrl_shutdown(enum mfg0_power_state power) +{ + setbits32p(MFG_RPC_MFG0_PWR_CON, BIT(28)); + + if (power == POWER_ON) + gpueb_do_state_power_on(power); + else + gpueb_do_state_power_off(power); +} + +static void mfg0_rpc_ctrl(enum mfg0_power_state power) +{ + if (read32p(MFG_RPC_MFG0_PWR_CON) & MFG0_PWR_SRAM_PDN) + mfg0_rpc_ctrl_shutdown(power); +} + +static void switch_mux_pll(void) +{ + request_resource(); + setbits32p(MFG_RPC_AO_CLK_CFG, GPUEB_CKMUX_SEL_26M_BIT); + udelay(SWITCH_MUX_WAIT_TIME); +} + +static void gpueb_assert_init_success(void) +{ + u32 gpueb_mux; + + gpueb_mux = read32p(MFG_RPC_AO_CLK_CFG); + if (is_mfg0_power_on() && + ((gpueb_mux & GPUEB_CKMUX_SEL_26M_BIT) == GPUEB_CKMUX_SEL_26M_BIT)) { + printk(BIOS_INFO, "%s: Done.\n", __func__); + return; + } + gpueb_print_exp_status(); + halt(); +} + +static void gpueb_parsing_fw(void *tmp_addr, void **gpueb_img, size_t *gpueb_imgsize) +{ + int i; + void *img; + struct ptimg_hdr_t *hdr; + + hdr = (struct ptimg_hdr_t *)tmp_addr; + + while (hdr->magic == PT_MAGIC) { + img = ((void *)hdr) + hdr->hdr_size; + + if (hdr->id == 0 || hdr->id >= PT_FW_NUM) { + img += ALIGN_UP(hdr->img_size, hdr->align); + hdr = (struct ptimg_hdr_t *)img; + continue; + } + + if (hdr->id == PT_FW_IDX_GPUEB_FW) { + /* GPUEB FW no need include header */ + *gpueb_img = img; + *gpueb_imgsize = hdr->img_size; + auto_dma_fw[PT_FW_IDX_GPUEB_FW].fw = img; + auto_dma_fw[PT_FW_IDX_GPUEB_FW].fw_size = hdr->img_size; + } else { + auto_dma_fw[hdr->id].fw = img; + auto_dma_fw[hdr->id].fw_size = hdr->img_size; + auto_dma_fw[hdr->id].fw_addr = hdr->addr; + } + + img += ALIGN_UP(hdr->img_size, hdr->align); + hdr = (struct ptimg_hdr_t *)img; + } + + for (i = 1; i < PT_FW_NUM; i++) { + if (!auto_dma_fw[i].fw) { + die("%s: Partition missing (@%p)\n" + "fw_id[%d]:%p\n", __func__, tmp_addr, i, auto_dma_fw[i].fw); + } + } +} + +static void load_fw(int pt_id) +{ + memcpy((void *)(GPUEB_SRAM_BASE + auto_dma_fw[pt_id].fw_addr), + auto_dma_fw[pt_id].fw, auto_dma_fw[pt_id].fw_size); +} + +static void load_auto_dma_fw(void) +{ + load_fw(PT_FW_IDX_AUTO_DMA_CS_BRCAST_PART1_FW); + load_fw(PT_FW_IDX_AUTO_DMA_CS_BRCAST_PART2_FW); + load_fw(PT_FW_IDX_AUTO_DMA_CS_BRCAST_PART3_FW); + load_fw(PT_FW_IDX_AUTO_DMA_CS_HBVC_LOGGING_FW); + load_fw(PT_FW_IDX_AUTO_DMA_CS_TOP_SESV8_FW); + load_fw(PT_FW_IDX_AUTO_DMA_CS_STK_SESV8_FW); + load_fw(PT_FW_IDX_AUTO_DMA_SMMU_FW); + load_fw(PT_FW_IDX_AUTO_DMA_PREOC_FW); + load_fw(PT_FW_IDX_AUTO_DMA_CCMD_CH1_FW); + load_fw(PT_FW_IDX_AUTO_DMA_CCMD_CH2_FW); + load_fw(PT_FW_IDX_AUTO_DMA_CCMD_CH0_FW); + load_fw(PT_FW_IDX_AUTO_DMA_HBVC_CONFIG_GRP0_FW); + load_fw(PT_FW_IDX_AUTO_DMA_HBVC_CONFIG_GRP1_FW); + load_fw(PT_FW_IDX_AUTO_DMA_GPM_OUT_OF_RATIO_FW); + load_fw(PT_FW_IDX_AUTO_DMA_GPM_OUT_OF_SUM_MAX_FW); +} + +static bool gpueb_is_sram_access(void) +{ + u32 mfg0_pwr_con; + + mfg0_pwr_con = read32p(MFG0_PWR_CON); + + if ((mfg0_pwr_con & MFG0_PWR_SRAM_PDN_ACK)) { + printk(BIOS_CRIT, "%s: SRAM is power-down(%#x)\n", + __func__, mfg0_pwr_con); + return false; + } + + if ((mfg0_pwr_con & MFG0_PWR_SRAM_SLEEP_B_ACK) != MFG0_PWR_SRAM_SLEEP_B_ACK) { + printk(BIOS_CRIT, "%s: SRAM is under sleep mode(%#x)\n", + __func__, mfg0_pwr_con); + return false; + } + + return true; +} + +static void gpueb_power_init(void) +{ + if (read32p(MFG_RPC_MFG0_PWR_CON) != MFG0_PWR_ON_VALUE) + mfg0_rpc_ctrl(POWER_ON); + + switch_mux_pll(); + gpueb_assert_init_success(); +} + +static void gpueb_reset(struct mtk_mcu *mcu) +{ + void *gpueb_img = NULL; + size_t gpueb_imgsize = 0; + u32 tcm_lock_info; + + gpueb_parsing_fw(mcu->load_buffer, &gpueb_img, &gpueb_imgsize); + if (!gpueb_img || !gpueb_imgsize) + die("%s: Invalid parameters returned.", __func__); + + tcm_lock_info = (TCM_LOCK_ADDR >> 12) & GPUEB_TCM_LOCK_MASK; + tcm_lock_info = tcm_lock_info << 24; + + write32p(GPUEB_CFGREG_SW_RSTN, 0); + memset((void *)GPUEB_SRAM_BASE, 0, GPUEB_SRAM_SIZE); + memcpy((void *)GPUEB_SRAM_BASE, gpueb_img, gpueb_imgsize); + + load_auto_dma_fw(); + + write32p(GPUEB_INFO, (uintptr_t)mcu->load_buffer); + write32p(GPUEB_ABNORMAL_BOOT, 0); + write32p(GPUEB_WARM_BOOT, 0); + write32p(GPUMPU_RSV_ADDR, (uintptr_t)_resv_mem_gpueb >> PAGE_SHIFT); + + /* Trigger GPUEB */ + write32p(GPUEB_CFGREG_SW_RSTN, 0); + write32p(GPUEB_CFGREG_SW_RSTN, + GPUEB_CFGREG_SW_RSTN_SW_RSTN | GPUEB_CFGREG_SW_RSTN_DMA_BUSY_MASK | + tcm_lock_info | GPUEB_CFGREG_PTCM_LOCK); +} + +static bool is_boot_up_complete(void) +{ + return read32p(GPUEB_INIT_FOOTPRINT) == GPUEB_BOOT_UP_COMPLETE; +} + +static bool gpueb_wait_boot_up_done(void) +{ + if (wait_us(BOOT_TIMEOUT_US, is_boot_up_complete()) == 0) { + printk(BIOS_CRIT, "%s: GPUEB boot-up timed out!!!\n", __func__); + DUMP_REG(GPUEB_MUX); + DUMP_REG(MFG0_PWR_CON); + DUMP_REG(SPM_MFG0_PWR_CON); + DUMP_REG(MFG_RPC_GPUEB_CFG); + DUMP_REG(SPM2GPUPM_CON); + DUMP_REG(GPUEB_CFGREG_SW_RSTN); + DUMP_REG(GPUEB_CFGREG_DBG_APB_PC); + DUMP_REG(GPUEB_CFGREG_DBG_APB_LR); + DUMP_REG(GPUEB_CFGREG_DBG_APB_SP); + DUMP_REG(GPUEB_INIT_FOOTPRINT); + DUMP_REG(GPUFREQ_FOOTPRINT_GPR); + DUMP_REG(GPUPTP3_BAD_SAMPLE); + DUMP_REG(GPUEB_DIAGNOSIS_GPR); + + write32p(GPUEB_INFO, 0x5A5A5A5A); + DUMP_REG(GPUEB_INFO); + return false; + } + + return true; +} + +static struct mtk_mcu gpueb = { + .firmware_name = CONFIG_GPUEB_FIRMWARE, + .load_buffer = _dram_dma, + .buffer_size = REGION_SIZE(dram_dma), + .reset = gpueb_reset +}; + +static void gpueb_platform_load(void) +{ + if ((!is_mfg0_power_on()) || (!gpueb_is_sram_access())) + die("%s: GPUEB(MFG0) NOT power-on!!!", __func__); + + /* Load FW image and trigger GPUEB */ + if (mtk_init_mcu(&gpueb)) + die("%s: Load FW failed.", __func__); + + if (!gpueb_wait_boot_up_done()) + die("%s: Failed.", __func__); + + printk(BIOS_INFO, "%s: GPUEB boot-up complete (magic: %#x)\n", __func__, + read32p(GPUEB_INIT_FOOTPRINT)); +} + +void gpueb_init(void) +{ + gpu_reset(); + gpueb_power_init(); + gpueb_platform_load(); + printk(BIOS_INFO, "%s: Init done.\n", __func__); +} diff --git a/src/soc/mediatek/mt8196/include/soc/addressmap.h b/src/soc/mediatek/mt8196/include/soc/addressmap.h index c9fb302..6fe3269 100644 --- a/src/soc/mediatek/mt8196/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8196/include/soc/addressmap.h @@ -33,11 +33,13 @@ APMIXED_BASE = IO_PHYS + 0x00000800, INFRACFG_AO_BASE = IO_PHYS + 0x00001000, CKSYS_GP2_BASE = IO_PHYS + 0x0000C000, + DRM_DEBUG_BASE = IO_PHYS + 0x0000D000, APMIXEDSYS_GP2_BASE = IO_PHYS + 0x0000C800, BCRM_INFRA_AO_BASE = IO_PHYS + 0x00022000, PMIF_SPI_BASE = IO_PHYS + 0x00024000, PMICSPI_MST_BASE = IO_PHYS + 0x00025000, BCRM_INFRA1_AO_BASE = IO_PHYS + 0x0002A000, + IFRBUS_AO_REG_BUS_BASE = IO_PHYS + 0x0002C000, GPIO_BASE = IO_PHYS + 0x0002D000, DBGSYS_AO_DEBUG_BASE = IO_PHYS + 0x00031000, APINFRA_IO_AO_DEBUG_BASE = IO_PHYS + 0x00155000, @@ -183,9 +185,12 @@ OVLSYS1_CONFIG_BASE = IO_PHYS + 0x22C00000, DISP_VDISP_AO_CONFIG_BASE = IO_PHYS + 0x2E800000, EDP_BASE = IO_PHYS + 0x2EC40000, + MFG_TOP_CFG_BASE = IO_PHYS + 0x38500000, + GPU_EB_RPC_BASE = IO_PHYS + 0x3B800000, MFGPLL_PLL_CTRL_BASE = IO_PHYS + 0x3B810000, MFGPLL_SC0_PLL_CTRL_BASE = IO_PHYS + 0x3B810400, MFGPLL_SC1_PLL_CTRL_BASE = IO_PHYS + 0x3B810800, + MFG_VCORE_AO_CFG_BASE = IO_PHYS + 0x3B860000, }; #endif diff --git a/src/soc/mediatek/mt8196/include/soc/gpueb.h b/src/soc/mediatek/mt8196/include/soc/gpueb.h new file mode 100644 index 0000000..ce93139 --- /dev/null +++ b/src/soc/mediatek/mt8196/include/soc/gpueb.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ + +#ifndef __SOC_MEDIATEK_MT8196_INCLUDE_SOC_GPUEB_H__ +#define __SOC_MEDIATEK_MT8196_INCLUDE_SOC_GPUEB_H__ + +#include <soc/gpueb_priv.h> + +void gpueb_init(void); + +#endif /* __SOC_MEDIATEK_MT8196_INCLUDE_SOC_GPUEB_H__ */ diff --git a/src/soc/mediatek/mt8196/include/soc/gpueb_priv.h b/src/soc/mediatek/mt8196/include/soc/gpueb_priv.h new file mode 100644 index 0000000..e14dd56 --- /dev/null +++ b/src/soc/mediatek/mt8196/include/soc/gpueb_priv.h @@ -0,0 +1,203 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ + +#ifndef __SOC_MEDIATEK_MT8196_INCLUDE_SOC_GPUEB_PRIV_H__ +#define __SOC_MEDIATEK_MT8196_INCLUDE_SOC_GPUEB_PRIV_H__ + +#include <soc/addressmap.h> +#include <types.h> + +#define MAINPLL_SEL (IO_PHYS + 0x0060) /* 0x10000060 */ +#define SPM2GPUPM_CON (SPM_BASE + 0x0410) /* 0x1C004410 */ +#define SPM_REQ_STA_9 (SPM_BASE + 0x0884) /* 0x1C004884 */ +#define SPM_MFG0_PWR_CON (SPM_BASE + 0x0EA8) /* 0x1C004EA8 */ +#define GPUEB_BASE (MFGSYS_BASE + 0x0B000000) /* 0x4B000000 */ +#define MFG_RPC_BASE (MFGSYS_BASE + 0x0B800000) /* 0x4B800000 */ +#define MFG_RPC_SLV_WAY_EN_SET (MFG_RPC_BASE + 0x0060) /* 0x4B800060 */ +#define MFG_RPC_SLV_WAY_EN_CLR (MFG_RPC_BASE + 0x0064) /* 0x4B800064 */ +#define MFG_RPC_SLV_CTRL_UPDATE (MFG_RPC_BASE + 0x0068) /* 0x4B800068 */ +#define MFG_RPC_SLV_SLP_PROT_EN_SET (MFG_RPC_BASE + 0x0070) /* 0x4B800070 */ +#define MFG_RPC_SLV_SLP_PROT_EN_CLR (MFG_RPC_BASE + 0x0074) /* 0x4B800074 */ +#define MFG_RPC_SLV_SLP_PROT_RDY_STA (MFG_RPC_BASE + 0x0078) /* 0x4B800078 */ +#define MFG_RPC_MFG1_PWR_CON (GPU_EB_RPC_BASE + 0x0500) /* 0x4B800500 */ +#define MFG_RPC_MFG0_PWR_CON (GPU_EB_RPC_BASE + 0x0504) /* 0x4B800504 */ +#define MFG_RPC_MFG2_PWR_CON (GPU_EB_RPC_BASE + 0x0508) /* 0x4B800508 */ +#define MFG_RPC_MFG3_PWR_CON (GPU_EB_RPC_BASE + 0x050C) /* 0x4B80050C */ +#define MFG_RPC_MFG4_PWR_CON (GPU_EB_RPC_BASE + 0x0510) /* 0x4B800510 */ +#define MFG_RPC_MFG5_PWR_CON (GPU_EB_RPC_BASE + 0x0514) /* 0x4B800514 */ +#define MFG_RPC_MFG7_PWR_CON (GPU_EB_RPC_BASE + 0x051C) /* 0x4B80051C */ +#define MFG_RPC_MFG8_PWR_CON (GPU_EB_RPC_BASE + 0x0520) /* 0x4B800520 */ +#define MFG_RPC_MFG9_PWR_CON (GPU_EB_RPC_BASE + 0x0524) /* 0x4B800524 */ +#define MFG_RPC_MFG10_PWR_CON (GPU_EB_RPC_BASE + 0x0528) /* 0x4B800528 */ +#define MFG_RPC_MFG11_PWR_CON (GPU_EB_RPC_BASE + 0x052C) /* 0x4B80052C */ +#define MFG_RPC_MFG12_PWR_CON (GPU_EB_RPC_BASE + 0x0530) /* 0x4B800530 */ +#define MFG_RPC_MFG13_PWR_CON (GPU_EB_RPC_BASE + 0x0534) /* 0x4B800534 */ +#define MFG_RPC_MFG14_PWR_CON (GPU_EB_RPC_BASE + 0x0538) /* 0x4B800538 */ +#define MFG_RPC_MFG15_PWR_CON (GPU_EB_RPC_BASE + 0x053C) /* 0x4B80053C */ +#define MFG_RPC_MFG16_PWR_CON (GPU_EB_RPC_BASE + 0x0540) /* 0x4B800540 */ +#define MFG_RPC_MFG17_PWR_CON (GPU_EB_RPC_BASE + 0x0544) /* 0x4B800544 */ +#define MFG_RPC_MFG18_PWR_CON (GPU_EB_RPC_BASE + 0x0548) /* 0x4B800548 */ +#define MFG_RPC_MFG19_PWR_CON (GPU_EB_RPC_BASE + 0x054C) /* 0x4B80054C */ +#define MFG_RPC_MFG20_PWR_CON (GPU_EB_RPC_BASE + 0x0550) /* 0x4B800550 */ +#define MFG_RPC_MFG23_PWR_CON (GPU_EB_RPC_BASE + 0x055C) /* 0x4B80055C */ +#define MFG_RPC_MFG25_PWR_CON (GPU_EB_RPC_BASE + 0x0564) /* 0x4B800564 */ +#define MFG_RPC_MFG26_PWR_CON (GPU_EB_RPC_BASE + 0x0568) /* 0x4B800568 */ +#define MFG_RPC_MFG27_PWR_CON (GPU_EB_RPC_BASE + 0x056C) /* 0x4B80056C */ +#define MFG_RPC_MFG28_PWR_CON (GPU_EB_RPC_BASE + 0x0570) /* 0x4B800570 */ +#define MFG_RPC_MFG29_PWR_CON (GPU_EB_RPC_BASE + 0x0574) /* 0x4B800574 */ +#define MFG_RPC_MFG30_PWR_CON (GPU_EB_RPC_BASE + 0x0578) /* 0x4B800578 */ +#define MFG_RPC_MFG31_PWR_CON (GPU_EB_RPC_BASE + 0x057C) /* 0x4B80057C */ +#define MFG_RPC_MFG32_PWR_CON (GPU_EB_RPC_BASE + 0x0580) /* 0x4B800580 */ +#define MFG_RPC_MFG33_PWR_CON (GPU_EB_RPC_BASE + 0x0584) /* 0x4B800584 */ +#define MFG_RPC_MFG34_PWR_CON (GPU_EB_RPC_BASE + 0x0588) /* 0x4B800588 */ +#define MFG_RPC_MFG35_PWR_CON (GPU_EB_RPC_BASE + 0x058C) /* 0x4B80058C */ +#define MFG_RPC_MFG36_PWR_CON (GPU_EB_RPC_BASE + 0x0590) /* 0x4B800590 */ +#define MFG_RPC_MFG37_PWR_CON (GPU_EB_RPC_BASE + 0x0594) /* 0x4B800594 */ +#define MFG_RPCTOP_DUMMY_REG_0 (GPU_EB_RPC_BASE + 0x0650) /* 0x4B800650 */ +#define MFG_GHPM_CFG0_CON (GPU_EB_RPC_BASE + 0x0800) /* 0x4B800800 */ +#define MFG_RPC_GHPM_CFG13_CON (GPU_EB_RPC_BASE + 0x0834) /* 0x4B800834 */ +#define MFG_GHPM_RO2_CON (MFG_RPC_BASE + 0x09AC) /* 0x4B8009AC */ +#define MFG_VCORE_AO_CONFIG_BASE (MFGSYS_BASE + 0x0B860000) /* 0x4B860000 */ +#define MFG_RPC_GPUEB_CFG (MFG_VCORE_AO_CONFIG_BASE + 0x0074) /* 0x4B860074 */ +#define MFG_RPC_AO_CLK_CFG (MFG_VCORE_AO_CONFIG_BASE + 0x0078) /* 0x4B860078 */ +#define MFGSYS_PROTECT_EN_SET_0 (MFG_VCORE_AO_CFG_BASE + 0x0080) /* 0x4B860080 */ +#define MFGSYS_PROTECT_EN_CLR_0 (MFG_VCORE_AO_CFG_BASE + 0x0084) /* 0x4B860084 */ +#define MFGSYS_PROTECT_EN_STA_0 (MFG_VCORE_AO_CFG_BASE + 0x0088) /* 0x4B860088 */ +#define MFG_SODI_VRF18 (MFG_VCORE_AO_CFG_BASE + 0x00D4) /* 0x4B8600D4 */ + +/* GPUEB */ +#define MBOX_START (GPUEB_SRAM_BASE + 0x0009FD80) +#define GPUEB_MUX MFG_RPC_AO_CLK_CFG +#define GPUEB_SRAM_BASE GPUEB_BASE +#define GPUEB_SRAM_SIZE 0xA0000 /* 640 KB */ +#define GPUEB_GPR_SIZE 0x00000080 /* 128 bytes */ +#define GPUEB_SRAM_GPR_SIZE_4B 0x00000004 +#define GPR_BASE_ADDR(x) (MBOX_START - \ + GPUEB_GPR_SIZE + \ + (x * GPUEB_SRAM_GPR_SIZE_4B)) +#define GPUEB_GPR0 GPR_BASE_ADDR(0) +#define GPUEB_GPR1 GPR_BASE_ADDR(1) +#define GPUEB_GPR2 GPR_BASE_ADDR(2) +#define GPUEB_GPR6 GPR_BASE_ADDR(6) +#define GPUEB_GPR17 GPR_BASE_ADDR(17) +#define GPUEB_GPR18 GPR_BASE_ADDR(18) +#define GPUEB_GPR23 GPR_BASE_ADDR(23) +#define GPUEB_GPR30 GPR_BASE_ADDR(30) +#define GPUEB_INFO GPUEB_GPR0 +#define GPUEB_ABNORMAL_BOOT GPUEB_GPR1 +#define GPUEB_INIT_FOOTPRINT GPUEB_GPR2 +#define GPUMPU_RSV_ADDR GPUEB_GPR6 +#define GPUFREQ_FOOTPRINT_GPR GPUEB_GPR17 +#define GPUEB_DIAGNOSIS_GPR GPUEB_GPR18 +#define GPUEB_WARM_BOOT GPUEB_GPR23 +#define GPUPTP3_BAD_SAMPLE GPUEB_GPR30 +#define GPUEB_CFGREG_BASE (GPUEB_BASE + 0x140100) +#define GPUEB_CFGREG_SW_RSTN (GPUEB_CFGREG_BASE + 0x0000) +#define GPUEB_CFGREG_SW_RSTN_SW_RSTN BIT(0) +#define GPUEB_CFGREG_SW_RSTN_DMA_BUSY_MASK BIT(1) +#define GPUEB_CFGREG_PTCM_LOCK BIT(3) +#define GPUEB_CKMUX_SEL_26M_BIT BIT(6) +#define GPUEB_TCM_LOCK_MASK 0xFF +#define GPUEB_CFGREG_DBG_APB_PC (GPUEB_CFGREG_BASE + 0x011C) +#define GPUEB_CFGREG_DBG_APB_LR (GPUEB_CFGREG_BASE + 0x0120) +#define GPUEB_CFGREG_DBG_APB_SP (GPUEB_CFGREG_BASE + 0x0124) + +#define GPU_PMU_COUNTER_SIZE 0x00000064 +#define GPU_PMU_COUNTER_END GPR_BASE_ADDR(0) +#define GPU_PMU_COUNTER_START (GPU_PMU_COUNTER_END - GPU_PMU_COUNTER_SIZE) +#define GPUEB_SMEM_START (GPU_PMU_COUNTER_START & TCM_LOCK_ALIGNMENT) + +#define TCM_LOCK_ADDR GPUEB_SMEM_START +#define TCM_LOCK_ALIGNMENT 0xFFFFF000 /* 4KB alignment */ + +#define SW_VCORE_REQ BIT(0) +#define SW_PMIC_REQ BIT(1) +#define SW_CK26M_REQ BIT(2) +#define SW_MAINPLL_REQ BIT(3) +#define RESOURCE_BITS (SW_MAINPLL_REQ | SW_CK26M_REQ | SW_PMIC_REQ |\ + SW_VCORE_REQ) + +#define VCORE_ACK_SYNC BIT(28) +#define PMIC_ACK_SYNC BIT(29) +#define CK26M_ACK_SYNC BIT(30) +#define MAINPLL_ACK_SYNC BIT(31) +#define RESOURCE_ACK_BITS (MAINPLL_ACK_SYNC | CK26M_ACK_SYNC |\ + PMIC_ACK_SYNC | VCORE_ACK_SYNC) + +#define MFG_RPC_MFG0_PWR_ACK_2ND_BIT BIT(31) +#define MFG_RPC_MFG0_PWR_ACK_1ST_BIT BIT(30) +#define MFG_RPC_MFG0_PWR_ACK_BIT (MFG_RPC_MFG0_PWR_ACK_1ST_BIT |\ + MFG_RPC_MFG0_PWR_ACK_2ND_BIT) +#define MFG_RPC_MFG0_PWR_SRAM_PDN_ACK BIT(12) +#define MFG_RPC_MFG0_PWR_SRAM_SLEEP_B_ACK BIT(23) +#define MFG0_PWR_CON MFG_RPC_MFG0_PWR_CON +#define MFG0_PWR_ACK_BIT MFG_RPC_MFG0_PWR_ACK_BIT +#define MFG0_PWR_SRAM_SLEEP_B_ACK MFG_RPC_MFG0_PWR_SRAM_SLEEP_B_ACK +#define MFG0_PWR_SRAM_PDN_ACK MFG_RPC_MFG0_PWR_SRAM_PDN_ACK +#define GPUEB_BOOT_UP_COMPLETE 0x55667788 +#define PT_MAGIC 0x58901690 +#define GPUEB_SRAM_GPR25 GPR_BASE_ADDR(25) +#define GPUEB_BUSPLL_RES_STA_GPR GPUEB_SRAM_GPR25 +#define MFG0_PWR_SRAM_PDN BIT(8) +#define MFG_PWR_OFF_VALUE0 0x00001112 +#define MFG_PWR_OFF_VALUE2 0x00003312 +#define MFG_PWR_OFF_VALUE3 0x00700112 +#define SPM_MFG_PWR_OFF_VALUE 0x02000372 +#define MFG_PWR_OFF_VALUE1 0x60001112 +#define MFG0_PWR_ON_VALUE 0xD0B0000D + +#define BOOT_TIMEOUT_US 1000000 +#define MTCMOS_DELAY_TIME_US 3 +#define PAGE_SHIFT 12 +#define SWITCH_MUX_WAIT_TIME 10 + +#define DUMP_REG(reg) printk(BIOS_CRIT, #reg "(%#x) = %#x\n", (reg), read32p((reg))) + +enum mfg0_power_state { + POWER_OFF = 0, + POWER_ON, +}; + +enum PT_FW_IDX { + PT_FW_IDX_GPUEB_FW = 1, + PT_FW_IDX_AUTO_DMA_BRCAST_PART1_FW = 2, + PT_FW_IDX_AUTO_DMA_BRCAST_PART2_FW = 3, + PT_FW_IDX_AUTO_DMA_BRCAST_PART3_FW = 4, + PT_FW_IDX_AUTO_DMA_SMMU_FW = 5, + PT_FW_IDX_AUTO_DMA_PREOC_FW = 6, + PT_FW_IDX_AUTO_DMA_HBVC_LOGGING_FW = 7, + PT_FW_IDX_AUTO_DMA_CCMD_CH1_FW = 8, + PT_FW_IDX_AUTO_DMA_CCMD_CH2_FW = 9, + PT_FW_IDX_AUTO_DMA_CCMD_CH0_FW = 10, + PT_FW_IDX_AUTO_DMA_HBVC_CONFIG_GRP0_FW = 11, + PT_FW_IDX_AUTO_DMA_HBVC_CONFIG_GRP1_FW = 12, + PT_FW_IDX_AUTO_DMA_GPM_OUT_OF_RATIO_FW = 13, + PT_FW_IDX_AUTO_DMA_GPM_OUT_OF_SUM_MAX_FW = 14, + PT_FW_IDX_AUTO_DMA_TOP_SESV8_FW = 15, + PT_FW_IDX_AUTO_DMA_STK_SESV8_FW = 16, + PT_FW_IDX_AUTO_DMA_CS_BRCAST_PART1_FW = 17, + PT_FW_IDX_AUTO_DMA_CS_BRCAST_PART2_FW = 18, + PT_FW_IDX_AUTO_DMA_CS_BRCAST_PART3_FW = 19, + PT_FW_IDX_AUTO_DMA_CS_HBVC_LOGGING_FW = 20, + PT_FW_IDX_AUTO_DMA_CS_TOP_SESV8_FW = 21, + PT_FW_IDX_AUTO_DMA_CS_STK_SESV8_FW = 22, + PT_FW_NUM = 23, +}; + +struct auto_dma_fw_header { + void *fw; + size_t fw_size; + uint64_t fw_addr; +}; + +struct ptimg_hdr_t { + unsigned int magic; /* magic number*/ + unsigned int hdr_size; /* data size */ + unsigned int img_size; /* img size */ + unsigned int align; /* align */ + unsigned int id; /* image id */ + unsigned int addr; /* memory addr; current setting is within the 4GB memory + * region + */ +}; + +#endif /* __SOC_MEDIATEK_MT8196_INCLUDE_SOC_GPUEB_PRIV_H__ */ diff --git a/src/soc/mediatek/mt8196/include/soc/memlayout.ld b/src/soc/mediatek/mt8196/include/soc/memlayout.ld index 83e80b6..595ead1 100644 --- a/src/soc/mediatek/mt8196/include/soc/memlayout.ld +++ b/src/soc/mediatek/mt8196/include/soc/memlayout.ld @@ -5,6 +5,12 @@ #define OPTEE_BUF(addr, size) \ REGION(resv_mem_optee, addr, size, 4K) +#define GPU_BUF(addr, size) \ + REGION(resv_mem_gpu, addr, size, 4K) + +#define RESV_MEMORY_GPUEB(addr, size)\ + REGION(resv_mem_gpueb, addr, size, 2M) + SECTIONS { /* MT8196 has 256KB SRAM. */ @@ -60,4 +66,8 @@ OPTEE_BUF(0x80500000, 70M) BL31(0x94600000, 0x200000) + + /* Reserved Memory for the shared buffer between AP and uP */ + RESV_MEMORY_GPUEB(0xA0000000, 2M) + GPU_BUF(0xA2000000, 16M) } diff --git a/src/soc/mediatek/mt8196/soc.c b/src/soc/mediatek/mt8196/soc.c index 0fe6909..62a0597 100644 --- a/src/soc/mediatek/mt8196/soc.c +++ b/src/soc/mediatek/mt8196/soc.c @@ -1,9 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <bootmem.h> #include <device/device.h> #include <device/pci.h> #include <soc/dramc_info.h> #include <soc/emi.h> +#include <soc/gpueb.h> #include <soc/mmu_operations.h> #include <soc/pcie.h> #include <soc/sspm.h> @@ -17,6 +19,11 @@ REGION_SIZE(resv_mem_optee), BM_MEM_RESERVED); reserve_buffer_for_dramc(); + + bootmem_add_range((uint64_t)_resv_mem_gpu, + (uint64_t)REGION_SIZE(resv_mem_gpu), BM_MEM_RESERVED); + bootmem_add_range((uint64_t)_resv_mem_gpueb, + (uint64_t)REGION_SIZE(resv_mem_gpueb), BM_MEM_RESERVED); } static void soc_read_resources(struct device *dev) @@ -28,6 +35,7 @@ { mtk_mmu_disable_l2c_sram(); sspm_init(); + gpueb_init(); } static struct device_operations soc_ops = { -- To view, visit https://review.coreboot.org/c/coreboot/+/85654?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0f10dfc753f73df97ea08a4c23e97de416832be2 Gerrit-Change-Number: 85654 Gerrit-PatchSet: 1 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Andy Hsu <andy.hsu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Andy Hsu <andy.hsu(a)mediatek.corp-partner.google.com>

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[XS] Change in coreboot[main]: mb/google/corsola: Add new board variant Ponyta360
by Yang Wu (Code Review) 18 Dec '24

18 Dec '24

Attention is currently required from: Hung-Te Lin, Xinxiong Xu, Yu-Ping Wu. Yang Wu has posted comments on this change by Yang Wu. ( https://review.coreboot.org/c/coreboot/+/85652?usp=email ) Change subject: mb/google/corsola: Add new board variant Ponyta360 ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/85652/comment/f76d8b6f_15695bb4?us… : PS1, Line 7: mb/google/corsola: Add new board variant Ponyta360 > Do Ponyta and Ponyta360 need to be different coreboot boards? As [b:375298183](https://partnerissuetracker.corp.google.com/issues/375298183) metioned, Ponyta360 and Ponyta will not use common FW, we are separating Ponyta360 as an independent project. -- To view, visit https://review.coreboot.org/c/coreboot/+/85652?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic0ddbfc667d1ba583f3cb95f60c73eb344b454c6 Gerrit-Change-Number: 85652 Gerrit-PatchSet: 1 Gerrit-Owner: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Xinxiong Xu <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Xinxiong Xu <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Wed, 18 Dec 2024 09:53:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com>

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