coreboot-gerrit December 2024

coreboot-gerrit@coreboot.org

1 participants
3018 discussions

[S] Change in coreboot[main]: CEZANNE:AB recovery: Add offsets for A/B to amdfwtool command line
by Bao Zheng (Code Review) 18 Dec '24

18 Dec '24

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier, Zheng Bao. Hello Zheng Bao, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/85658?usp=email to review the following change. Change subject: CEZANNE:AB recovery: Add offsets for A/B to amdfwtool command line ...................................................................... CEZANNE:AB recovery: Add offsets for A/B to amdfwtool command line Change-Id: Ib6a65b935b234df7a7b8d95c02694d2068da7a9f Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M src/soc/amd/cezanne/Kconfig M src/soc/amd/cezanne/Makefile.mk 2 files changed, 12 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/85658/1 diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index c6846a1..cd1cd07 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -410,7 +410,7 @@ config PSP_AB_RECOVERY bool "Use A/B Recovery scheme" - default n + default y help Enable the PSP A/B Recovery mechanism diff --git a/src/soc/amd/cezanne/Makefile.mk b/src/soc/amd/cezanne/Makefile.mk index 3983aaa..7cc0cd9 100644 --- a/src/soc/amd/cezanne/Makefile.mk +++ b/src/soc/amd/cezanne/Makefile.mk @@ -48,6 +48,14 @@ CEZANNE_FW_B_POSITION=$(call int-add, \ $(call get_fmap_value,FMAP_SECTION_FW_MAIN_B_START) $(AMD_FW_AB_POSITION)) + +ifeq ($(CONFIG_PSP_AB_RECOVERY), y) +CEZANNE_FW_A_RECOVERY=$(call int-add, \ + $(call get_fmap_value,FMAP_SECTION_PARTITIION_START) 4096) +CEZANNE_FW_B_RECOVERY=$(call int-add, \ + $(call get_fmap_value,FMAP_SECTION_BCOPY_START) 4096) +endif + # # PSP Directory Table items # @@ -182,10 +190,12 @@ OPT_WHITELIST_FILE=$(call add_opt_prefix, $(PSP_WHITELIST_FILE), --whitelist) OPT_SPL_TABLE_FILE=$(call add_opt_prefix, $(SPL_TABLE_FILE), --spl-table) -OPT_RECOVERY_AB=$(call add_opt_prefix, $(CONFIG_PSP_RECOVERY_AB), --recovery-ab) +OPT_RECOVERY_AB=$(if $(CONFIG_PSP_AB_RECOVERY), --recovery-ab) OPT_BIOS_AMDCOMPRESS=$(if $(CONFIG_CBFS_VERIFICATION), --elfcopy, --compress) OPT_BIOS_FWCOMPRESS=$(if $(CONFIG_CBFS_VERIFICATION), --bios-bin-uncomp) +OPT_RECOVERY_AB+=$(if $(CONFIG_PSP_AB_RECOVERY), --recovery-a-location $(call _tohex, $(CEZANNE_FW_A_RECOVERY)) --recovery-b-location $(call _tohex, $(CEZANNE_FW_B_RECOVERY))) + AMDFW_COMMON_ARGS=$(OPT_PSP_APCB_FILES) \ $(OPT_PSP_NVRAM_BASE) \ $(OPT_PSP_NVRAM_SIZE) \ -- To view, visit https://review.coreboot.org/c/coreboot/+/85658?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib6a65b935b234df7a7b8d95c02694d2068da7a9f Gerrit-Change-Number: 85658 Gerrit-PatchSet: 1 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Zheng Bao Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

1 0

[S] Change in coreboot[main]: soc/amd: Add A/B recovery support to AMD SOC
by Bao Zheng (Code Review) 18 Dec '24

18 Dec '24

Attention is currently required from: Bao Zheng, Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier, Zheng Bao. Hello Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier, Zheng Bao, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85647?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: soc/amd: Add A/B recovery support to AMD SOC ...................................................................... soc/amd: Add A/B recovery support to AMD SOC Copy the settings from Cezanne. 1. Add A/B data address to command line. 2. Enable CBFS verificatin if A/B recovery is enabled. 3. Do not compress the bootblock binary. Change-Id: Iaa8c4175285c5ceb16972ea57f0c0ca0403d8b84 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M src/soc/amd/glinda/Kconfig M src/soc/amd/glinda/Makefile.mk M src/soc/amd/phoenix/Kconfig M src/soc/amd/phoenix/Makefile.mk 4 files changed, 46 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/85647/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85647?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iaa8c4175285c5ceb16972ea57f0c0ca0403d8b84 Gerrit-Change-Number: 85647 Gerrit-PatchSet: 2 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

1 0

[M] Change in coreboot[main]: ec/google/chromeec: Publish LPC GMR address range via CREC _CRS
by Subrata Banik (Code Review) 18 Dec '24

18 Dec '24

Attention is currently required from: Boris Mittelberg, Gwendal Grignou, Kapil Porwal. Subrata Banik has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/85603?usp=email ) Change subject: ec/google/chromeec: Publish LPC GMR address range via CREC _CRS ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/85603/comment/757570a4_1970fae3?us… : PS2, Line 17: > Could you please add ACPI code with and without this CL? the DSDT entry is almost similar what I have added in this cros_ec.asl file hence, I have added more meaningful information about how OS is using this newly exposed range. I hope this information is useful. -- To view, visit https://review.coreboot.org/c/coreboot/+/85603?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib3ea3e2a482f9eceaa8c15e38b7e708b156bc978 Gerrit-Change-Number: 85603 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Gwendal Grignou <gwendal(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Gwendal Grignou <gwendal(a)chromium.org> Gerrit-Attention: Boris Mittelberg <bmbm(a)google.com> Gerrit-Comment-Date: Wed, 18 Dec 2024 14:31:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kapil Porwal <kapilporwal(a)google.com>

1 0

[M] Change in coreboot[main]: ec/google/chromeec: Publish LPC GMR address range via CREC _CRS
by Subrata Banik (Code Review) 18 Dec '24

18 Dec '24

Attention is currently required from: Boris Mittelberg, Gwendal Grignou, Subrata Banik. Hello Boris Mittelberg, Caveh Jalali, Gwendal Grignou, Kapil Porwal, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85603?usp=email to look at the new patch set (#3). Change subject: ec/google/chromeec: Publish LPC GMR address range via CREC _CRS ...................................................................... ec/google/chromeec: Publish LPC GMR address range via CREC _CRS This change allows the Chrome EC (CREC) ACPI device to publish the LPC Generic Memory Range (GMR) address range using the _CRS method. The Google CREC driver can now parse this information to determine the MMIO address map, enabling access to the LPC GMR register space. This addresses the issue where the CREC driver was unable to automatically determine the LPC GMR base address. TEST=Able to build and boot google/brox. without this patch: brox-rev0 ~ # cat /proc/iomem | grep fe0 fe000000-fe00ffff : INTC1026:00 fe000000-fe00ffff : intel_scu_ipc fe03e000-fe03efff : 0000:00:1e.0 fe03e000-fe03e1ff : lpss_dev fe03e000-fe03e1ff : serial fe03e200-fe03e2ff : lpss_priv fe03e800-fe03efff : idma64.4 fe03e800-fe03efff : idma64.4 idma64.4 with this patch: brox-rev0 ~ # cat /proc/iomem | grep fe0 fe000000-fe00ffff : INTC1026:00 fe000000-fe00ffff : intel_scu_ipc fe03e000-fe03efff : 0000:00:1e.0 fe03e000-fe03e1ff : lpss_dev fe03e000-fe03e1ff : serial fe03e200-fe03e2ff : lpss_priv fe03e800-fe03efff : idma64.4 fe03e800-fe03efff : idma64.4 idma64.4 fe0b0000-fe0bffff : GOOG0004:00 Change-Id: Ib3ea3e2a482f9eceaa8c15e38b7e708b156bc978 Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/ec/google/chromeec/Kconfig M src/ec/google/chromeec/acpi/cros_ec.asl 2 files changed, 35 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/85603/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/85603?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib3ea3e2a482f9eceaa8c15e38b7e708b156bc978 Gerrit-Change-Number: 85603 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Gwendal Grignou <gwendal(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Gwendal Grignou <gwendal(a)chromium.org> Gerrit-Attention: Boris Mittelberg <bmbm(a)google.com>

1 0

[M] Change in coreboot[main]: soc/amd/common: Add partition B for bootblock B
by Bao Zheng (Code Review) 18 Dec '24

18 Dec '24

Attention is currently required from: Zheng Bao. Hello Zheng Bao, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/85657?usp=email to review the following change. Change subject: soc/amd/common: Add partition B for bootblock B ...................................................................... soc/amd/common: Add partition B for bootblock B Change-Id: I12e956f36b5a22eecd1fd207c346a928c170c16e Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M src/soc/amd/common/Makefile.mk M src/soc/amd/common/block/psp/Makefile.mk 2 files changed, 45 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/85657/1 diff --git a/src/soc/amd/common/Makefile.mk b/src/soc/amd/common/Makefile.mk index 626260f..dcdeb71 100644 --- a/src/soc/amd/common/Makefile.mk +++ b/src/soc/amd/common/Makefile.mk @@ -40,22 +40,49 @@ amd_microcode_bins += $(wildcard ${FIRMWARE_LOCATION}/*U?odePatch*.bin) +AB_RECOVERY=$(CONFIG_PSP_AB_RECOVERY) +ifeq ($(AB_RECOVERY),y) +BOOTBLOCK_SOURCE=$(obj)/amdfw.rom.ra +BOOTBLOCK_SOURCE_B=$(obj)/amdfw.rom.rb +else +BOOTBLOCK_SOURCE=$(obj)/amdfw.rom +endif + ifeq ($(CONFIG_RESET_VECTOR_IN_RAM),y) -$(objcbfs)/bootblock.bin: $(obj)/amdfw.rom $(obj)/fmap_config.h +$(objcbfs)/bootblock.bin: $(BOOTBLOCK_SOURCE) $(obj)/fmap_config.h cp $< $@ amdfw_region_start=$(subst $(spc),,FMAP_SECTION_$(call regions-for-file,apu/amdfw)_START) +ifeq ($(AB_RECOVERY),y) +amdfw_offset=4096 +$(call add_intermediate, add_amdfw, $(obj)/amdfw.rom) + printf " DD Adding AMD Firmware at ROM offset 0x%x\n" \ + "$(CONFIG_AMD_FWM_POSITION)" + $(CBFSTOOL) $(obj)/coreboot.pre write -r EFS -f $(obj)/amdfw.rom --fill-upward + +$(obj)/amdfw.rom.rb: $(obj)/amdfw.rom +$(obj)/amdfw.rom.ra: $(obj)/amdfw.rom + +else amdfw_offset=$(call int-subtract, \ $(CONFIG_AMD_FWM_POSITION) \ $(call int-subtract, \ $(call get_fmap_value,$(amdfw_region_start)) \ $(call get_fmap_value,FMAP_SECTION_FLASH_START))) +endif -add_bootblock = \ - $(CBFSTOOL) $(1) add -f $(2) -n apu/amdfw -t amdfw \ - -b $(amdfw_offset) -r $(call regions-for-file,apu/amdfw) \ - $(CBFSTOOL_ADD_CMD_OPTIONS) - +add_bootblock= \ + for region in $(subst $(comma),$(spc),$(call regions-for-file,apu/amdfw)); do \ + if [ $$region = COREBOOT ]; then \ + $(CBFSTOOL) $(1) add -f $(2) -n apu/amdfw -t amdfw \ + -b $(amdfw_offset) -r $$region \ + $(CBFSTOOL_ADD_CMD_OPTIONS) ; \ + elif [ $$region = COREBOOTB ]; then \ + $(CBFSTOOL) $(1) add -f $(obj)/amdfw.rom.rb -n apu/amdfw -t amdfw \ + -b $(amdfw_offset) -r $$region \ + $(CBFSTOOL_ADD_CMD_OPTIONS) ; \ + fi ; \ + done endif # ifeq ($(CONFIG_RESET_VECTOR_IN_RAM),y) ifeq ($(CONFIG_VBOOT_GSCVD),y) diff --git a/src/soc/amd/common/block/psp/Makefile.mk b/src/soc/amd/common/block/psp/Makefile.mk index f90f94b..150d406 100644 --- a/src/soc/amd/common/block/psp/Makefile.mk +++ b/src/soc/amd/common/block/psp/Makefile.mk @@ -39,3 +39,15 @@ ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_PSP_SPL) += spl_fuse.c endif # CONFIG_SOC_AMD_COMMON_BLOCK_PSP_GEN2 + +regions-for-file += $(if $(filter \ + %/romstage \ + %/ramstage \ + %/dsdt.aml \ + %/payload \ + fspm%.bin \ + fsps%.bin \ + cpu_microcode%.bin \ + pci%.rom \ + apu/amdfw \ + ,$(1)), $(if $(call get_fmap_value,FMAP_SECTION_BCOPY_START),COREBOOTB)) -- To view, visit https://review.coreboot.org/c/coreboot/+/85657?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I12e956f36b5a22eecd1fd207c346a928c170c16e Gerrit-Change-Number: 85657 Gerrit-PatchSet: 1 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Attention: Zheng Bao

1 0

[S] Change in coreboot[main]: payloads/LinuxBoot: Build x86_64 with host toolchain
by Lean Sheng Tan (Code Review) 18 Dec '24

18 Dec '24

Attention is currently required from: Christian Walter, Elyes HAOUAS, Felix Singer, Frans Hendriks, Martin L Roth, Maximilian Brune. Lean Sheng Tan has posted comments on this change by Maximilian Brune. ( https://review.coreboot.org/c/coreboot/+/83990?usp=email ) Change subject: payloads/LinuxBoot: Build x86_64 with host toolchain ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83990?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icaf56d6991d79f629e9ba8c901b441d81921d594 Gerrit-Change-Number: 83990 Gerrit-PatchSet: 2 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Elyes HAOUAS Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Elyes HAOUAS Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Comment-Date: Wed, 18 Dec 2024 14:06:20 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

1 0

[XS] Change in coreboot[main]: abrecovery: Add setting boot status and corrupt type
by Bao Zheng (Code Review) 18 Dec '24

18 Dec '24

Attention is currently required from: Bao Zheng, Julius Werner, Zheng Bao. Hello Julius Werner, Zheng Bao, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85645?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: abrecovery: Add setting boot status and corrupt type ...................................................................... abrecovery: Add setting boot status and corrupt type Change-Id: I55a379b9c9f85fabbd8a1f98fbef3f57d7d8118d Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M src/lib/cbfs.c M src/lib/prog_loaders.c 2 files changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/85645/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85645?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I55a379b9c9f85fabbd8a1f98fbef3f57d7d8118d Gerrit-Change-Number: 85645 Gerrit-PatchSet: 2 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Zheng Bao

1 0

[XS] Change in coreboot[main]: mb/emulation/qemu-sbsa: Configure flash region for MMU
by Lean Sheng Tan (Code Review) 18 Dec '24

18 Dec '24

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85147?usp=email ) Change subject: mb/emulation/qemu-sbsa: Configure flash region for MMU ...................................................................... mb/emulation/qemu-sbsa: Configure flash region for MMU Since QEMU commit 728b923f548d ("target/arm: Do memory type alignment check when translation enabled") alignment is checked for device memory. That causes exceptions during bootup of coreboot trying to load things (e.g. stages) from the memory mapped flash. To fix it the memory mapped flash region will be marked as MA_MEM (normal memory) instead of MA_DEV (device memory). Technically that isn't 100% correct, but avoids having to write a custom memory mapped flash driver that checks for alignment on all accesses. Since it is emulation and therefore always normal memory anyway, there shouldn't be any side effects. Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> Change-Id: I98bd1a18495e3d153ce53abec8686c7871ee12c5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/85147 Reviewed-by: David Milosevic <David.Milosevic(a)9elements.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> --- M src/mainboard/emulation/qemu-sbsa/bootblock.c 1 file changed, 3 insertions(+), 0 deletions(-) Approvals: David Milosevic: Looks good to me, but someone else must approve build bot (Jenkins): Verified Lean Sheng Tan: Looks good to me, approved diff --git a/src/mainboard/emulation/qemu-sbsa/bootblock.c b/src/mainboard/emulation/qemu-sbsa/bootblock.c index b38df6e..53eb9af 100644 --- a/src/mainboard/emulation/qemu-sbsa/bootblock.c +++ b/src/mainboard/emulation/qemu-sbsa/bootblock.c @@ -4,6 +4,7 @@ #include <bootblock_common.h> #include <symbols.h> +DECLARE_REGION(flash); void bootblock_mainboard_init(void) { mmu_init(); @@ -13,6 +14,8 @@ /* Set a dummy value for DRAM. ramstage should update the mapping. */ mmu_config_range(_dram, ((size_t) CONFIG_DRAM_SIZE_MB) * MiB, MA_MEM | MA_RW); + mmu_config_range(_flash, REGION_SIZE(flash), MA_MEM | MA_RO | MA_MEM_NC); + mmu_config_range(_ttb, REGION_SIZE(ttb), MA_MEM | MA_S | MA_RW); mmu_config_range(_bootblock, REGION_SIZE(bootblock), MA_MEM | MA_S | MA_RW); mmu_config_range(_ramstage, REGION_SIZE(ramstage), MA_MEM | MA_S | MA_RW); -- To view, visit https://review.coreboot.org/c/coreboot/+/85147?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I98bd1a18495e3d153ce53abec8686c7871ee12c5 Gerrit-Change-Number: 85147 Gerrit-PatchSet: 2 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

[XS] Change in coreboot[main]: mb/emulation/qemu-sbsa: Configure flash region for MMU
by Lean Sheng Tan (Code Review) 18 Dec '24

18 Dec '24

Attention is currently required from: Julius Werner, Maximilian Brune, Naresh Solanki. Lean Sheng Tan has posted comments on this change by Maximilian Brune. ( https://review.coreboot.org/c/coreboot/+/85147?usp=email ) Change subject: mb/emulation/qemu-sbsa: Configure flash region for MMU ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85147?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I98bd1a18495e3d153ce53abec8686c7871ee12c5 Gerrit-Change-Number: 85147 Gerrit-PatchSet: 1 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Comment-Date: Wed, 18 Dec 2024 13:13:58 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

1 0

[XL] Change in coreboot[main]: drivers/option: Add forms in cbtables
by Werner Zeh (Code Review) 18 Dec '24

18 Dec '24

Attention is currently required from: Angel Pons, Benjamin Doron, Lean Sheng Tan, Martin L Roth, Maximilian Brune, Nico Huber, Patrick Rudolph, Sean Rhodes. Werner Zeh has posted comments on this change by Angel Pons. ( https://review.coreboot.org/c/coreboot/+/74121?usp=email ) Change subject: drivers/option: Add forms in cbtables ...................................................................... Patch Set 29: (3 comments) Patchset: PS29: Just two small things. I marked them as resolved right away in order to not block things here. If you think there is value in my findings feel free to update the patch. File Documentation/drivers/cfr.md: https://review.coreboot.org/c/coreboot/+/74121/comment/cf6b0618_10ed885a?us… : PS29, Line 211: CFR_OPTFLAG_GRAYOUT This strongly sounds like adopting UEFI vfr methods. I would rather call it ```CFR_OPTFLAG_DISABLED``` or ```CFR_OPTFLAG_INACTIVE``` as the GRAYOUT strictly associates (at least for me) with a graphical menu which the user can walk through. This is not the intention you have in mind with this implementation, though. As I do not want to block this it is up to you to decide, hence setting it as resolved. File src/drivers/option/cfr.c: https://review.coreboot.org/c/coreboot/+/74121/comment/4e01d13e_9a9643c6?us… : PS29, Line 42: char *data Why redefining? Use ```char *data;`` in line 32 right away. -- To view, visit https://review.coreboot.org/c/coreboot/+/74121?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I304de7d26d79245a2e31a6d01f6c5643b31cb772 Gerrit-Change-Number: 74121 Gerrit-PatchSet: 29 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Daniel Maslowski <info(a)orangecms.org> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Wed, 18 Dec 2024 12:59:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit December 2024