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[XS] Change in coreboot[main]: soc/mediatek/common: Move SPM_SYSTEM_BASE_OFFSET to soc folders
by Yidi Lin (Code Review) 19 Dec '24

19 Dec '24

Yidi Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85625?usp=email ) ( 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/mediatek/common: Move SPM_SYSTEM_BASE_OFFSET to soc folders ...................................................................... soc/mediatek/common: Move SPM_SYSTEM_BASE_OFFSET to soc folders MT8196's SPM_SYSTEM_BASE_OFFSET has a different offset due to the hardware design. To avoid adding a new kconfig for differentiation, migrate this definition into SoC specific value. BUG=none TEST=emerge-geralt coreboot && emerge-corsola coreboot Change-Id: I5df510d5d05a0594d87e7e96e1e03e20a018785f Signed-off-by: Yidi Lin <yidilin(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85625 Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/mediatek/common/include/soc/spm_common.h M src/soc/mediatek/mt8186/include/soc/spm.h M src/soc/mediatek/mt8188/include/soc/spm.h M src/soc/mediatek/mt8192/include/soc/spm.h M src/soc/mediatek/mt8195/include/soc/spm.h 5 files changed, 7 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved diff --git a/src/soc/mediatek/common/include/soc/spm_common.h b/src/soc/mediatek/common/include/soc/spm_common.h index 6a65b2c..f45b59e 100644 --- a/src/soc/mediatek/common/include/soc/spm_common.h +++ b/src/soc/mediatek/common/include/soc/spm_common.h @@ -5,8 +5,6 @@ #include <soc/mcu_common.h> -#define SPM_SYSTEM_BASE_OFFSET 0x40000000 - struct pcm_desc { u32 pmem_words; u32 total_words; diff --git a/src/soc/mediatek/mt8186/include/soc/spm.h b/src/soc/mediatek/mt8186/include/soc/spm.h index cffc523..9368916 100644 --- a/src/soc/mediatek/mt8186/include/soc/spm.h +++ b/src/soc/mediatek/mt8186/include/soc/spm.h @@ -14,6 +14,7 @@ #include <soc/spm_common.h> #include <types.h> +#define SPM_SYSTEM_BASE_OFFSET 0x40000000 #define SPM_INIT_DONE_US 20 #define CLK_SCP_CFG_0 (IO_PHYS + 0x200) diff --git a/src/soc/mediatek/mt8188/include/soc/spm.h b/src/soc/mediatek/mt8188/include/soc/spm.h index 043a102..529ad18 100644 --- a/src/soc/mediatek/mt8188/include/soc/spm.h +++ b/src/soc/mediatek/mt8188/include/soc/spm.h @@ -9,6 +9,8 @@ #include <soc/spm_common.h> #include <types.h> +#define SPM_SYSTEM_BASE_OFFSET 0x40000000 + /* SPM READ/WRITE CFG */ #define SPM_PROJECT_CODE 0xb16 #define SPM_REGWR_CFG_KEY (SPM_PROJECT_CODE << 16) diff --git a/src/soc/mediatek/mt8192/include/soc/spm.h b/src/soc/mediatek/mt8192/include/soc/spm.h index cc5052b..065053a 100644 --- a/src/soc/mediatek/mt8192/include/soc/spm.h +++ b/src/soc/mediatek/mt8192/include/soc/spm.h @@ -9,6 +9,8 @@ #include <soc/spm_common.h> #include <types.h> +#define SPM_SYSTEM_BASE_OFFSET 0x40000000 + /* SPM READ/WRITE CFG */ #define SPM_PROJECT_CODE 0xb16 #define SPM_REGWR_CFG_KEY (SPM_PROJECT_CODE << 16) diff --git a/src/soc/mediatek/mt8195/include/soc/spm.h b/src/soc/mediatek/mt8195/include/soc/spm.h index c118f06..67873ec 100644 --- a/src/soc/mediatek/mt8195/include/soc/spm.h +++ b/src/soc/mediatek/mt8195/include/soc/spm.h @@ -9,6 +9,8 @@ #include <soc/spm_common.h> #include <types.h> +#define SPM_SYSTEM_BASE_OFFSET 0x40000000 + /* SPM READ/WRITE CFG */ #define SPM_PROJECT_CODE 0xb16 #define SPM_REGWR_CFG_KEY (SPM_PROJECT_CODE << 16) -- To view, visit https://review.coreboot.org/c/coreboot/+/85625?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5df510d5d05a0594d87e7e96e1e03e20a018785f Gerrit-Change-Number: 85625 Gerrit-PatchSet: 4 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: soc/mediatek/common: Use array to represent spm_sw_rsv registers
by Yidi Lin (Code Review) 19 Dec '24

19 Dec '24

Yidi Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85624?usp=email ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/mediatek/common: Use array to represent spm_sw_rsv registers ...................................................................... soc/mediatek/common: Use array to represent spm_sw_rsv registers This patch only revises the registers used by common/spm.c. BUG=none TEST=emerge-geralt coreboot && emerge-rauru corsola Change-Id: I7f49e18e7907d59944e6eb3554df667d12b07399 Signed-off-by: Yidi Lin <yidilin(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85624 Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/mediatek/common/spm.c M src/soc/mediatek/mt8186/include/soc/spm.h M src/soc/mediatek/mt8188/include/soc/spm.h M src/soc/mediatek/mt8192/include/soc/spm.h M src/soc/mediatek/mt8195/include/soc/spm.h 5 files changed, 9 insertions(+), 34 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved diff --git a/src/soc/mediatek/common/spm.c b/src/soc/mediatek/common/spm.c index 8a57af7..65372f9 100644 --- a/src/soc/mediatek/common/spm.c +++ b/src/soc/mediatek/common/spm.c @@ -67,8 +67,8 @@ write32(&mtk_spm->spm_sw_flag_0, pcm_flags); write32(&mtk_spm->spm_sw_flag_1, pcm_flags1); - write32(&mtk_spm->spm_sw_rsv_7, pcm_flags); - write32(&mtk_spm->spm_sw_rsv_8, pcm_flags1); + write32(&mtk_spm->spm_sw_rsv[7], pcm_flags); + write32(&mtk_spm->spm_sw_rsv[8], pcm_flags1); } static void spm_parse_firmware(struct mtk_mcu *mcu) diff --git a/src/soc/mediatek/mt8186/include/soc/spm.h b/src/soc/mediatek/mt8186/include/soc/spm.h index b402b2c..cffc523 100644 --- a/src/soc/mediatek/mt8186/include/soc/spm.h +++ b/src/soc/mediatek/mt8186/include/soc/spm.h @@ -415,15 +415,7 @@ uint32_t spm_sw_debug_0; uint32_t spm_sw_flag_1; uint32_t spm_sw_debug_1; - uint32_t spm_sw_rsv_0; - uint32_t spm_sw_rsv_1; - uint32_t spm_sw_rsv_2; - uint32_t spm_sw_rsv_3; - uint32_t spm_sw_rsv_4; - uint32_t spm_sw_rsv_5; - uint32_t spm_sw_rsv_6; - uint32_t spm_sw_rsv_7; - uint32_t spm_sw_rsv_8; + uint32_t spm_sw_rsv[9]; uint32_t spm_bk_wake_event; uint32_t spm_bk_vtcxo_dur; uint32_t spm_bk_wake_misc; diff --git a/src/soc/mediatek/mt8188/include/soc/spm.h b/src/soc/mediatek/mt8188/include/soc/spm.h index 240805c6..043a102 100644 --- a/src/soc/mediatek/mt8188/include/soc/spm.h +++ b/src/soc/mediatek/mt8188/include/soc/spm.h @@ -733,15 +733,7 @@ u32 spm_sw_debug_0; u32 spm_sw_flag_1; u32 spm_sw_debug_1; - u32 spm_sw_rsv_0; - u32 spm_sw_rsv_1; - u32 spm_sw_rsv_2; - u32 spm_sw_rsv_3; - u32 spm_sw_rsv_4; - u32 spm_sw_rsv_5; - u32 spm_sw_rsv_6; - u32 spm_sw_rsv_7; - u32 spm_sw_rsv_8; + u32 spm_sw_rsv[9]; u32 spm_bk_wake_event; u32 spm_bk_vtcxo_dur; u32 spm_bk_wake_misc; diff --git a/src/soc/mediatek/mt8192/include/soc/spm.h b/src/soc/mediatek/mt8192/include/soc/spm.h index 4c24a48..cc5052b 100644 --- a/src/soc/mediatek/mt8192/include/soc/spm.h +++ b/src/soc/mediatek/mt8192/include/soc/spm.h @@ -603,9 +603,8 @@ u32 spm_sw_flag_0; u32 spm_sw_debug_0; u32 spm_sw_flag_1; - u32 reserved11[8]; - u32 spm_sw_rsv_7; - u32 spm_sw_rsv_8; + u32 spm_sw_debug_1; + u32 spm_sw_rsv[9]; u32 reserved12[203]; u32 spm_ack_chk_con_3; u32 spm_ack_chk_pc_3; @@ -645,8 +644,8 @@ check_member(mtk_spm_regs, spm_force_dvfs, 0x4fc); check_member(mtk_spm_regs, spm_sw_flag_0, 0x600); check_member(mtk_spm_regs, spm_sw_flag_1, 0x608); -check_member(mtk_spm_regs, spm_sw_rsv_7, 0x62c); -check_member(mtk_spm_regs, spm_sw_rsv_8, 0x630); +check_member(mtk_spm_regs, spm_sw_rsv[7], 0x62c); +check_member(mtk_spm_regs, spm_sw_rsv[8], 0x630); check_member(mtk_spm_regs, spm_ack_chk_con_3, 0x960); check_member(mtk_spm_regs, spm_ack_chk_timer_3, 0x96c); check_member(mtk_spm_regs, sys_timer_con, 0x98c); diff --git a/src/soc/mediatek/mt8195/include/soc/spm.h b/src/soc/mediatek/mt8195/include/soc/spm.h index 0974ee1..c118f06 100644 --- a/src/soc/mediatek/mt8195/include/soc/spm.h +++ b/src/soc/mediatek/mt8195/include/soc/spm.h @@ -705,15 +705,7 @@ u32 spm_sw_debug_0; u32 spm_sw_flag_1; u32 spm_sw_debug_1; - u32 spm_sw_rsv_0; - u32 spm_sw_rsv_1; - u32 spm_sw_rsv_2; - u32 spm_sw_rsv_3; - u32 spm_sw_rsv_4; - u32 spm_sw_rsv_5; - u32 spm_sw_rsv_6; - u32 spm_sw_rsv_7; - u32 spm_sw_rsv_8; + u32 spm_sw_rsv[9]; u32 spm_bk_wake_event; u32 spm_bk_vtcxo_dur; u32 spm_bk_wake_misc; -- To view, visit https://review.coreboot.org/c/coreboot/+/85624?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7f49e18e7907d59944e6eb3554df667d12b07399 Gerrit-Change-Number: 85624 Gerrit-PatchSet: 3 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: soc/mediatek/common: Move some functions to spm_v1.c
by Yidi Lin (Code Review) 19 Dec '24

19 Dec '24

Yidi Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85623?usp=email ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/mediatek/common: Move some functions to spm_v1.c ...................................................................... soc/mediatek/common: Move some functions to spm_v1.c The init flow in `spm_init_pcm_register` and `spm_kick_pcm_to_run` is simplified on MT8196. And MT8196 does not have corresponded registers used by these two functions. Therefore, move these two function to a separated file and simply name it as spm_v1.c. BUG=none TEST=emerge-geralt coreboot && emerge-corsola coreboot Change-Id: I028d8f8ca8c9988d26d400f25ca09a2615541364 Signed-off-by: Yidi Lin <yidilin(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85623 Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/mediatek/common/include/soc/spm_common.h M src/soc/mediatek/common/spm.c A src/soc/mediatek/common/spm_v1.c M src/soc/mediatek/mt8186/Makefile.mk M src/soc/mediatek/mt8188/Makefile.mk M src/soc/mediatek/mt8192/Makefile.mk M src/soc/mediatek/mt8195/Makefile.mk 7 files changed, 53 insertions(+), 45 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved diff --git a/src/soc/mediatek/common/include/soc/spm_common.h b/src/soc/mediatek/common/include/soc/spm_common.h index 820fbca..6a65b2c 100644 --- a/src/soc/mediatek/common/include/soc/spm_common.h +++ b/src/soc/mediatek/common/include/soc/spm_common.h @@ -27,5 +27,8 @@ void spm_set_wakeup_event(const struct pwr_ctrl *pwrctrl); void spm_extern_initialize(void); int spm_init(void); +void spm_set_pcm_flags(const struct pwr_ctrl *pwrctrl); +void spm_init_pcm_register(void); +void spm_kick_pcm_to_run(const struct pwr_ctrl *pwrctrl); #endif /* SOC_MEDIATEK_SPM_COMMON_H */ diff --git a/src/soc/mediatek/common/spm.c b/src/soc/mediatek/common/spm.c index e39f3da..8a57af7 100644 --- a/src/soc/mediatek/common/spm.c +++ b/src/soc/mediatek/common/spm.c @@ -51,22 +51,7 @@ setbits32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB); } -static void spm_init_pcm_register(void) -{ - /* Init r0 with POWER_ON_VAL0 */ - write32(&mtk_spm->pcm_reg_data_ini, - read32(&mtk_spm->spm_power_on_val0)); - write32(&mtk_spm->pcm_pwr_io_en, PCM_RF_SYNC_R0); - write32(&mtk_spm->pcm_pwr_io_en, 0); - - /* Init r7 with POWER_ON_VAL1 */ - write32(&mtk_spm->pcm_reg_data_ini, - read32(&mtk_spm->spm_power_on_val1)); - write32(&mtk_spm->pcm_pwr_io_en, PCM_RF_SYNC_R7); - write32(&mtk_spm->pcm_pwr_io_en, 0); -} - -static void spm_set_pcm_flags(const struct pwr_ctrl *pwrctrl) +void spm_set_pcm_flags(const struct pwr_ctrl *pwrctrl) { u32 pcm_flags = pwrctrl->pcm_flags, pcm_flags1 = pwrctrl->pcm_flags1; @@ -86,31 +71,6 @@ write32(&mtk_spm->spm_sw_rsv_8, pcm_flags1); } -static void spm_kick_pcm_to_run(const struct pwr_ctrl *pwrctrl) -{ - /* Waiting for loading SPMFW done*/ - while (read32(&mtk_spm->md32pcm_dma0_rlct) != 0x0) - ; - - /* Init register to match PCM expectation */ - write32(&mtk_spm->spm_bus_protect_mask_b, SPM_BUS_PROTECT_MASK_B_DEF); - write32(&mtk_spm->spm_bus_protect2_mask_b, - SPM_BUS_PROTECT2_MASK_B_DEF); - write32(&mtk_spm->pcm_reg_data_ini, 0); - - spm_set_pcm_flags(pwrctrl); - - /* Kick PCM to run (only toggle PCM_KICK) */ - setbits32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB); - - /* Reset md32pcm */ - SET32_BITFIELDS(&mtk_spm->md32pcm_cfgreg_sw_rstn, - MD32PCM_CFGREG_SW_RSTN_RESET, 1); - - /* Waiting for SPM init done */ - udelay(SPM_INIT_DONE_US); -} - static void spm_parse_firmware(struct mtk_mcu *mcu) { size_t file_size, copy_size; diff --git a/src/soc/mediatek/common/spm_v1.c b/src/soc/mediatek/common/spm_v1.c new file mode 100644 index 0000000..cbae66e --- /dev/null +++ b/src/soc/mediatek/common/spm_v1.c @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/mmio.h> +#include <soc/spm.h> +#include <delay.h> + +void spm_init_pcm_register(void) +{ + /* Init r0 with POWER_ON_VAL0 */ + write32(&mtk_spm->pcm_reg_data_ini, + read32(&mtk_spm->spm_power_on_val0)); + write32(&mtk_spm->pcm_pwr_io_en, PCM_RF_SYNC_R0); + write32(&mtk_spm->pcm_pwr_io_en, 0); + + /* Init r7 with POWER_ON_VAL1 */ + write32(&mtk_spm->pcm_reg_data_ini, + read32(&mtk_spm->spm_power_on_val1)); + write32(&mtk_spm->pcm_pwr_io_en, PCM_RF_SYNC_R7); + write32(&mtk_spm->pcm_pwr_io_en, 0); +} + +void spm_kick_pcm_to_run(const struct pwr_ctrl *pwrctrl) +{ + /* Waiting for loading SPMFW done*/ + while (read32(&mtk_spm->md32pcm_dma0_rlct) != 0x0) + ; + + /* Init register to match PCM expectation */ + write32(&mtk_spm->spm_bus_protect_mask_b, SPM_BUS_PROTECT_MASK_B_DEF); + write32(&mtk_spm->spm_bus_protect2_mask_b, + SPM_BUS_PROTECT2_MASK_B_DEF); + write32(&mtk_spm->pcm_reg_data_ini, 0); + + spm_set_pcm_flags(pwrctrl); + + /* Kick PCM to run (only toggle PCM_KICK) */ + setbits32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB); + + /* Reset md32pcm */ + SET32_BITFIELDS(&mtk_spm->md32pcm_cfgreg_sw_rstn, + MD32PCM_CFGREG_SW_RSTN_RESET, 1); + + /* Waiting for SPM init done */ + udelay(SPM_INIT_DONE_US); +} diff --git a/src/soc/mediatek/mt8186/Makefile.mk b/src/soc/mediatek/mt8186/Makefile.mk index fda4180..0d44c2e 100644 --- a/src/soc/mediatek/mt8186/Makefile.mk +++ b/src/soc/mediatek/mt8186/Makefile.mk @@ -50,7 +50,7 @@ ramstage-y += ../common/pmic_wrap.c pmic_wrap.c pmif.c mt6366.c ramstage-y += ../common/rtc.c ../common/rtc_osc_init.c rtc.c ramstage-y += soc.c -ramstage-y += ../common/spm.c spm.c +ramstage-y += ../common/spm.c ../common/spm_v1.c spm.c ramstage-y += ../common/sspm.c ramstage-y += ../common/tps65132s.c ramstage-y += ../common/usb.c ../common/usb_secondary.c usb.c diff --git a/src/soc/mediatek/mt8188/Makefile.mk b/src/soc/mediatek/mt8188/Makefile.mk index e9e7088..3c5965b 100644 --- a/src/soc/mediatek/mt8188/Makefile.mk +++ b/src/soc/mediatek/mt8188/Makefile.mk @@ -56,7 +56,7 @@ ramstage-y += ../common/pmif_spmi.c pmif_spmi.c ramstage-y += ../common/rtc.c ../common/rtc_osc_init.c ../common/rtc_mt6359p.c ramstage-y += soc.c -ramstage-y += ../common/spm.c spm.c +ramstage-y += ../common/spm.c ../common/spm_v1.c spm.c ramstage-y += ../common/sspm.c ramstage-y += ../common/tps65132s.c ramstage-y += ../common/usb.c usb.c diff --git a/src/soc/mediatek/mt8192/Makefile.mk b/src/soc/mediatek/mt8192/Makefile.mk index 8b409ba..1c4baa8 100644 --- a/src/soc/mediatek/mt8192/Makefile.mk +++ b/src/soc/mediatek/mt8192/Makefile.mk @@ -49,7 +49,7 @@ ramstage-y += ../common/pmif.c ../common/pmif_init.c ramstage-y += ../common/rtc.c ../common/rtc_mt6359p.c ramstage-y += soc.c -ramstage-y += ../common/spm.c spm.c +ramstage-y += ../common/spm.c ../common/spm_v1.c spm.c ramstage-y += ../common/sspm.c ramstage-y += ../common/ufs.c ramstage-y += ../common/usb.c usb.c diff --git a/src/soc/mediatek/mt8195/Makefile.mk b/src/soc/mediatek/mt8195/Makefile.mk index 3ece4ad..f011f95 100644 --- a/src/soc/mediatek/mt8195/Makefile.mk +++ b/src/soc/mediatek/mt8195/Makefile.mk @@ -65,7 +65,7 @@ ramstage-y += ../common/pmif.c ../common/pmif_init.c ramstage-y += ../common/rtc.c ../common/rtc_mt6359p.c ramstage-y += soc.c -ramstage-y += ../common/spm.c spm.c +ramstage-y += ../common/spm.c ../common/spm_v1.c spm.c ramstage-y += ../common/sspm.c ramstage-y += ../common/ufs.c ramstage-y += ../common/usb.c usb.c -- To view, visit https://review.coreboot.org/c/coreboot/+/85623?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I028d8f8ca8c9988d26d400f25ca09a2615541364 Gerrit-Change-Number: 85623 Gerrit-PatchSet: 3 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: mb/google/fatcat: Suppress unnecessary extra space in device trees
by Jérémy Compostella (Code Review) 19 Dec '24

19 Dec '24

Jérémy Compostella has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/85661?usp=email ) Change subject: mb/google/fatcat: Suppress unnecessary extra space in device trees ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/85661?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I546e704fa1c525406edede24cf0b4485276b878e Gerrit-Change-Number: 85661 Gerrit-PatchSet: 1 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Comment-Date: Wed, 18 Dec 2024 23:30:30 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: mb/google/brya: Adjust EC memory map range to support indexed IO
by Jayvik Desai (Code Review) 19 Dec '24

19 Dec '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Kapil Porwal, Nick Vaccaro, Subrata Banik. Jayvik Desai has posted comments on this change by Jayvik Desai. ( https://review.coreboot.org/c/coreboot/+/85547?usp=email ) Change subject: mb/google/brya: Adjust EC memory map range to support indexed IO ...................................................................... Patch Set 6: (1 comment) This change is ready for review. File src/mainboard/google/brya/variants/baseboard/trulo/devicetree.cb: https://review.coreboot.org/c/coreboot/+/85547/comment/195e836e_871e8b45?us… : PS3, Line 11: # EC memory map range is 0x900-0x9ff and indexed access is through 0x380 > can you please follow https://review.coreboot. […] Updated, Can you confirm based on the range is the programmed value correct ? Thanks! -- To view, visit https://review.coreboot.org/c/coreboot/+/85547?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ide5026b35da7c00deab4464eedfca9d52d294fd6 Gerrit-Change-Number: 85547 Gerrit-PatchSet: 6 Gerrit-Owner: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Wed, 18 Dec 2024 23:01:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[S] Change in coreboot[main]: ec/google/chromeec: Add indexed IO support
by Jayvik Desai (Code Review) 19 Dec '24

19 Dec '24

Attention is currently required from: Boris Mittelberg, Caveh Jalali, Kapil Porwal, Subrata Banik. Jayvik Desai has posted comments on this change by Jayvik Desai. ( https://review.coreboot.org/c/coreboot/+/85449?usp=email ) Change subject: ec/google/chromeec: Add indexed IO support ...................................................................... Patch Set 5: (1 comment) This change is ready for review. File src/ec/google/chromeec/ec_commands.h: https://review.coreboot.org/c/coreboot/+/85449/comment/c1af111f_d35d2b77?us… : PS4, Line 152: 0x380 > +1 Added a Kconfig option -- To view, visit https://review.coreboot.org/c/coreboot/+/85449?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6c1aab3fc914eb5af2736a8ea3adf447040905e0 Gerrit-Change-Number: 85449 Gerrit-PatchSet: 5 Gerrit-Owner: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Boris Mittelberg <bmbm(a)google.com> Gerrit-Comment-Date: Wed, 18 Dec 2024 23:01:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jayvik Desai <jayvik(a)google.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Kapil Porwal <kapilporwal(a)google.com>

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[XS] Change in coreboot[main]: mb/google/brya: Adjust EC memory map range to support indexed IO
by Jayvik Desai (Code Review) 18 Dec '24

18 Dec '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Paul Menzel. Hello Dinesh Gehlot, Eric Lai, Kapil Porwal, Nick Vaccaro, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85547?usp=email to look at the new patch set (#5). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: mb/google/brya: Adjust EC memory map range to support indexed IO ...................................................................... mb/google/brya: Adjust EC memory map range to support indexed IO Adjust the EC memory map range for indexed IO access in trulo variant from 0x900 to 0x380 BUG=b:379224648 TEST= able to build nissa/trulo. Change-Id: Ide5026b35da7c00deab4464eedfca9d52d294fd6 Signed-off-by: Jayvik Desai <jayvik(a)google.com> --- M src/mainboard/google/brya/variants/baseboard/trulo/devicetree.cb 1 file changed, 5 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/85547/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/85547?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ide5026b35da7c00deab4464eedfca9d52d294fd6 Gerrit-Change-Number: 85547 Gerrit-PatchSet: 5 Gerrit-Owner: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org>

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[M] Change in coreboot[main]: lib/{fit,fit_payload}.c: Enhance support for FIT images
by Benjamin Doron (Code Review) 18 Dec '24

18 Dec '24

Attention is currently required from: Felix Held, Julius Werner, Lean Sheng Tan, Matt DeVillier, Maximilian Brune. Benjamin Doron has posted comments on this change by Benjamin Doron. ( https://review.coreboot.org/c/coreboot/+/84796?usp=email ) Change subject: lib/{fit,fit_payload}.c: Enhance support for FIT images ...................................................................... Patch Set 6: (1 comment) File src/lib/fit_payload.c: https://review.coreboot.org/c/coreboot/+/84796/comment/e288248c_ec8a20dd?us… : PS6, Line 118: /* We may want to check if relocation is needed and then at least do something: > nit: 5 lines is a bit long for short multiline comment style, maybe better use […] As it happens, I've just realised that our secondary images never need relocation: they're UEFI FVs, which I believe are position-independent, and they contain PEs. Those are probably (read: hopefully?) using RIP-relative addressing on x86, and in general, EDK2's loader will be doing relocation if the FV's PEs need it. Yes, that's pretty much it. I didn't want to lose the Gerrit comment so I added it to the code. Sure, we could spend time coding up a perfect solution, but it doesn't seem worth it: we at 9elements want to get UPL support in, and other people clearly haven't thought that FIT relocation is worth supporting, since the existing code didn't have it. And regarding the other props: I had seen a number of props in our FITs that weren't supported, and I was planning on digging into them sometime. I've done that now, and they're either UPL customisations or don't have all that much information to offer. For example, sure, we could start parsing `arch` (and EDK2's build script is getting that wrong too, so I'd have yet one more thing to fix...) but it doesn't matter. We really shouldn't be getting that wrong at build time. I'm going to write some code to detect if we need relocation, and then just have it print an error. Clearly, relocation isn't something we need all that often. -- To view, visit https://review.coreboot.org/c/coreboot/+/84796?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6a21954c0dc5fd820d135e8cd0599ce87903a1c0 Gerrit-Change-Number: 84796 Gerrit-PatchSet: 6 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 18 Dec 2024 22:33:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org>

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[XS] Change in coreboot[main]: mb/google/brya: Adjust EC memory map range to support indexed IO
by Jayvik Desai (Code Review) 18 Dec '24

18 Dec '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Paul Menzel. Hello Dinesh Gehlot, Eric Lai, Kapil Porwal, Nick Vaccaro, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85547?usp=email to look at the new patch set (#4). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mb/google/brya: Adjust EC memory map range to support indexed IO ...................................................................... mb/google/brya: Adjust EC memory map range to support indexed IO Adjust the EC memory map range for indexed IO access in trulo variant from 0x900 to 0x380 BUG=b:379224648 TEST= able to build nissa/trulo. Change-Id: Ide5026b35da7c00deab4464eedfca9d52d294fd6 Signed-off-by: Jayvik Desai <jayvik(a)google.com> --- M src/mainboard/google/brya/variants/baseboard/trulo/devicetree.cb 1 file changed, 5 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/85547/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/85547?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ide5026b35da7c00deab4464eedfca9d52d294fd6 Gerrit-Change-Number: 85547 Gerrit-PatchSet: 4 Gerrit-Owner: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org>

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[S] Change in coreboot[main]: soc/intel/pantherlake: Update Touch Controller UPD params
by Bora Guvendik (Code Review) 18 Dec '24

18 Dec '24

Attention is currently required from: Cliff Huang, Jérémy Compostella, Kapil Porwal, Kyoung Il Kim, Paul Menzel, Pranava Y N, Subrata Banik. Bora Guvendik has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/85199?usp=email ) Change subject: soc/intel/pantherlake: Update Touch Controller UPD params ...................................................................... Patch Set 9: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/85199?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I15fb62eaadc03b9a17e94609b97c686518150e2e Gerrit-Change-Number: 85199 Gerrit-PatchSet: 9 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Kyoung Il Kim <kyoung.il.kim(a)intel.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kyoung Il Kim <kyoung.il.kim(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Wed, 18 Dec 2024 22:10:39 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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