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Change subject: mb/trulo/var/uldrenite: Support USB_OC on the A0 port
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Patch Set 1: Code-Review+2
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Change subject: mb/google/nissa/var/rull: Add G2 touchscreen to devicetree
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Change subject: ec/google/chromeec: Add indexed IO support
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Patch Set 5:
(1 comment)
File src/ec/google/chromeec/ec_lpc.c:
https://review.coreboot.org/c/coreboot/+/85449/comment/2e098dad_c4cbf96c?us… :
PS5, Line 57: port
`port` is always `EC_GOOGLE_CHROMEEC_MEMMAP_INDEXED_IO_PORT`
so it can be dropped as a parameter. the name of the function
already suggests indexed IO.
do you expect callers to specify alternate ports?
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Change subject: lib/{fit,fit_payload}.c: Enhance support for FIT images
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Patch Set 6:
(1 comment)
File src/lib/fit_payload.c:
https://review.coreboot.org/c/coreboot/+/84796/comment/b3f31454_143c2f37?us… :
PS6, Line 131: continue;
> Shouldn't you return a hard error that makes the parent function fail in these cases? That's what we […]
Secondary images aren't necessarily crucial for the boot, and there are other reasons why we might fail (images don't fit in memory, and theoretically a need to perform relocation, ours will never need that). For example, one of ours is network-fv, which contains a network stack. If it can't be unpacked, I'd still want the boot to continue. Even if if we're missing an image that's integrated more tightly into the codebase, such as sec-fv (contains secure boot and TPM), I'd still want to try booting.
This is because when I started with coreboot development, I didn't have the luxury of a serial port, so I developed an ideology of aiming to survive through the boot even if I was hitting errors. This was the only way I'd be able to extract the log from the memory and get some debug value from the boot.
I'll add a comment in the code about this if you're fine with the theory.
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Change subject: util/crossgcc: Add libstdcxx target
......................................................................
Patch Set 14:
(1 comment)
Patchset:
PS5:
> My patch adds 39 lines, so that's not really a fair comment. […]
I completely agree that targeted development that can't be used by others shouldn't be added here. This is a simple feature that can be used by anyone.
Having Google engaged in the maintenance and development of the toolchain helps the community. Forcing Google to fork the toolchain means you'll lose the support that the community is already getting.
The coreboot toolchain is Google's firmware toolchain build standard. If we're not able to add features we need, we will have to come up with alternatives(Again, to be clear, I'm not advocating for or suggesting that we have carte blanche to add whatever we like. The changes should be within reason and benefit the community). If you don't want this change, we can abandon it.
We'll maintain a patch internally for now. There has already been push back on not using the coreboot toolchain internally, and I was doing what I could to make sure we stayed aligned with and supported the upstream community. Long term we'll likely fork internally or abandon the toolchain if maintaining a delta or being blocked becomes to burdensome.
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Change subject: util/crossgcc: Add libstdcxx target
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Patch Set 14:
(1 comment)
Patchset:
PS5:
> We can't support everything. […]
My patch adds 39 lines, so that's not really a fair comment.
nds32le was added in support of the ChromeOS EC since we have EC variants that use that architecture.
I can't speak to why the submodule for the EC was pulled in in the first place, that doesn't seem germane to this review.
It feels like a lot of misplaced baggage is being brought into the review of this change.
There's no expectation for the coreboot community to maintain anything here, it's enabling the build of another library, and it's providing functionality to a toolchain which coreboot has already chosen to support.
Having support for building another library which is inherently supported by the GCC distribution that we're already pulling doesn't seem like a bad thing. It's added in a way that doesn't affect anything else.
This patch is calling configure and make on a tarball that we're already pulling and extracting.
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Change subject: util/crossgcc: Add libstdcxx target
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Patch Set 14:
(1 comment)
Patchset:
PS5:
> It's also not doing anything unreasonable. […]
We can't support everything. Our main project is not maintaining toolchains for everyones use case or even other projects. I don't want this to be a place where everyone can throw things in just because they have a use case for it. This has the potential to explode. It's 1329 lines of bash with your patch. This is not ideal.
It's great that it worked well for Google so far, but adding expectations on coreboot to support unrelated projects seems wrong to me. I think we removed the chromeec submodule not so long ago because no one maintained or updated it in coreboot. I've never saw anyone using the nds32le toolchain, but we still include it in a full build. Why? For what?
So, I want this to be specific to what coreboot needs. If it makes things easier for you now, another compromise for me would be to land this patch now, Google works out a solution in '25 and we remove it later.
What do you think?
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Change subject: drivers/option: Add forms in cbtables
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Patch Set 30:
(1 comment)
File Documentation/drivers/cfr.md:
https://review.coreboot.org/c/coreboot/+/74121/comment/78d564fe_31d0bae5?us… :
PS29, Line 211: CFR_OPTFLAG_GRAYOUT
> This strongly sounds like adopting UEFI vfr methods. […]
to me CFR_OPTFLAG_INACTIVE also sounds better than CFR_OPTFLAG_GRAYOUT
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Change subject: drivers/option: Add forms in cbtables
......................................................................
Patch Set 30:
(6 comments)
Patchset:
PS30:
only read the first document so far and it looks reasonable to me. found a few things; would be good if those will get addressed in follow-up patches
File Documentation/drivers/cfr.md:
https://review.coreboot.org/c/coreboot/+/74121/comment/b98d6cfb_fcf8de1f?us… :
PS30, Line 1: form representation
hmm, didn't we agree in a meeting that we wanted to get rid of this uefi terminology here which is also not that descriptive of what this is?
https://review.coreboot.org/c/coreboot/+/74121/comment/bf58a844_36ac0e2c?us… :
PS30, Line 29: ore
or
https://review.coreboot.org/c/coreboot/+/74121/comment/6cb64e93_bc9e9d19?us… :
PS30, Line 58: jumping `size` bytes forward.
i like this design
https://review.coreboot.org/c/coreboot/+/74121/comment/edb149b2_34617326?us… :
PS30, Line 69: immideatly
immediately
https://review.coreboot.org/c/coreboot/+/74121/comment/99334641_55fd887e?us… :
PS30, Line 72:
the doc would be slightly easier to read if all tags were first defined and then used. right now some tags are referenced before they are introduces and at least for me it makes this slightly more difficult to read and understand
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Change subject: soc/meidatek/mt8196: Add SPM loader
......................................................................
Patch Set 6:
(1 comment)
Patchset:
PS3:
> With the refactoring in https://review.coreboot. […]
@jarried.lin@mediatek.com CB:85625 is merged, please rebase the patch.
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