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Hello Julius Werner, Zheng Bao, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: cbfs: Add COREBOOTB as backup region for A/B recovery
......................................................................
cbfs: Add COREBOOTB as backup region for A/B recovery
Change-Id: I019af6fbeca46e0e35d739a028655051fb466b48
Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com>
---
M src/lib/cbfs.c
M util/cbfstool/platform_fixups.c
2 files changed, 12 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/85629/5
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Change subject: mb/trulo/var/uldrenite: Support USB_OC on the A0 port
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Patch Set 1: Code-Review+2
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Change subject: soc/intel/pantherlake: Update Touch Controller UPD params
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Patch Set 8:
(1 comment)
File src/soc/intel/pantherlake/chip.h:
https://review.coreboot.org/c/coreboot/+/85199/comment/1a56df9f_f4b5110f?us… :
PS8, Line 520: Hid
Spi?
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Change subject: vc/intel/fsp/mtl: Update MTL fsp header files from 3471_91 to 4122_21
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Patch Set 8:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/84656/comment/d54b1215_90d425f0?us… :
PS8, Line 16: PchHdaSubSystemIds
@alok.agarwal@intel.com Can we add this UPD to X64 headers as well?
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Change subject: soc/intel/mtl: Set HDA subsystem ID during FSP-M
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Patch Set 4:
(1 comment)
Patchset:
PS4:
> Created b/345650429 to track this request.
For X86-32 FSP: https://review.coreboot.org/c/coreboot/+/84656
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Change subject: soc/amd/glinda/cpu: Update cache info
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> I am a bit confused by this set of patches. […]
The current implementation checks cache in BSP. which is inaccurate in for Glinda SoC.
For example, in my Glinda SoC based board. LLC is 16 + 8 shared between 8 + 12 threads.
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