coreboot-gerrit December 2024

coreboot-gerrit@coreboot.org

1 participants
3018 discussions

[S] Change in coreboot[main]: soc/intel/pantherlake: Bind SoC config VR settings to respective UPD
by Subrata Banik (Code Review) 19 Dec '24

19 Dec '24

Attention is currently required from: Jérémy Compostella, Paul Menzel. Subrata Banik has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/85131?usp=email ) Change subject: soc/intel/pantherlake: Bind SoC config VR settings to respective UPD ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85131?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie72e4725cb97b4af7843a43eeaedd687d28b6752 Gerrit-Change-Number: 85131 Gerrit-PatchSet: 6 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Thu, 19 Dec 2024 14:17:14 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

1 0

[M] Change in coreboot[main]: soc/intel/meteorlake: Use ASPM helpers from Alder Lake
by Subrata Banik (Code Review) 19 Dec '24

19 Dec '24

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Sean Rhodes, Tarun. Subrata Banik has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/83678?usp=email ) Change subject: soc/intel/meteorlake: Use ASPM helpers from Alder Lake ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83678?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia5cc11188b245a93c303117589bd9d3c18c2877e Gerrit-Change-Number: 83678 Gerrit-PatchSet: 5 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Thu, 19 Dec 2024 14:16:00 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

1 0

[L] Change in coreboot[main]: soc/mediatek/mt8196: Add GPUEB support
by Yidi Lin (Code Review) 19 Dec '24

19 Dec '24

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yu-Ping Wu. Yidi Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85654?usp=email ) Change subject: soc/mediatek/mt8196: Add GPUEB support ...................................................................... Patch Set 2: (1 comment) File src/soc/mediatek/mt8196/gpueb.c: https://review.coreboot.org/c/coreboot/+/85654/comment/266bd7e1_f8856bae?us… : PS2, Line 305: write32p(GPUEB_INFO, (uintptr_t)mcu->load_buffer); : write32p(GPUEB_ABNORMAL_BOOT, 0); : write32p(GPUEB_WARM_BOOT, 0); : write32p(GPUMPU_RSV_ADDR, (uintptr_t)_resv_mem_gpueb >> PAGE_SHIFT); Can you explain this part ? I don't quite understand why it writes `mcu->load_buffer` to `GPUEB_INFO`. `mcu->load_buffer` is pointing to a shared DMA buffer. Will GPUEB HW copy the content of `mcu->load_buffer` to somewhere ? -- To view, visit https://review.coreboot.org/c/coreboot/+/85654?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0f10dfc753f73df97ea08a4c23e97de416832be2 Gerrit-Change-Number: 85654 Gerrit-PatchSet: 2 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Andy Hsu <andy.hsu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Thu, 19 Dec 2024 13:23:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

1 0

[XL] Change in coreboot[main]: soc/meidatek/mt8196: Add SPM loader
by Yu-Ping Wu (Code Review) 19 Dec '24

19 Dec '24

Attention is currently required from: Ccong Chen, Hung-Te Lin, Jarried Lin, Yidi Lin. Yu-Ping Wu has posted comments on this change by Ccong Chen. ( https://review.coreboot.org/c/coreboot/+/85599?usp=email ) Change subject: soc/meidatek/mt8196: Add SPM loader ...................................................................... Patch Set 8: (3 comments) File src/soc/mediatek/common/spm.c: https://review.coreboot.org/c/coreboot/+/85599/comment/da50a50c_3444638e?us… : PS1, Line 59: #ifndef CONFIG_MEDIATEK_SPM_V2 > No done Done https://review.coreboot.org/c/coreboot/+/85599/comment/49adc530_c59ba8ff?us… : PS1, Line 101: CONFIG_MEDIATEK_SPM_V2 > not done Done File src/soc/mediatek/common/spm.c: https://review.coreboot.org/c/coreboot/+/85599/comment/029b1f1d_a05fd73f?us… : PS8, Line 30: ptr = (uintptr_t)pcm->buf + SPM_SYSTEM_BASE_OFFSET; Define SPM_SYSTEM_BASE_OFFSET as 0 in the header file. There's no need to change this. Remove the newly added Kconfig. It's not needed. -- To view, visit https://review.coreboot.org/c/coreboot/+/85599?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie09346f46cb734c74776b760485e7f35d4357e5e Gerrit-Change-Number: 85599 Gerrit-PatchSet: 8 Gerrit-Owner: Ccong Chen <ot_ccong.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-CC: Wenzhen Yu <wenzhen.yu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Ccong Chen <ot_ccong.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Thu, 19 Dec 2024 13:21:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Ccong Chen <ot_ccong.chen(a)mediatek.corp-partner.google.com> Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com>

1 0

[XL] Change in coreboot[main]: soc/meidatek/mt8196: Add SPM loader
by Ccong Chen (Code Review) 19 Dec '24

19 Dec '24

Attention is currently required from: Ccong Chen, Hung-Te Lin, Jarried Lin, Yu-Ping Wu. Hello Hung-Te Lin, Wenzhen Yu, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85599?usp=email to look at the new patch set (#8). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: soc/meidatek/mt8196: Add SPM loader ...................................................................... soc/meidatek/mt8196: Add SPM loader This patch adds support for loading SPM firmware from CBFS to SPM SRAM and fix the SPM register definitions. SPM needs its own firmware to enable SPM suspend/resume function which turns off several resources such as DRAM/mainpll/26M clk when linux system suspend. coreboot log: CBFS: Found 'spm_firmware.pm' @0xadf00 size 0x5a60 in mcache @0xfffdd3c mtk_init_mcu: Loaded (and reset) spm_firmware.pm in 3 msecs (30080 byt) TEST=build pass BUG=348147674 Change-Id: Ie09346f46cb734c74776b760485e7f35d4357e5e Signed-off-by: Wenzhen Yu <wenzhen.yu(a)mediatek.corp-partner.google.com> --- M src/soc/mediatek/common/Kconfig M src/soc/mediatek/common/spm.c M src/soc/mediatek/mt8196/Kconfig M src/soc/mediatek/mt8196/Makefile.mk M src/soc/mediatek/mt8196/include/soc/addressmap.h M src/soc/mediatek/mt8196/include/soc/pll.h M src/soc/mediatek/mt8196/include/soc/spm.h A src/soc/mediatek/mt8196/spm.c 8 files changed, 1,367 insertions(+), 169 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/85599/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/85599?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie09346f46cb734c74776b760485e7f35d4357e5e Gerrit-Change-Number: 85599 Gerrit-PatchSet: 8 Gerrit-Owner: Ccong Chen <ot_ccong.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-CC: Wenzhen Yu <wenzhen.yu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Ccong Chen <ot_ccong.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com>

1 0

[M] Change in coreboot[main]: mb/google/skywalker: Add MediaTek MT8189 reference board
by Yidi Lin (Code Review) 19 Dec '24

19 Dec '24

Yidi Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85617?usp=email ) ( 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/google/skywalker: Add MediaTek MT8189 reference board ...................................................................... mb/google/skywalker: Add MediaTek MT8189 reference board Add mainboard folder and drivers for new reference board 'Skywalker'. BUG=b:379008996 BRANCH=none TEST=saw the coreboot uart log to bootblock Change-Id: I690508fea91c790f202f234f89be8f3cf4d09546 Signed-off-by: Vince Liu <vince-wl.liu(a)mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85617 Reviewed-by: Yidi Lin <yidilin(a)google.com> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- A src/mainboard/google/skywalker/Kconfig A src/mainboard/google/skywalker/Kconfig.name A src/mainboard/google/skywalker/Makefile.mk A src/mainboard/google/skywalker/board_info.txt A src/mainboard/google/skywalker/bootblock.c A src/mainboard/google/skywalker/chromeos.c A src/mainboard/google/skywalker/chromeos.fmd A src/mainboard/google/skywalker/devicetree.cb A src/mainboard/google/skywalker/mainboard.c A src/mainboard/google/skywalker/memlayout.ld A src/mainboard/google/skywalker/reset.c A src/mainboard/google/skywalker/romstage.c 12 files changed, 157 insertions(+), 0 deletions(-) Approvals: Yu-Ping Wu: Looks good to me, approved Yidi Lin: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/google/skywalker/Kconfig b/src/mainboard/google/skywalker/Kconfig new file mode 100644 index 0000000..a3bed90 --- /dev/null +++ b/src/mainboard/google/skywalker/Kconfig @@ -0,0 +1,30 @@ +## SPDX-License-Identifier: GPL-2.0-only OR MIT + +# Umbrella option to be selected by variant boards. +config BOARD_GOOGLE_SKYWALKER_COMMON + def_bool BOARD_GOOGLE_SKYWALKER + +if BOARD_GOOGLE_SKYWALKER_COMMON + +config VBOOT + select VBOOT_VBNV_FLASH + select VBOOT_NO_BOARD_SUPPORT + select VBOOT_MOCK_SECDATA + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select SOC_MEDIATEK_MT8189 + select BOARD_ROMSIZE_KB_8192 + select MAINBOARD_HAS_CHROMEOS + select COMMON_CBFS_SPI_WRAPPER + select SPI_FLASH + select SPI_FLASH_INCLUDE_ALL_DRIVERS + +config MAINBOARD_DIR + string + default "google/skywalker" + +config MAINBOARD_PART_NUMBER + string + default "Skywalker" if BOARD_GOOGLE_SKYWALKER +endif diff --git a/src/mainboard/google/skywalker/Kconfig.name b/src/mainboard/google/skywalker/Kconfig.name new file mode 100644 index 0000000..0fc672d --- /dev/null +++ b/src/mainboard/google/skywalker/Kconfig.name @@ -0,0 +1,6 @@ +## SPDX-License-Identifier: GPL-2.0-only OR MIT + +comment "Skywalker" + +config BOARD_GOOGLE_SKYWALKER + bool "-> Skywalker" diff --git a/src/mainboard/google/skywalker/Makefile.mk b/src/mainboard/google/skywalker/Makefile.mk new file mode 100644 index 0000000..c2ff8f6 --- /dev/null +++ b/src/mainboard/google/skywalker/Makefile.mk @@ -0,0 +1,11 @@ +## SPDX-License-Identifier: GPL-2.0-only OR MIT + +all-y += memlayout.ld +all-y += chromeos.c +all-y += reset.c + +bootblock-y += bootblock.c + +romstage-y += romstage.c + +ramstage-y += mainboard.c diff --git a/src/mainboard/google/skywalker/board_info.txt b/src/mainboard/google/skywalker/board_info.txt new file mode 100644 index 0000000..fc4eee5 --- /dev/null +++ b/src/mainboard/google/skywalker/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Google +Board name: Skywalker MediaTek MT8189 reference board +Category: eval +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/google/skywalker/bootblock.c b/src/mainboard/google/skywalker/bootblock.c new file mode 100644 index 0000000..af9934e --- /dev/null +++ b/src/mainboard/google/skywalker/bootblock.c @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ + +#include <bootblock_common.h> + +void bootblock_mainboard_init(void) +{ + /* TODO: add mainboard init for bootblock */ +} diff --git a/src/mainboard/google/skywalker/chromeos.c b/src/mainboard/google/skywalker/chromeos.c new file mode 100644 index 0000000..0e0f62d --- /dev/null +++ b/src/mainboard/google/skywalker/chromeos.c @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ + +#include <boot/coreboot_tables.h> + +void fill_lb_gpios(struct lb_gpios *gpios) +{ + /* TODO: add ChromeOS specific gpios */ +} diff --git a/src/mainboard/google/skywalker/chromeos.fmd b/src/mainboard/google/skywalker/chromeos.fmd new file mode 100644 index 0000000..5b2234d --- /dev/null +++ b/src/mainboard/google/skywalker/chromeos.fmd @@ -0,0 +1,46 @@ +# Firmware Layout Description for ChromeOS. +# +# The size and address of every section must be aligned to at least 4K, except: +# RO_FRID, RW_FWID*, GBB, or any unused / padding / CBFS type sections. +# +# 'FMAP' may be found by binary search so its starting address should be better +# aligned to larger values. +# +# For sections to be preserved on update, add (PRESERVE) to individual sections +# instead of a group section; otherwise the preserved data may be wrong if you +# resize or reorder sections inside a group. + +FLASH@0x0 8M { + WP_RO@0x0 4M { + RO_SECTION { + BOOTBLOCK 128K + FMAP 4K + COREBOOT(CBFS) + GBB 0x2f00 + RO_FRID 0x100 + } + RO_GSCVD 8K + RO_VPD(PRESERVE) 32K # At least 16K. + } + RW_SECTION_A 1500K { + VBLOCK_A 8K + FW_MAIN_A(CBFS) + RW_FWID_A 0x100 + } + RW_MISC 36K { + RW_VPD(PRESERVE) 16K # At least 8K. + RW_NVRAM(PRESERVE) 8K + RW_MRC_CACHE(PRESERVE) 8K + RW_ELOG(PRESERVE) 4K # ELOG driver hard-coded size in 4K. + } + RW_SECTION_B 1500K { + VBLOCK_B 8K + FW_MAIN_B(CBFS) + RW_FWID_B 0x100 + } + RW_SHARED 36K { # Will be force updated on recovery. + SHARED_DATA 4K # 4K or less for netboot params. + RW_UNUSED + } + RW_LEGACY(CBFS) 1M # Minimal 1M. +} diff --git a/src/mainboard/google/skywalker/devicetree.cb b/src/mainboard/google/skywalker/devicetree.cb new file mode 100644 index 0000000..c76b4e6 --- /dev/null +++ b/src/mainboard/google/skywalker/devicetree.cb @@ -0,0 +1,5 @@ +## SPDX-License-Identifier: GPL-2.0-only OR MIT + +chip soc/mediatek/mt8189 + device cpu_cluster 0 on end +end diff --git a/src/mainboard/google/skywalker/mainboard.c b/src/mainboard/google/skywalker/mainboard.c new file mode 100644 index 0000000..9ab352c --- /dev/null +++ b/src/mainboard/google/skywalker/mainboard.c @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ + +#include <device/device.h> + +static void mainboard_init(struct device *dev) +{ + /* TODO: add mainboard init */ +} + +static void mainboard_enable(struct device *dev) +{ + dev->ops->init = &mainboard_init; +} + +struct chip_operations mainboard_ops = { + .name = CONFIG_MAINBOARD_PART_NUMBER, + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/google/skywalker/memlayout.ld b/src/mainboard/google/skywalker/memlayout.ld new file mode 100644 index 0000000..17d54f2 --- /dev/null +++ b/src/mainboard/google/skywalker/memlayout.ld @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ + +#include <soc/memlayout.ld> diff --git a/src/mainboard/google/skywalker/reset.c b/src/mainboard/google/skywalker/reset.c new file mode 100644 index 0000000..1a4b156 --- /dev/null +++ b/src/mainboard/google/skywalker/reset.c @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ + +#include <reset.h> + +void do_board_reset(void) +{ + /* TODO: add reset function when gpio is ready */ +} diff --git a/src/mainboard/google/skywalker/romstage.c b/src/mainboard/google/skywalker/romstage.c new file mode 100644 index 0000000..7758dfa --- /dev/null +++ b/src/mainboard/google/skywalker/romstage.c @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ + +#include <arch/stages.h> + +void platform_romstage_main(void) +{ + /* TODO: add romstage main function */ +} -- To view, visit https://review.coreboot.org/c/coreboot/+/85617?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I690508fea91c790f202f234f89be8f3cf4d09546 Gerrit-Change-Number: 85617 Gerrit-PatchSet: 5 Gerrit-Owner: Vince Liu <vince-wl.liu(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

[L] Change in coreboot[main]: soc/mediatek/mt8189: Add a stub implementation of MT8189 SoC
by Yidi Lin (Code Review) 19 Dec '24

19 Dec '24

Yidi Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85616?usp=email ) ( 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/mediatek/mt8189: Add a stub implementation of MT8189 SoC ...................................................................... soc/mediatek/mt8189: Add a stub implementation of MT8189 SoC Add new folder and basic drivers for Mediatek SoC 'MT8189'. Also enable UART and ARM arch timer. This commit includes the necessary initialization files for MT8189, which cannot be shared with other existing SoCs. The modules included are: - Memory layout: MT8189 has only 64KB of SRAM, differing in space allocation compared to other SoCs. - PLL: Different SoCs have different PLL designs. In this commit, we provide the most basic settings, with more configurations to be added in future commits. - Timer: MT8189 uses timer v2, unlike other SoCs which use timer v1. - SPI: The SPI driver for different SoCs varies depending on the GPIO/ PIN MUX used. In this commit, we provide the most basic settings, with more configurations to be added in future commits. - EMI: MT8189 uses common EMI code along with MT8189-specific 'dram_parameter.h'. This commit provides an EMI stub to ensure coreboot builds successfully. Future DRAM-related commits will utilize the common EMI code. BUG=b:379008996 BRANCH=none TEST=saw the coreboot uart log to bootblock Change-Id: I5d83c4c7fba49e455fac0b58f019ad225f83c197 Signed-off-by: Vince Liu <vince-wl.liu(a)mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85616 Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Reviewed-by: Yidi Lin <yidilin(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- A src/soc/mediatek/mt8189/Kconfig A src/soc/mediatek/mt8189/Makefile.mk A src/soc/mediatek/mt8189/bootblock.c A src/soc/mediatek/mt8189/emi.c A src/soc/mediatek/mt8189/include/soc/addressmap.h A src/soc/mediatek/mt8189/include/soc/emi.h A src/soc/mediatek/mt8189/include/soc/memlayout.ld A src/soc/mediatek/mt8189/include/soc/pll.h A src/soc/mediatek/mt8189/include/soc/spi.h A src/soc/mediatek/mt8189/include/soc/timer.h A src/soc/mediatek/mt8189/soc.c A src/soc/mediatek/mt8189/spi.c A src/soc/mediatek/mt8189/timer.c 13 files changed, 318 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Yidi Lin: Looks good to me, approved Yu-Ping Wu: Looks good to me, approved diff --git a/src/soc/mediatek/mt8189/Kconfig b/src/soc/mediatek/mt8189/Kconfig new file mode 100644 index 0000000..d0395c2 --- /dev/null +++ b/src/soc/mediatek/mt8189/Kconfig @@ -0,0 +1,22 @@ +## SPDX-License-Identifier: GPL-2.0-only OR MIT + +config SOC_MEDIATEK_MT8189 + bool + default n + select ARCH_BOOTBLOCK_ARMV8_64 + select ARCH_VERSTAGE_ARMV8_64 + select ARCH_ROMSTAGE_ARMV8_64 + select ARCH_RAMSTAGE_ARMV8_64 + select HAVE_UART_SPECIAL + select SOC_MEDIATEK_COMMON + select ARM64_USE_ARCH_TIMER + +if SOC_MEDIATEK_MT8189 + +config VBOOT + select VBOOT_MUST_REQUEST_DISPLAY + select VBOOT_STARTS_IN_BOOTBLOCK + select VBOOT_SEPARATE_VERSTAGE + select VBOOT_RETURN_FROM_VERSTAGE + +endif diff --git a/src/soc/mediatek/mt8189/Makefile.mk b/src/soc/mediatek/mt8189/Makefile.mk new file mode 100644 index 0000000..9b09628 --- /dev/null +++ b/src/soc/mediatek/mt8189/Makefile.mk @@ -0,0 +1,24 @@ +## SPDX-License-Identifier: GPL-2.0-only OR MIT + +ifeq ($(CONFIG_SOC_MEDIATEK_MT8189),y) + +all-$(CONFIG_SPI_FLASH) += spi.c +all-y += timer.c +all-y += ../common/uart.c + +bootblock-y += bootblock.c +bootblock-y += ../common/mmu_operations.c + +romstage-y += ../common/cbmem.c +romstage-y += emi.c + +ramstage-y += emi.c +ramstage-y += soc.c + +CPPFLAGS_common += -Isrc/soc/mediatek/mt8189/include +CPPFLAGS_common += -Isrc/soc/mediatek/common/include + +$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin + ./util/mtkheader/gen-bl-img.py mt8189 sf $< $@ + +endif diff --git a/src/soc/mediatek/mt8189/bootblock.c b/src/soc/mediatek/mt8189/bootblock.c new file mode 100644 index 0000000..89cd22d --- /dev/null +++ b/src/soc/mediatek/mt8189/bootblock.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ + +#include <bootblock_common.h> +#include <soc/mmu_operations.h> + +void bootblock_soc_init(void) +{ + mtk_mmu_init(); +} diff --git a/src/soc/mediatek/mt8189/emi.c b/src/soc/mediatek/mt8189/emi.c new file mode 100644 index 0000000..8b933e8 --- /dev/null +++ b/src/soc/mediatek/mt8189/emi.c @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ + +#include <soc/emi.h> + +size_t sdram_size(void) +{ + return (size_t)4 * GiB; +} diff --git a/src/soc/mediatek/mt8189/include/soc/addressmap.h b/src/soc/mediatek/mt8189/include/soc/addressmap.h new file mode 100644 index 0000000..c0c78b1 --- /dev/null +++ b/src/soc/mediatek/mt8189/include/soc/addressmap.h @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ + +#ifndef __SOC_MEDIATEK_MT8189_INCLUDE_SOC_ADDRESSMAP_H__ +#define __SOC_MEDIATEK_MT8189_INCLUDE_SOC_ADDRESSMAP_H__ + +enum { + IO_PHYS = 0x10000000, +}; + +enum { + CKSYS_BASE = IO_PHYS + 0x00000000, + INFRACFG_AO_BASE = IO_PHYS + 0x00001000, + GPIO_BASE = IO_PHYS + 0x00005000, + APMIXED_BASE = IO_PHYS + 0x0000C000, + DEVAPC_INFRA_SECU_AO_BASE = IO_PHYS + 0x0001C000, + BCRM_INFRA_AO_BASE = IO_PHYS + 0x00022000, + DEVAPC_INFRA_AO_BASE = IO_PHYS + 0x00030000, + DEVAPC_INFRA_AO1_BASE = IO_PHYS + 0x00034000, + EMI0_BASE = IO_PHYS + 0x00219000, + EMI0_MPU_BASE = IO_PHYS + 0x00226000, + DRAMC_CHA_AO_BASE = IO_PHYS + 0x00230000, + THERM_CTRL_BASE = IO_PHYS + 0x00315000, + DPM_PM_SRAM_BASE = IO_PHYS + 0x00900000, + DPM_DM_SRAM_BASE = IO_PHYS + 0x00920000, + DPM_CFG_BASE = IO_PHYS + 0x00940000, + DPM_PM_SRAM_BASE2 = IO_PHYS + 0x00A00000, + DPM_DM_SRAM_BASE2 = IO_PHYS + 0x00A20000, + DPM_CFG_BASE2 = IO_PHYS + 0x00A40000, + UART0_BASE = IO_PHYS + 0x01001000, + SFLASH_REG_BASE = IO_PHYS + 0x01018000, + PERICFG_AO_BASE = IO_PHYS + 0x01036000, + DEVAPC_PERI_PAR_AO_BASE = IO_PHYS + 0x0103C000, + SSUSB_IPPC_BASE = IO_PHYS + 0x01203E00, + UFSHCI_BASE = IO_PHYS + 0x012B0000, + MIPITX0_BASE = IO_PHYS + 0x01B40000, + IOCFG_LM_BASE = IO_PHYS + 0x01B50000, + EDP_BASE = IO_PHYS + 0x01B70000, + IOCFG_RB0_BASE = IO_PHYS + 0x01C50000, + IOCFG_RB1_BASE = IO_PHYS + 0x01C60000, + IOCFG_BM0_BASE = IO_PHYS + 0x01D20000, + IOCFG_BM1_BASE = IO_PHYS + 0x01D30000, + IOCFG_BM2_BASE = IO_PHYS + 0x01D40000, + IOCFG_LT0_BASE = IO_PHYS + 0x01E20000, + IOCFG_LT1_BASE = IO_PHYS + 0x01E30000, + SSUSB_SIF_BASE = IO_PHYS + 0x01E80300, + IOCFG_RT_BASE = IO_PHYS + 0x01F20000, + DSI0_BASE = IO_PHYS + 0x04016000, + DISP_DVO0 = IO_PHYS + 0x04019000, + RGU_BASE = IO_PHYS + 0x0C00A000, + SPMI_MST_BASE = IO_PHYS + 0x0C013000, + DEVAPC_VLP_AO_BASE = IO_PHYS + 0x0C018000, + SPMI_MST_P_BASE = IO_PHYS + 0x0CC00000, + PMIF_SPMI_BASE = IO_PHYS + 0x0CC04000, + PMIF_SPMI_P_BASE = IO_PHYS + 0x0CC06000, + SYSTIMER_BASE = IO_PHYS + 0x0CC10000, + DEVAPC_MM_AO_BASE = IO_PHYS + 0x0E820000, +}; + +#endif /* __SOC_MEDIATEK_MT8189_INCLUDE_SOC_ADDRESSMAP_H__ */ diff --git a/src/soc/mediatek/mt8189/include/soc/emi.h b/src/soc/mediatek/mt8189/include/soc/emi.h new file mode 100644 index 0000000..9f66a7f --- /dev/null +++ b/src/soc/mediatek/mt8189/include/soc/emi.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ + +#ifndef __SOC_MEDIATEK_MT8189_INCLUDE_SOC_EMI_H__ +#define __SOC_MEDIATEK_MT8189_INCLUDE_SOC_EMI_H__ + +#include <stddef.h> + +size_t sdram_size(void); + +#endif /* __SOC_MEDIATEK_MT8189_INCLUDE_SOC_EMI_H__ */ diff --git a/src/soc/mediatek/mt8189/include/soc/memlayout.ld b/src/soc/mediatek/mt8189/include/soc/memlayout.ld new file mode 100644 index 0000000..b3ca9b7 --- /dev/null +++ b/src/soc/mediatek/mt8189/include/soc/memlayout.ld @@ -0,0 +1,70 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ + +#include <soc/memlayout.h> + +SECTIONS +{ + /* MT8189 has 64KB SRAM. */ + SRAM_START(0x00100000) + WATCHDOG_TOMBSTONE(0x00100030, 4) + + /* + * MCUPM uses the following regions to exchange data with kernel. + * The addresses are hardcoded in MCUPM image. + */ + REGION(dvfs1_reserved, 0x00100a00, 3K, 4) + REGION(cpucooler_reserved, 0x00101600, 700, 4) + REGION(mcdi_reserved, 0x00101d00, 2K, 4) + REGION(thermal_reserved, 0x00102500, 1K, 4) + REGION(dvfs2_reserved, 0x00108D68, 5K, 4) + REGION(ptp1_reserved, 0x0010A168, 6808, 4) + + /* + * Since MCUPM uses most of the space, most regions are put in SRAM_L2C below. + */ + + SRAM_END(0x00110000) + + /* + * The L3 (can be used as SRAM_L2C) currently using is 1MB. + * The BootROM has configured all cache as SRAM so we can't use them + * unless if we disable L2C and reconfigure. + */ + SRAM_L2C_START(0x02000000) + #if ENV_ROMSTAGE + /* + * The needed size can be obtained by: + * aarch64-cros-linux-gnu-objdump -x dram.elf | grep memsz + * To move the address, dram.elf also needs to be modified accordingly. + */ + DRAM_INIT_CODE(0x02000000, 500K) + #else + /* + * The bootROM needs 4K starting from SRAM_L2C_START so the bootblock starting address + * is fixed at SRAM_L2C_START + 4K, and the 4K can be reused after bootblock is started. + * To move the address, gen-bl-img.py also needs to be modified accordingly. + */ + BOOTBLOCK(0x02001000, 60K) + #endif + + OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0x0207D000, 272K) + PRERAM_CBFS_CACHE(0x020C1000, 48K) + + CBFS_MCACHE(0x020CD000, 16K) + VBOOT2_WORK(0x020D1000, 12K) + FMAP_CACHE(0x020D4000, 2K) + TPM_LOG(0x020D4800, 2K) + TTB(0x020D5000, 28K) + DMA_COHERENT(0x020DC000, 4K) + STACK(0x020DD000, 15K) + TIMESTAMP(0x020E0C00, 1K) + PRERAM_CBMEM_CONSOLE(0x020E1000, 124K) + SRAM_L2C_END(0x02100000) + + DRAM_START(0x40000000) + DRAM_DMA(0x40000000, 1M) + POSTRAM_CBFS_CACHE(0x40100000, 2M) + RAMSTAGE(0x40300000, 2M) + + BL31(0x54600000, 0x60000) +} diff --git a/src/soc/mediatek/mt8189/include/soc/pll.h b/src/soc/mediatek/mt8189/include/soc/pll.h new file mode 100644 index 0000000..8d6de12 --- /dev/null +++ b/src/soc/mediatek/mt8189/include/soc/pll.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ + +/* + * This file is created based on MT8189 Functional Specification + * Chapter number: 8.1 + */ + +#ifndef __SOC_MEDIATEK_MT8189_INCLUDE_SOC_PLL_H__ +#define __SOC_MEDIATEK_MT8189_INCLUDE_SOC_PLL_H__ + +#include <soc/pll_common.h> + +/* top_div rate */ +enum { + CLK26M_HZ = 26 * MHz, +}; + +/* top_mux rate */ +enum { + UART_HZ = CLK26M_HZ, +}; + +#endif /* __SOC_MEDIATEK_MT8189_INCLUDE_SOC_PLL_H__ */ diff --git a/src/soc/mediatek/mt8189/include/soc/spi.h b/src/soc/mediatek/mt8189/include/soc/spi.h new file mode 100644 index 0000000..8c66e4a --- /dev/null +++ b/src/soc/mediatek/mt8189/include/soc/spi.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ + +/* + * This file is created based on MT8189 Functional Specification + * Chapter number: 9.17 + */ + +#ifndef __SOC_MEDIATEK_MT8189_INCLUDE_SOC_SPI_H__ +#define __SOC_MEDIATEK_MT8189_INCLUDE_SOC_SPI_H__ + +#include <spi-generic.h> + +#endif /* __SOC_MEDIATEK_MT8189_INCLUDE_SOC_SPI_H__ */ diff --git a/src/soc/mediatek/mt8189/include/soc/timer.h b/src/soc/mediatek/mt8189/include/soc/timer.h new file mode 100644 index 0000000..60af8aa --- /dev/null +++ b/src/soc/mediatek/mt8189/include/soc/timer.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ + +/* + * This file is created based on MT8189 Functional Specification + * Chapter number: 9.16 + */ + +#ifndef __SOC_MEDIATEK_MT8189_INCLUDE_SOC_TIMER_H__ +#define __SOC_MEDIATEK_MT8189_INCLUDE_SOC_TIMER_H__ + +#include <soc/timer_v2.h> + +#endif /* __SOC_MEDIATEK_MT8189_INCLUDE_SOC_TIMER_H__ */ diff --git a/src/soc/mediatek/mt8189/soc.c b/src/soc/mediatek/mt8189/soc.c new file mode 100644 index 0000000..e4dfc23 --- /dev/null +++ b/src/soc/mediatek/mt8189/soc.c @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ + +#include <device/device.h> +#include <soc/emi.h> +#include <symbols.h> + +static void soc_read_resources(struct device *dev) +{ + ram_range(dev, 0, (uintptr_t)_dram, sdram_size()); +} + +static void soc_init(struct device *dev) +{ +} + +static struct device_operations soc_ops = { + .read_resources = soc_read_resources, + .set_resources = noop_set_resources, + .init = soc_init, +}; + +static void enable_soc_dev(struct device *dev) +{ + dev->ops = &soc_ops; +} + +struct chip_operations soc_mediatek_mt8189_ops = { + .name = "SOC Mediatek MT8189", + .enable_dev = enable_soc_dev, +}; diff --git a/src/soc/mediatek/mt8189/spi.c b/src/soc/mediatek/mt8189/spi.c new file mode 100644 index 0000000..da40fc5 --- /dev/null +++ b/src/soc/mediatek/mt8189/spi.c @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ + +/* + * This file is created based on MT8189 Functional Specification + * Chapter number: 9.17 + */ + +#include <device/mmio.h> +#include <soc/addressmap.h> +#include <soc/spi.h> + +static const struct spi_ctrlr spi_flash_ctrlr = { + .max_xfer_size = 65535, +}; + +const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { + { + .ctrlr = &spi_flash_ctrlr, + }, +}; + +const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map); diff --git a/src/soc/mediatek/mt8189/timer.c b/src/soc/mediatek/mt8189/timer.c new file mode 100644 index 0000000..2f299ea --- /dev/null +++ b/src/soc/mediatek/mt8189/timer.c @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on MT8189 Functional Specification + * Chapter number: 9.16 + */ + +#include <arch/lib_helpers.h> +#include <commonlib/helpers.h> +#include <delay.h> + +void init_timer(void) +{ + raw_write_cntfrq_el0(13 * MHz); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/85616?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5d83c4c7fba49e455fac0b58f019ad225f83c197 Gerrit-Change-Number: 85616 Gerrit-PatchSet: 5 Gerrit-Owner: Vince Liu <vince-wl.liu(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

[XL] Change in coreboot[main]: soc/meidatek/mt8196: Add SPM loader
by Ccong Chen (Code Review) 19 Dec '24

19 Dec '24

Attention is currently required from: Ccong Chen, Hung-Te Lin, Jarried Lin, Wenzhen Yu, Yu-Ping Wu. Hello Hung-Te Lin, Wenzhen Yu, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85599?usp=email to look at the new patch set (#7). The following approvals got outdated and were removed: Code-Review+1 by Yu-Ping Wu, Verified-1 by build bot (Jenkins) Change subject: soc/meidatek/mt8196: Add SPM loader ...................................................................... soc/meidatek/mt8196: Add SPM loader This patch adds support for loading SPM firmware from CBFS to SPM SRAM and fix the SPM register definitions. SPM needs its own firmware to enable SPM suspend/resume function which turns off several resources such as DRAM/mainpll/26M clk when linux system suspend. coreboot log: CBFS: Found 'spm_firmware.pm' @0xadf00 size 0x5a60 in mcache @0xfffdd3c mtk_init_mcu: Loaded (and reset) spm_firmware.pm in 3 msecs (30080 byt) TEST=build pass BUG=348147674 Change-Id: Ie09346f46cb734c74776b760485e7f35d4357e5e Signed-off-by: Wenzhen Yu <wenzhen.yu(a)mediatek.corp-partner.google.com> --- M src/soc/mediatek/common/Kconfig M src/soc/mediatek/common/include/soc/spm_common.h M src/soc/mediatek/common/spm.c M src/soc/mediatek/mt8196/Kconfig M src/soc/mediatek/mt8196/Makefile.mk M src/soc/mediatek/mt8196/include/soc/addressmap.h M src/soc/mediatek/mt8196/include/soc/pll.h M src/soc/mediatek/mt8196/include/soc/spm.h A src/soc/mediatek/mt8196/spm.c 9 files changed, 1,387 insertions(+), 173 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/85599/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/85599?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie09346f46cb734c74776b760485e7f35d4357e5e Gerrit-Change-Number: 85599 Gerrit-PatchSet: 7 Gerrit-Owner: Ccong Chen <ot_ccong.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Wenzhen Yu <wenzhen.yu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Wenzhen Yu <wenzhen.yu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Ccong Chen <ot_ccong.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com>

1 0

[S] Change in coreboot[main]: mb/google/nissa/var/telith: Modify PLD for typeC and typeA
by Subrata Banik (Code Review) 19 Dec '24

19 Dec '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Ginger Zhang, Jayvik Desai, Kun Liu, Nick Vaccaro. Subrata Banik has posted comments on this change by Kun Liu. ( https://review.coreboot.org/c/coreboot/+/85618?usp=email ) Change subject: mb/google/nissa/var/telith: Modify PLD for typeC and typeA ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85618?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifc5cd7c8e61b20632d2dcf4b7b2d506c42162063 Gerrit-Change-Number: 85618 Gerrit-PatchSet: 2 Gerrit-Owner: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Ginger Zhang <zhangqingchun(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Ginger Zhang <zhangqingchun(a)huaqin.corp-partner.google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Thu, 19 Dec 2024 11:26:54 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

1 0

[M] Change in coreboot[main]: soc/mediatek: Add support for MediaTek firmware support package
by Yidi Lin (Code Review) 19 Dec '24

19 Dec '24

Attention is currently required from: Hung-Te Lin, Yidi Lin, Yu-Ping Wu. Hello Hung-Te Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85665?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: soc/mediatek: Add support for MediaTek firmware support package ...................................................................... soc/mediatek: Add support for MediaTek firmware support package Starting from MT8196, MediaTek platform introudces a new blob named MediaTek firmeware support package (mtk-fsp). The features of mtk-fsp includes but not limit to, - Security settings, e.g: Device Access Proctection Control, Security Memory Protection Unit. - Initialization for advanced CPU frequency control. This patch implements APIs for 1. Exchanging data between coreboot and mtk-fsp. 2. Loading and running the mtk-fsp blob at a specific bootstage. BUG=b:373797027 TEST=emerge-rauru coreboot; Run mock blob and return from mock blob. Change-Id: Idef3518f9763fe5f74adb459c137db164563e483 Signed-off-by: Yidi Lin <yidilin(a)chromium.org> --- A src/soc/mediatek/common/include/soc/mtk_fsp.h A src/soc/mediatek/common/include/soc/mtk_fsp_common.h A src/soc/mediatek/common/mtk_fsp.c M src/soc/mediatek/mt8196/Makefile.mk 4 files changed, 180 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/85665/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85665?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idef3518f9763fe5f74adb459c137db164563e483 Gerrit-Change-Number: 85665 Gerrit-PatchSet: 2 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com>

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit December 2024