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[M] Change in coreboot[main]: soc/mediatek: Add support for MediaTek firmware support package
by Yidi Lin (Code Review) 19 Dec '24

19 Dec '24

Yidi Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85665?usp=email ) Change subject: soc/mediatek: Add support for MediaTek firmware support package ...................................................................... soc/mediatek: Add support for MediaTek firmware support package Starting from MT8196, MediaTek platform introudces a new blob named MediaTek firmeware support package (mtk-fsp). The features of mtk-fsp includes but not limit to, - Security settings, e.g: Device Access Proctection Control, Security Memory Protection Unit. - Initialization for advanced CPU frequency control. This patch implements APIs for 1. Exchanging data between coreboot and mtk-fsp. 2. Loading and running the mtk-fsp blob at a specific bootstage. BUG=b:373797027 TEST=emerge-rauru coreboot; Run mock blob and return from mock blob. Change-Id: Idef3518f9763fe5f74adb459c137db164563e483 Signed-off-by: Yidi Lin <yidilin(a)chromium.org> --- A src/soc/mediatek/common/include/soc/mtk_fsp.h A src/soc/mediatek/common/include/soc/mtk_fsp_common.h A src/soc/mediatek/common/mtk_fsp.c M src/soc/mediatek/mt8196/Makefile.mk 4 files changed, 176 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/85665/1 diff --git a/src/soc/mediatek/common/include/soc/mtk_fsp.h b/src/soc/mediatek/common/include/soc/mtk_fsp.h new file mode 100644 index 0000000..c018169 --- /dev/null +++ b/src/soc/mediatek/common/include/soc/mtk_fsp.h @@ -0,0 +1,11 @@ +#ifndef __SOC_MEDIATEK_COMMON_INCLUDE_SOC_MTK_FSP_H__ +#define __SOC_MEDIATEK_COMMON_INCLUDE_SOC_MTK_FSP_H__ + +#include <soc/mtk_fsp_common.h> + +void mtk_fsp_init(void); +enum cb_err mtk_fsp_add_param(enum fsp_param_type type, size_t param_size, + void *param); +enum cb_err mtk_fsp_load_and_run(enum fsp_phase phase); + +#endif /* __SOC_MEDIATEK_COMMON_INCLUDE_SOC_MTK_FSP_H__ */ diff --git a/src/soc/mediatek/common/include/soc/mtk_fsp_common.h b/src/soc/mediatek/common/include/soc/mtk_fsp_common.h new file mode 100644 index 0000000..043417a --- /dev/null +++ b/src/soc/mediatek/common/include/soc/mtk_fsp_common.h @@ -0,0 +1,59 @@ +#ifndef __COMMON_INCLUDE_MTK_FSP_COMMON_H__ +#define __COMMON_INCLUDE_MTK_FSP_COMMON_H__ + +#include <stdarg.h> +#include <stdint.h> + +#define INTF_MAJOR_VER 1 +#define INTF_MINOR_VER 0 + +enum fsp_status { + FSP_STATUS_SUCCESS = 0, + FSP_STATUS_INVALID_VERSION, +}; + +enum fsp_phase { + ROMSTAGE_INIT = 0x30, + RAMSTAGE_MAINBOARD_INIT = 0x40, + RAMSTAGE_SOC_INIT = 0x50, +}; + +enum fsp_param_io { + FSP_PARAM_IO_INVALID = 0, + FSP_PARAM_IO_IN, + FSP_PARAM_IO_OUT, + FSP_PARAM_IO_INOUT, +}; + +#define FSP_PARAM_IO_ENCODE(x) ((uint32_t)(x) << 30) + +enum fsp_param_type { + FSP_PARAM_TYPE_INVALID = 0, + /* 0x40000000+ reserved for input type params */ + FSP_PARAM_TYPE_IN = FSP_PARAM_IO_ENCODE(FSP_PARAM_IO_IN), + + /* 0x80000000+ reserved for output type params */ + FSP_PARAM_TYPE_OUT = FSP_PARAM_IO_ENCODE(FSP_PARAM_IO_OUT), + + /* 0xC0000000+ reserved for the params that support both input and output */ + FSP_PARAM_TYPE_INOUT = FSP_PARAM_IO_ENCODE(FSP_PARAM_IO_INOUT), +}; + +struct mtk_fsp_intf { + uint8_t major_version; + uint8_t minor_version; + uint16_t header_size; + uint32_t phase; /* enum fsp_phase */ + int32_t status; /* enum fsp_status */ + uint16_t entry_size; + uint8_t num_entries; + uint8_t reserved; + int (*do_vprintf)(const char *fmt, va_list args); + struct mtk_fsp_param { + uint32_t param_type; + uint32_t param_size; + void *param; + } entries[]; +}; + +#endif /* __COMMON_INCLUDE_MTK_FSP_COMMON_H__ */ diff --git a/src/soc/mediatek/common/mtk_fsp.c b/src/soc/mediatek/common/mtk_fsp.c new file mode 100644 index 0000000..f8ccdae --- /dev/null +++ b/src/soc/mediatek/common/mtk_fsp.c @@ -0,0 +1,104 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <cbfs.h> +#include <console/console.h> +#include <soc/mtk_fsp.h> + +#define MAX_PARAM_ENTRIES 32 +#define FSP_INTF_SIZE (sizeof(struct mtk_fsp_intf) + \ + sizeof(struct mtk_fsp_param) * MAX_PARAM_ENTRIES) + +static struct mtk_fsp_intf *intf; +static uint8_t fsp_intf_buf[FSP_INTF_SIZE] __aligned(8); + +static int vprintf_wrapper(const char *fmt, va_list args) +{ + return vprintk(BIOS_INFO, fmt, args); +} + +void mtk_fsp_init(void) +{ + intf = (struct mtk_fsp_intf *)fsp_intf_buf; + intf->major_version = INTF_MAJOR_VER; + intf->minor_version = INTF_MINOR_VER; + intf->header_size = sizeof(struct mtk_fsp_intf); + intf->entry_size = sizeof(struct mtk_fsp_param); + intf->num_entries = 0; + intf->do_vprintf = vprintf_wrapper; +} + +enum cb_err mtk_fsp_add_param(enum fsp_param_type type, size_t param_size, + void *param) +{ + struct mtk_fsp_param *entry; + + if (!intf) + mtk_fsp_init(); + + if (intf->num_entries == MAX_PARAM_ENTRIES) { + printk(BIOS_ERR, "%s: run out all entries\n", __func__); + return CB_ERR; + } + + entry = &intf->entries[intf->num_entries]; + + entry->param_type = type; + entry->param_size = param_size; + entry->param = param; + intf->num_entries++; + + return CB_SUCCESS; +} + +static void mtk_fsp_dump_intf(void) +{ + struct mtk_fsp_param *entry; + + if (!intf) { + printk(BIOS_ERR, "%s: intf is not initialized\n", __func__); + return; + } + + printk(BIOS_DEBUG, "%s: major version: %u, minor version: %u\n", + __func__, intf->major_version, intf->minor_version); + printk(BIOS_DEBUG, "%s: FSP phase: %u, status: %d\n", + __func__, intf->phase, intf->status); + printk(BIOS_DEBUG, "%-5s %-10s %-10s %s\n", "Param", "type", "size", "address"); + for (int i = 0; i < intf->num_entries; i++) { + entry = &intf->entries[i]; + printk(BIOS_DEBUG, "%-5u %-10u %-10u %p\n", + i, entry->param_type, entry->param_size, entry->param); + } +} + +static const char *mtk_fsp_file(void) +{ + return CONFIG_CBFS_PREFIX "/mtk_fsp_" ENV_STRING; +} + +enum cb_err mtk_fsp_load_and_run(enum fsp_phase phase) +{ + struct prog fsp = PROG_INIT(PROG_REFCODE, mtk_fsp_file()); + + if (cbfs_prog_stage_load(&fsp)) { + printk(BIOS_ERR, "%s: CBFS load program failed\n", __func__); + return CB_ERR; + } + + if (!intf) + mtk_fsp_init(); + intf->phase = phase; + + prog_set_entry(&fsp, prog_entry(&fsp), intf); + prog_run(&fsp); + + if (intf->status != FSP_STATUS_SUCCESS) { + mtk_fsp_dump_intf(); + return CB_ERR; + } + + printk(BIOS_INFO, "%s: run %s at phase %d done\n", + __func__, mtk_fsp_file(), phase); + + return CB_SUCCESS; +} diff --git a/src/soc/mediatek/mt8196/Makefile.mk b/src/soc/mediatek/mt8196/Makefile.mk index b61f7d9..3d8585b 100644 --- a/src/soc/mediatek/mt8196/Makefile.mk +++ b/src/soc/mediatek/mt8196/Makefile.mk @@ -34,6 +34,7 @@ romstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c romstage-y += ../common/mt6363.c mt6363.c romstage-y += ../common/mt6373.c mt6373.c +romstage-y += ../common/mtk_fsp.c romstage-y += mtk_pwrsel.c romstage-y += ../common/pmif_clk.c pmif_clk.c romstage-y += ../common/pmif.c pmif_init.c @@ -52,6 +53,7 @@ ramstage-y += ../common/mt6363.c mt6363.c ramstage-y += ../common/mt6363_sdmadc.c ramstage-y += ../common/mt6373.c mt6373.c +ramstage-y += ../common/mtk_fsp.c ramstage-y += soc.c ramstage-y += ../common/sspm.c sspm_sram.c ramstage-y += ../common/pmif_clk.c pmif_clk.c -- To view, visit https://review.coreboot.org/c/coreboot/+/85665?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idef3518f9763fe5f74adb459c137db164563e483 Gerrit-Change-Number: 85665 Gerrit-PatchSet: 1 Gerrit-Owner: Yidi Lin <yidilin(a)google.com>

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[XS] Change in coreboot[main]: mb/google/rauru: Add pwrsel init in romstage
by Yidi Lin (Code Review) 19 Dec '24

19 Dec '24

Yidi Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85620?usp=email ) ( 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/google/rauru: Add pwrsel init in romstage ...................................................................... mb/google/rauru: Add pwrsel init in romstage BUG=b:317009620 TEST=build pass, reg set ok, log show: PWR_SEL = 0x0 PWRSEL_CONFIG = 0x7fff Change-Id: I37c0fb905f99491ca99f04bc5bfa6abfb1c01059 Signed-off-by: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85620 Reviewed-by: Yidi Lin <yidilin(a)google.com> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/rauru/romstage.c 1 file changed, 2 insertions(+), 0 deletions(-) Approvals: Yu-Ping Wu: Looks good to me, approved build bot (Jenkins): Verified Yidi Lin: Looks good to me, approved diff --git a/src/mainboard/google/rauru/romstage.c b/src/mainboard/google/rauru/romstage.c index ebeedb8..b6f0d4e 100644 --- a/src/mainboard/google/rauru/romstage.c +++ b/src/mainboard/google/rauru/romstage.c @@ -3,11 +3,13 @@ #include <arch/stages.h> #include <soc/emi.h> #include <soc/irq2axi.h> +#include <soc/mtk_pwrsel.h> #include <soc/pcie.h> void platform_romstage_main(void) { irq2axi_disable(); + pwrsel_init(); mtk_dram_init(); if (CONFIG(PCI)) -- To view, visit https://review.coreboot.org/c/coreboot/+/85620?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I37c0fb905f99491ca99f04bc5bfa6abfb1c01059 Gerrit-Change-Number: 85620 Gerrit-PatchSet: 4 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: soc/mediatek/mt8196: Add pwrsel driver
by Yidi Lin (Code Review) 19 Dec '24

19 Dec '24

Yidi Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85613?usp=email ) Change subject: soc/mediatek/mt8196: Add pwrsel driver ...................................................................... soc/mediatek/mt8196: Add pwrsel driver The MediaTek pwrsel (Power Select) is mainly used to reduce power consumption, controlled by mcupm. BUG=b:317009620 TEST=Build pass Change-Id: Ib1b8588810fdad5c675dee865627337269b57d18 Signed-off-by: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85613 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yidi Lin <yidilin(a)google.com> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/soc/mediatek/mt8196/Makefile.mk M src/soc/mediatek/mt8196/include/soc/addressmap.h A src/soc/mediatek/mt8196/include/soc/mtk_pwrsel.h A src/soc/mediatek/mt8196/mtk_pwrsel.c 4 files changed, 47 insertions(+), 0 deletions(-) Approvals: Yu-Ping Wu: Looks good to me, approved build bot (Jenkins): Verified Yidi Lin: Looks good to me, approved diff --git a/src/soc/mediatek/mt8196/Makefile.mk b/src/soc/mediatek/mt8196/Makefile.mk index 2e78e1a..b61f7d9 100644 --- a/src/soc/mediatek/mt8196/Makefile.mk +++ b/src/soc/mediatek/mt8196/Makefile.mk @@ -34,6 +34,7 @@ romstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c romstage-y += ../common/mt6363.c mt6363.c romstage-y += ../common/mt6373.c mt6373.c +romstage-y += mtk_pwrsel.c romstage-y += ../common/pmif_clk.c pmif_clk.c romstage-y += ../common/pmif.c pmif_init.c romstage-y += pmif_spmi.c diff --git a/src/soc/mediatek/mt8196/include/soc/addressmap.h b/src/soc/mediatek/mt8196/include/soc/addressmap.h index dc21f60..fcb5fc8 100644 --- a/src/soc/mediatek/mt8196/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8196/include/soc/addressmap.h @@ -8,6 +8,7 @@ MCUPM_CFG_BASE = 0x0C240000, BUS_TRACE_MONITOR_BASE = 0x0D040000, IO_PHYS = 0x10000000, + MFGSYS_BASE = 0x40000000, }; enum { diff --git a/src/soc/mediatek/mt8196/include/soc/mtk_pwrsel.h b/src/soc/mediatek/mt8196/include/soc/mtk_pwrsel.h new file mode 100644 index 0000000..327735e --- /dev/null +++ b/src/soc/mediatek/mt8196/include/soc/mtk_pwrsel.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ + +#ifndef __SOC_MEDIATEK_MT8196_MTK_PWRSEL__ +#define __SOC_MEDIATEK_MT8196_MTK_PWRSEL__ + +#include <soc/addressmap.h> + +#define VAL_PWRSEL 0x0 +#define VAL_PWRSEL_AUTO_MODE 0x1FF0000 +#define OFFSET_PWRSEL 0x04A0 +#define OFFSET_PWRSEL_AUTO_MODE_CFG 0x04A4 + +#define MFG_VCORE_AO_CFG_BASE (MFGSYS_BASE + 0x0B860000) /* 0x4B860000 */ +#define MFG_VCORE_AO_RPC_PWRSEL_CONFIG (MFG_VCORE_AO_CFG_BASE + 0x00B4) /* 0x4B8600B4 */ + +void pwrsel_init(void); + +#endif /* end of __SOC_MEDIATEK_MT8196_MTK_PWRSEL__ */ diff --git a/src/soc/mediatek/mt8196/mtk_pwrsel.c b/src/soc/mediatek/mt8196/mtk_pwrsel.c new file mode 100644 index 0000000..b1cb528 --- /dev/null +++ b/src/soc/mediatek/mt8196/mtk_pwrsel.c @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ + +#include <console/console.h> +#include <device/mmio.h> +#include <soc/mtk_pwrsel.h> + +static void cpu_pwrsel_init(void) +{ + write32p(MCUSYS_BASE + OFFSET_PWRSEL, VAL_PWRSEL); + write32p(MCUSYS_BASE + OFFSET_PWRSEL_AUTO_MODE_CFG, VAL_PWRSEL_AUTO_MODE); +} + +static void gpu_pwrsel_init(void) +{ + write32p(MFG_VCORE_AO_RPC_PWRSEL_CONFIG, GENMASK(14, 0)); +} + +void pwrsel_init(void) +{ + cpu_pwrsel_init(); + gpu_pwrsel_init(); + + /* PWR_SEL must be 0x0 */ + printk(BIOS_DEBUG, "PWR_SEL = %#x\n", read32p(MCUSYS_BASE + OFFSET_PWRSEL)); + /* PWRSEL_CONFIG must be 0x7fff */ + printk(BIOS_DEBUG, "PWRSEL_CONFIG = %#x\n", read32p(MFG_VCORE_AO_RPC_PWRSEL_CONFIG)); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/85613?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib1b8588810fdad5c675dee865627337269b57d18 Gerrit-Change-Number: 85613 Gerrit-PatchSet: 5 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

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[L] Change in coreboot[main]: soc/mediatek/mt8196: Add GPUEB support
by Yidi Lin (Code Review) 19 Dec '24

19 Dec '24

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yu-Ping Wu. Yidi Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85654?usp=email ) Change subject: soc/mediatek/mt8196: Add GPUEB support ...................................................................... Patch Set 2: Code-Review+1 (2 comments) File src/soc/mediatek/mt8196/gpueb.c: https://review.coreboot.org/c/coreboot/+/85654/comment/606dc9bb_e6b2e926?us… : PS2, Line 236: aut align with `(void *)` File src/soc/mediatek/mt8196/include/soc/gpueb_priv.h: https://review.coreboot.org/c/coreboot/+/85654/comment/aa4b0c87_d362e412?us… : PS2, Line 157: #define DUMP_REG(reg) printk(BIOS_CRIT, #reg "(%#x) = %#x\n", (reg), read32p((reg))) move to gpueb.c -- To view, visit https://review.coreboot.org/c/coreboot/+/85654?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0f10dfc753f73df97ea08a4c23e97de416832be2 Gerrit-Change-Number: 85654 Gerrit-PatchSet: 2 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Andy Hsu <andy.hsu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Thu, 19 Dec 2024 09:14:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/google/rauru: Disable modem power
by Jarried Lin (Code Review) 19 Dec '24

19 Dec '24

Jarried Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85663?usp=email ) Change subject: mb/google/rauru: Disable modem power ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/85663?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I71bda7055afc902525501ddf7074f9b2c5550d4a Gerrit-Change-Number: 85663 Gerrit-PatchSet: 1 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 19 Dec 2024 09:01:58 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

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[M] Change in coreboot[main]: soc/mediatek/mt8196: Add disable modem power driver
by Jarried Lin (Code Review) 19 Dec '24

19 Dec '24

Jarried Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85651?usp=email ) Change subject: soc/mediatek/mt8196: Add disable modem power driver ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/85651?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia8808e3500727753e4537017b46ac8ab39d59468 Gerrit-Change-Number: 85651 Gerrit-PatchSet: 3 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 19 Dec 2024 09:01:54 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

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[M] Change in coreboot[main]: soc/intel/meteorlake: Use ASPM helpers from Alder Lake
by Kapil Porwal (Code Review) 19 Dec '24

19 Dec '24

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Sean Rhodes, Subrata Banik, Tarun. Kapil Porwal has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/83678?usp=email ) Change subject: soc/intel/meteorlake: Use ASPM helpers from Alder Lake ...................................................................... Patch Set 5: Code-Review+2 (2 comments) Patchset: PS5: We also need these changes for PTL. File src/soc/intel/meteorlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/83678/comment/e2bffb3e_6dfce612?us… : PS5, Line 676: pch > It could be just `pcie` for MTL. I see, you are trying to move this code to a common place. -- To view, visit https://review.coreboot.org/c/coreboot/+/83678?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia5cc11188b245a93c303117589bd9d3c18c2877e Gerrit-Change-Number: 83678 Gerrit-PatchSet: 5 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Thu, 19 Dec 2024 08:36:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Kapil Porwal <kapilporwal(a)google.com>

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[M] Change in coreboot[main]: soc/intel/meteorlake: Use ASPM helpers from Alder Lake
by Kapil Porwal (Code Review) 19 Dec '24

19 Dec '24

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Sean Rhodes, Subrata Banik, Tarun. Kapil Porwal has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/83678?usp=email ) Change subject: soc/intel/meteorlake: Use ASPM helpers from Alder Lake ...................................................................... Patch Set 5: (1 comment) File src/soc/intel/meteorlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/83678/comment/c85e19bc_3b952a5f?us… : PS5, Line 676: pch It could be just `pcie` for MTL. -- To view, visit https://review.coreboot.org/c/coreboot/+/83678?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia5cc11188b245a93c303117589bd9d3c18c2877e Gerrit-Change-Number: 83678 Gerrit-PatchSet: 5 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Thu, 19 Dec 2024 08:24:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[M] Change in coreboot[main]: ec/google/chromeec: Publish LPC GMR address range via CREC _CRS
by Subrata Banik (Code Review) 19 Dec '24

19 Dec '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85603?usp=email ) Change subject: ec/google/chromeec: Publish LPC GMR address range via CREC _CRS ...................................................................... ec/google/chromeec: Publish LPC GMR address range via CREC _CRS This change allows the Chrome EC (CREC) ACPI device to publish the LPC Generic Memory Range (GMR) address range using the _CRS method. The Google CREC driver can now parse this information to determine the MMIO address map, enabling access to the LPC GMR register space. This addresses the issue where the CREC driver was unable to automatically determine the LPC GMR base address. TEST=Able to build and boot google/brox. without this patch: brox-rev0 ~ # cat /proc/iomem | grep fe0 fe000000-fe00ffff : INTC1026:00 fe000000-fe00ffff : intel_scu_ipc fe03e000-fe03efff : 0000:00:1e.0 fe03e000-fe03e1ff : lpss_dev fe03e000-fe03e1ff : serial fe03e200-fe03e2ff : lpss_priv fe03e800-fe03efff : idma64.4 fe03e800-fe03efff : idma64.4 idma64.4 with this patch: brox-rev0 ~ # cat /proc/iomem | grep fe0 fe000000-fe00ffff : INTC1026:00 fe000000-fe00ffff : intel_scu_ipc fe03e000-fe03efff : 0000:00:1e.0 fe03e000-fe03e1ff : lpss_dev fe03e000-fe03e1ff : serial fe03e200-fe03e2ff : lpss_priv fe03e800-fe03efff : idma64.4 fe03e800-fe03efff : idma64.4 idma64.4 fe0b0000-fe0bffff : GOOG0004:00 Change-Id: Ib3ea3e2a482f9eceaa8c15e38b7e708b156bc978 Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85603 Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Reviewed-by: Caveh Jalali <caveh(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/ec/google/chromeec/Kconfig M src/ec/google/chromeec/acpi/cros_ec.asl 2 files changed, 35 insertions(+), 15 deletions(-) Approvals: Kapil Porwal: Looks good to me, approved build bot (Jenkins): Verified Caveh Jalali: Looks good to me, but someone else must approve diff --git a/src/ec/google/chromeec/Kconfig b/src/ec/google/chromeec/Kconfig index f0418ff..eae1fc6 100644 --- a/src/ec/google/chromeec/Kconfig +++ b/src/ec/google/chromeec/Kconfig @@ -167,6 +167,12 @@ If unsure, say N. +config EC_GOOGLE_CHROMEEC_LPC_GENERIC_MEMORY_RANGE + def_bool n + help + Select this option to access LPC GMR (Generic Memory Range) Register to + implement MMIO based communication between EC and AP firmware. + endif # EC_GOOGLE_CHROMEEC source "src/ec/google/chromeec/*/Kconfig" diff --git a/src/ec/google/chromeec/acpi/cros_ec.asl b/src/ec/google/chromeec/acpi/cros_ec.asl index 5b5229b..9cf1f66 100644 --- a/src/ec/google/chromeec/acpi/cros_ec.asl +++ b/src/ec/google/chromeec/acpi/cros_ec.asl @@ -1,5 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#if CONFIG(EC_GOOGLE_CHROMEEC_LPC_GENERIC_MEMORY_RANGE) +#define LPC_GMR_SIZE 0x10000 +#endif + Device (CREC) { Name (_HID, "GOOG0004") @@ -19,26 +23,36 @@ #define EC_SYNC_SHARE_TYPE Exclusive #endif -#ifdef EC_ENABLE_SYNC_IRQ - Name (_CRS, ResourceTemplate () +#if defined(EC_ENABLE_SYNC_IRQ) || defined(EC_ENABLE_SYNC_IRQ_GPIO) + Method (_CRS, 0x0, NotSerialized) { - Interrupt (ResourceConsumer, Level, ActiveLow, - EC_SYNC_SHARE_TYPE) + Name (RBUF, ResourceTemplate() { - EC_SYNC_IRQ - } - }) +#ifdef EC_ENABLE_SYNC_IRQ + Interrupt (ResourceConsumer, Level, ActiveLow, EC_SYNC_SHARE_TYPE) { EC_SYNC_IRQ } #endif #ifdef EC_ENABLE_SYNC_IRQ_GPIO - Name (_CRS, ResourceTemplate () - { - GpioInt (Level, ActiveLow, EC_SYNC_SHARE_TYPE, PullDefault, - 0x0000, "\\_SB.GPIO", 0x00, ResourceConsumer, ,) - { - EC_SYNC_IRQ - } - }) + GpioInt (Level, ActiveLow, EC_SYNC_SHARE_TYPE, PullDefault, + 0x0000, "\\_SB.GPIO", 0x00, ResourceConsumer, ,) + { + EC_SYNC_IRQ + } +#endif + +#if CONFIG(EC_GOOGLE_CHROMEEC_LPC_GENERIC_MEMORY_RANGE) + Memory32Fixed (ReadWrite, 0, 0, MADR) +#endif + }) + +#if CONFIG(EC_GOOGLE_CHROMEEC_LPC_GENERIC_MEMORY_RANGE) + CreateDWordField (RBUF, MADR._BAS, BAS0) + CreateDWordField (RBUF, MADR._LEN, LEN0) + BAS0 = \_SB.PCI0.LPCB.GLGM() + LEN0 = LPC_GMR_SIZE +#endif + Return (RBUF) + } #endif #ifdef EC_ENABLE_MKBP_DEVICE -- To view, visit https://review.coreboot.org/c/coreboot/+/85603?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib3ea3e2a482f9eceaa8c15e38b7e708b156bc978 Gerrit-Change-Number: 85603 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Gwendal Grignou <gwendal(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: soc/intel/cmn/acpi: Add ACPI method to get LGMR address
by Subrata Banik (Code Review) 19 Dec '24

19 Dec '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85602?usp=email ) Change subject: soc/intel/cmn/acpi: Add ACPI method to get LGMR address ...................................................................... soc/intel/cmn/acpi: Add ACPI method to get LGMR address This patch adds an ACPI method to get the LPC Generic Memory Range (LGMR) address. This is necessary for platforms that need to access the LGMR from OS driver. The new method, called GLGM, reads the LGMR address from the LPC PCI configuration space (offset 0x98) and returns it as a 32-bit value. BUG=b:354066052 TEST=Able to build and boot google/brox. Change-Id: I4322cee2c608e550e233c45c68958e8a4046c361 Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85602 Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/common/block/acpi/acpi/lpc.asl 1 file changed, 16 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Kapil Porwal: Looks good to me, approved diff --git a/src/soc/intel/common/block/acpi/acpi/lpc.asl b/src/soc/intel/common/block/acpi/acpi/lpc.asl index c4a7dd3..3e8f5a5 100644 --- a/src/soc/intel/common/block/acpi/acpi/lpc.asl +++ b/src/soc/intel/common/block/acpi/acpi/lpc.asl @@ -9,6 +9,22 @@ Name (_ADR, 0x001f0000) Name (_DDN, "LPC Bus Device") + OperationRegion (LPCP, PCI_Config, 0x00, 0x100) + Field (LPCP, DWordAcc, NoLock, Preserve) + { + Offset(0x98), /* LGMR */ + LGEN, 1, /* Enable */ + , 15, + LADR, 16, /* MADDR [31:16] */ + } + + /* Get LGMR */ + Method (GLGM, 0, Serialized) + { + Local0 = LADR << 16 + Return (Local0) + } + /* DMA Controller */ Device (DMAC) { -- To view, visit https://review.coreboot.org/c/coreboot/+/85602?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4322cee2c608e550e233c45c68958e8a4046c361 Gerrit-Change-Number: 85602 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Gwendal Grignou <gwendal(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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