coreboot-gerrit December 2024

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[L] Change in coreboot[main]: drivers/amd/opensil/mpio: Factor out common MPIO symbols from vendorcode
by Martin Roth (Code Review) 19 Dec '24

19 Dec '24

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Martin L Roth, Matt DeVillier, Nick Kochlowski, Varshit Pandya. Martin Roth has posted comments on this change by Nick Kochlowski. ( https://review.coreboot.org/c/coreboot/+/85632?usp=email ) Change subject: drivers/amd/opensil/mpio: Factor out common MPIO symbols from vendorcode ...................................................................... Patch Set 6: (5 comments) Patchset: PS6: I wouldn't insist on it, but in my opinion, this would be better split into a few different patches making changes in specific areas: 1) Add the code to drivers 2) switch phoenix 3) switch birman 4) switch genoa 5) switch onyx 6) remove vendorcode or something like that. We just prefer not to make changes in so many places at once unless it's required. Maybe it is in this case, but I don't think so... File src/drivers/amd/opensil/mpio/chip.h: https://review.coreboot.org/c/coreboot/+/85632/comment/9a851d67_e0824e5c?us… : PS6, Line 8: void configure_mpio(void); Why does this go in chip.h and not in opensil.h? File src/drivers/amd/opensil/mpio/chip.c: https://review.coreboot.org/c/coreboot/+/85632/comment/92b64706_f42dfd62?us… : PS6, Line 8: struct chip_operations drivers_amd_opensil_mpio_ops = { : .name = "AMD MPIO", : }; Why do these go in chip.c? Obviously the *can* go here, but that's not typically the case. Looking through the entirety of the drivers subdirectory, I see one case out of maybe 50 where this is in chip.c. File src/vendorcode/amd/opensil/Kconfig: https://review.coreboot.org/c/coreboot/+/85632/comment/eedc5615_c05b8f2a?us… : PS6, Line 28: ../../../../vendorcode '$(top)/src/vendorcode' ? File src/vendorcode/amd/opensil/stub/mpio/chip.c: https://review.coreboot.org/c/coreboot/+/85632/comment/5d9433e1_ffe03cb0?us… : PS6, Line 6: "../../opensil.h" <src/vendorcode/amd/opensil/opensil.h>? -- To view, visit https://review.coreboot.org/c/coreboot/+/85632?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8b1f92f08565216dd93203a06015e3eec1e7bb69 Gerrit-Change-Number: 85632 Gerrit-PatchSet: 6 Gerrit-Owner: Nick Kochlowski <nickkochlowski(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Nick Kochlowski <nickkochlowski(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 19 Dec 2024 17:02:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[M] Change in coreboot[main]: drivers/amd/opensil: Add openSIL timepoint calls
by Martin Roth (Code Review) 19 Dec '24

19 Dec '24

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Martin L Roth, Matt DeVillier, Nick Kochlowski, Varshit Pandya. Martin Roth has posted comments on this change by Nick Kochlowski. ( https://review.coreboot.org/c/coreboot/+/85631?usp=email ) Change subject: drivers/amd/opensil: Add openSIL timepoint calls ...................................................................... Patch Set 6: (3 comments) File src/drivers/amd/opensil/Kconfig: https://review.coreboot.org/c/coreboot/+/85631/comment/fb859c68_8e52cc87?us… : PS6, Line 5: depends on SOC_AMD_OPENSIL I don't think this is needed, or actually even useful. Because there's no prompt, the option *must* be selected to be enabled. Using a select will override a "depends on" statement. File src/drivers/amd/opensil/opensil.h: https://review.coreboot.org/c/coreboot/+/85631/comment/aa20c667_57dc4f93?us… : PS6, Line 3: _OPENSIL_DRIVER_H_ Nit: maybe "DRIVER_AMD_OPENSIL", without the underscores? Or not. It's not critical, but we'd like to get rid of all of the underscores at some point. We thought they were useful, but apparently they violate some spec or another. File src/soc/amd/phoenix/chip.c: https://review.coreboot.org/c/coreboot/+/85631/comment/a27e9c4a_d9ca3afc?us… : PS6, Line 3: /* TODO: Update for Phoenix */ Not related to this patch, but maybe we can get rid of this todo soon? -- To view, visit https://review.coreboot.org/c/coreboot/+/85631?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If0559fc0ff0ec55e9ef131e5ed20dfb5baa651da Gerrit-Change-Number: 85631 Gerrit-PatchSet: 6 Gerrit-Owner: Nick Kochlowski <nickkochlowski(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Nick Kochlowski <nickkochlowski(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 19 Dec 2024 16:49:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: mb/google/brox: Include CSE reset in mainboard reset expectation
by Karthik Ramasubramanian (Code Review) 19 Dec '24

19 Dec '24

Karthik Ramasubramanian has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85642?usp=email ) Change subject: mb/google/brox: Include CSE reset in mainboard reset expectation ...................................................................... mb/google/brox: Include CSE reset in mainboard reset expectation If CSE is in RO, then a reset is expected for CSE to jump to RW. Include that reset in mainboard_expects_another_reset() logic. This will avoid unnecessary warm reset during regular boot flow in boards with non-UFS storage. BUG=None TEST=Build Brox BIOS image and boot to OS. Ensure that redundant reset to disable UFS controller is avoided. Before this change: [INFO ] Disabling UFS controllers [INFO ] Warm Reset after disabling UFS controllers [INFO ] system_reset() called! <snip> [DEBUG] HECI: Global Reset(Type:1) Command <snip> [INFO ] Disabling UFS controllers [INFO ] Warm Reset after disabling UFS controllers [INFO ] system_reset() called! After this change: [DEBUG] HECI: Global Reset(Type:1) Command <snip> [INFO ] Disabling UFS controllers [INFO ] Warm Reset after disabling UFS controllers [INFO ] system_reset() called! Change-Id: I80a46b15813b6bdfa6c029c54590f4b7c2a6754b Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85642 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M src/mainboard/google/brox/variants/baseboard/brox/romstage.c 1 file changed, 6 insertions(+), 0 deletions(-) Approvals: Subrata Banik: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/google/brox/variants/baseboard/brox/romstage.c b/src/mainboard/google/brox/variants/baseboard/brox/romstage.c index 66ed99b..6a03a9a 100644 --- a/src/mainboard/google/brox/variants/baseboard/brox/romstage.c +++ b/src/mainboard/google/brox/variants/baseboard/brox/romstage.c @@ -3,6 +3,7 @@ #include <baseboard/variants.h> #include <cbfs.h> #include <ec/google/chromeec/ec.h> +#include <intelblocks/cse.h> #include <security/vboot/vboot_common.h> #include <security/vboot/misc.h> #include <soc/romstage.h> @@ -53,9 +54,14 @@ bool mainboard_expects_another_reset(void) { + /* Do not change the order of the check in this function */ if (vboot_recovery_mode_enabled()) return false; + /* If CSE is booting from RO, CSE state switch will issue a reset anyway. */ + if (!is_cse_boot_to_rw()) + return true; + if (!CONFIG(VBOOT) || (vboot_is_gbb_flag_set(VB2_GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC) && vboot_is_gbb_flag_set(VB2_GBB_FLAG_DISABLE_AUXFW_SOFTWARE_SYNC))) -- To view, visit https://review.coreboot.org/c/coreboot/+/85642?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I80a46b15813b6bdfa6c029c54590f4b7c2a6754b Gerrit-Change-Number: 85642 Gerrit-PatchSet: 3 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: mb/qemu-riscv: enable vboot
by Carlos López (Code Review) 19 Dec '24

19 Dec '24

Attention is currently required from: Maximilian Brune, Philipp Hug, ron minnich. Hello Maximilian Brune, Philipp Hug, ron minnich, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85677?usp=email to look at the new patch set (#2). Change subject: mb/qemu-riscv: enable vboot ...................................................................... mb/qemu-riscv: enable vboot Add the option to enable vboot for the qemu-riscv board. In order to do this, enable the qemu boot device driver, so that vboot is able to store and modify data in flash, as well as the fw_cfg driver. Additionally, add FMD files to describe the two different vboot FMAP configurations (A or A + B), and update the memory layout in the linker script to accommodate for the VBOOT2_WORK buffer. TEST=boot verified with qemu-system-riscv64 + OpenSBI Change-Id: I5a6dfa10b66c20851c5012679a9bc0168d1cf17c Signed-off-by: Carlos López <carlos.lopez(a)openchip.com> --- M src/mainboard/emulation/qemu-riscv/Kconfig M src/mainboard/emulation/qemu-riscv/Makefile.mk M src/mainboard/emulation/qemu-riscv/memlayout.ld M src/mainboard/emulation/qemu-riscv/rom_media.c A src/mainboard/emulation/qemu-riscv/vboot-rwa.fmd A src/mainboard/emulation/qemu-riscv/vboot-rwab.fmd 6 files changed, 68 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/85677/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85677?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5a6dfa10b66c20851c5012679a9bc0168d1cf17c Gerrit-Change-Number: 85677 Gerrit-PatchSet: 2 Gerrit-Owner: Carlos López <carlos.lopezr4096(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: ron minnich <rminnich(a)gmail.com>

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[S] Change in coreboot[main]: soc/mediatek/mt8189: Initialize watchdog
by Vince Liu (Code Review) 19 Dec '24

19 Dec '24

Vince Liu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85678?usp=email ) Change subject: soc/mediatek/mt8189: Initialize watchdog ...................................................................... soc/mediatek/mt8189: Initialize watchdog Add watchdog support for MT8189. BUG=b:379008996 BRANCH=none TEST=build pass and WDT makes DUT reboot when MTK_WDT_MODE_ENABLE is set. Change-Id: I496fce91e52393db31fd1fb5a1c68d91b2ed073e Signed-off-by: Vince Liu <vince-wl.liu(a)mediatek.corp-partner.google.com> --- M src/soc/mediatek/mt8189/Makefile.mk M src/soc/mediatek/mt8189/bootblock.c A src/soc/mediatek/mt8189/include/soc/wdt.h A src/soc/mediatek/mt8189/wdt.c 4 files changed, 39 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/85678/1 diff --git a/src/soc/mediatek/mt8189/Makefile.mk b/src/soc/mediatek/mt8189/Makefile.mk index 9b09628..e997ec1 100644 --- a/src/soc/mediatek/mt8189/Makefile.mk +++ b/src/soc/mediatek/mt8189/Makefile.mk @@ -8,6 +8,7 @@ bootblock-y += bootblock.c bootblock-y += ../common/mmu_operations.c +bootblock-y += ../common/wdt.c ../common/wdt_req.c wdt.c romstage-y += ../common/cbmem.c romstage-y += emi.c diff --git a/src/soc/mediatek/mt8189/bootblock.c b/src/soc/mediatek/mt8189/bootblock.c index 89cd22d..3e8a09c 100644 --- a/src/soc/mediatek/mt8189/bootblock.c +++ b/src/soc/mediatek/mt8189/bootblock.c @@ -1,9 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only OR MIT */ #include <bootblock_common.h> +#include <soc/wdt.h> #include <soc/mmu_operations.h> void bootblock_soc_init(void) { mtk_mmu_init(); + mtk_wdt_init(); } diff --git a/src/soc/mediatek/mt8189/include/soc/wdt.h b/src/soc/mediatek/mt8189/include/soc/wdt.h new file mode 100644 index 0000000..f6e808c --- /dev/null +++ b/src/soc/mediatek/mt8189/include/soc/wdt.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ + +/* + * This file is created based on MT8189 Functional Specification + * Chapter number: 8.2 + */ + +#ifndef __SOC_MEDIATEK_MT8189_INCLUDE_SOC_WDT_H__ +#define __SOC_MEDIATEK_MT8189_INCLUDE_SOC_WDT_H__ + +#include <soc/wdt_common.h> + +#define MTK_WDT_SPM_THERMAL_VAL 1 + +DEFINE_BIT(MTK_WDT_SPM_THERMAL_EN, 0) +DEFINE_BIT(MTK_WDT_THERMAL_EN, 18) +DEFINE_BIT(MTK_WDT_THERMAL_IRQ, 18) + +#endif /* __SOC_MEDIATEK_MT8189_INCLUDE_SOC_WDT_H__ */ diff --git a/src/soc/mediatek/mt8189/wdt.c b/src/soc/mediatek/mt8189/wdt.c new file mode 100644 index 0000000..ca6518b --- /dev/null +++ b/src/soc/mediatek/mt8189/wdt.c @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ + +/* + * This file is created based on MT8189 Functional Specification + * Chapter number: 8.2 + */ + +#include <device/mmio.h> +#include <soc/addressmap.h> +#include <soc/wdt.h> + +#define MTK_WDT_CLR_STATUS 0x230001FF + +void mtk_wdt_clr_status(void) +{ + write32(&mtk_wdt->wdt_mode, MTK_WDT_CLR_STATUS); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/85678?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I496fce91e52393db31fd1fb5a1c68d91b2ed073e Gerrit-Change-Number: 85678 Gerrit-PatchSet: 1 Gerrit-Owner: Vince Liu <vince-wl.liu(a)mediatek.com>

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[L] Change in coreboot[main]: soc/mediatek/mt8189: Add GPIO driver
by Yidi Lin (Code Review) 19 Dec '24

19 Dec '24

Attention is currently required from: Hung-Te Lin, Vince Liu. Yidi Lin has posted comments on this change by Vince Liu. ( https://review.coreboot.org/c/coreboot/+/85667?usp=email ) Change subject: soc/mediatek/mt8189: Add GPIO driver ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85667?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia87fe0975add95fcfad16d55586559c7f912a624 Gerrit-Change-Number: 85667 Gerrit-PatchSet: 1 Gerrit-Owner: Vince Liu <vince-wl.liu(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Vince Liu <vince-wl.liu(a)mediatek.com> Gerrit-Comment-Date: Thu, 19 Dec 2024 16:12:01 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: mb/qemu-riscv: enable vboot
by Carlos López (Code Review) 19 Dec '24

19 Dec '24

Attention is currently required from: Maximilian Brune, Philipp Hug, ron minnich. Carlos López has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85677?usp=email ) Change subject: mb/qemu-riscv: enable vboot ...................................................................... mb/qemu-riscv: enable vboot Add the option to enable vboot for the qemu-riscv board. In order to do this, enable the qemu boot device driver, so that vboot is able to store and modify data in flash, as well as the fw_cfg driver. Additionally, add FMD files to describe the two different vboot FMAP configurations (A or A + B), and update the memory layout in the linker script to acommodate for the VBOOT2_WORK buffer. TEST=boot verified with qemu-system-riscv64 + OpenSBI Change-Id: I5a6dfa10b66c20851c5012679a9bc0168d1cf17c Signed-off-by: Carlos López <carlos.lopez(a)openchip.com> --- M src/mainboard/emulation/qemu-riscv/Kconfig M src/mainboard/emulation/qemu-riscv/Makefile.mk M src/mainboard/emulation/qemu-riscv/memlayout.ld M src/mainboard/emulation/qemu-riscv/rom_media.c A src/mainboard/emulation/qemu-riscv/vboot-rwa.fmd A src/mainboard/emulation/qemu-riscv/vboot-rwab.fmd 6 files changed, 68 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/85677/1 diff --git a/src/mainboard/emulation/qemu-riscv/Kconfig b/src/mainboard/emulation/qemu-riscv/Kconfig index 2361e25..ac9bde6 100644 --- a/src/mainboard/emulation/qemu-riscv/Kconfig +++ b/src/mainboard/emulation/qemu-riscv/Kconfig @@ -35,6 +35,17 @@ select ARCH_ROMSTAGE_RISCV select ARCH_RAMSTAGE_RISCV select RISCV_USE_ARCH_TIMER + select BOOT_DEVICE_MEMORY_MAPPED + select DRIVERS_EMULATION_QEMU_FW_CFG + select DRIVERS_EMULATION_QEMU_BOOT_DEVICE + +config VBOOT + select VBOOT_STARTS_IN_BOOTBLOCK + select VBOOT_VBNV_FLASH + +config FMDFILE + default "src/mainboard/emulation/qemu-riscv/vboot-rwa.fmd" if VBOOT_SLOTS_RW_A && !VBOOT_SLOTS_RW_AB + default "src/mainboard/emulation/qemu-riscv/vboot-rwab.fmd" if VBOOT_SLOTS_RW_AB config MEMLAYOUT_LD_FILE string diff --git a/src/mainboard/emulation/qemu-riscv/Makefile.mk b/src/mainboard/emulation/qemu-riscv/Makefile.mk index bed0f80..55e6e79 100644 --- a/src/mainboard/emulation/qemu-riscv/Makefile.mk +++ b/src/mainboard/emulation/qemu-riscv/Makefile.mk @@ -18,4 +18,6 @@ ramstage-y += cbmem.c ramstage-y += chip.c +all-y += ../qemu-i440fx/bootmode.c + CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include diff --git a/src/mainboard/emulation/qemu-riscv/memlayout.ld b/src/mainboard/emulation/qemu-riscv/memlayout.ld index 9c16496..e02c335 100644 --- a/src/mainboard/emulation/qemu-riscv/memlayout.ld +++ b/src/mainboard/emulation/qemu-riscv/memlayout.ld @@ -16,5 +16,8 @@ PRERAM_CBMEM_CONSOLE(QEMU_VIRT_DRAM + 128K + 256K + 256K + 2M, 8K) FMAP_CACHE(QEMU_VIRT_DRAM + 128K + 256K + 256K + 2M + 8K, 2K) CBFS_MCACHE(QEMU_VIRT_DRAM + 128K + 256K + 256K + 2M + 8K + 2K, 10K) - STACK(QEMU_VIRT_DRAM + 128K + 256K + 256K + 2M + 8K + 2K + 10K, 4M) +#if CONFIG(VBOOT_STARTS_IN_BOOTBLOCK) + VBOOT2_WORK(QEMU_VIRT_DRAM + 128K + 256K + 256K + 2M + 8K + 2K + 10K, VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE) +#endif + STACK(QEMU_VIRT_DRAM + 4M, 4M) } diff --git a/src/mainboard/emulation/qemu-riscv/rom_media.c b/src/mainboard/emulation/qemu-riscv/rom_media.c index 3c636ce..531bca8 100644 --- a/src/mainboard/emulation/qemu-riscv/rom_media.c +++ b/src/mainboard/emulation/qemu-riscv/rom_media.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <boot_device.h> +#include <device/qemu_boot_device.h> #include <symbols.h> #include <mainboard/addressmap.h> @@ -10,3 +11,8 @@ { return &boot_dev.rdev; } + +void *qemu_boot_device_addr(void) +{ + return (void *)QEMU_VIRT_FLASH; +} diff --git a/src/mainboard/emulation/qemu-riscv/vboot-rwa.fmd b/src/mainboard/emulation/qemu-riscv/vboot-rwa.fmd new file mode 100644 index 0000000..741d4ba --- /dev/null +++ b/src/mainboard/emulation/qemu-riscv/vboot-rwa.fmd @@ -0,0 +1,20 @@ +FLASH@0 0x02000000 { + BIOS@0 0x02000000 { + WP_RO { + BOOTBLOCK 128K + FMAP 0x800 + RO_FRID 0x40 + RO_PADDING 0x7c0 + GBB 0x1e000 + COREBOOT(CBFS) + } + RW_SECTION_A 0x1c0000 { + VBLOCK_A@0x0 0x10000 + FW_MAIN_A(CBFS) + RW_FWID_A 0x40 + } + + RW_VPD(PRESERVE) 0x1000 + RW_NVRAM(PRESERVE) 0x6000 + } +} diff --git a/src/mainboard/emulation/qemu-riscv/vboot-rwab.fmd b/src/mainboard/emulation/qemu-riscv/vboot-rwab.fmd new file mode 100644 index 0000000..af4c8ea --- /dev/null +++ b/src/mainboard/emulation/qemu-riscv/vboot-rwab.fmd @@ -0,0 +1,25 @@ +FLASH@0 0x02000000 { + BIOS@0 0x02000000 { + WP_RO { + BOOTBLOCK 128K + FMAP 0x800 + RO_FRID 0x40 + RO_PADDING 0x7c0 + GBB 0x1e000 + COREBOOT(CBFS) + } + RW_SECTION_A 0x1c0000 { + VBLOCK_A@0x0 0x10000 + FW_MAIN_A(CBFS) + RW_FWID_A 0x40 + } + RW_SECTION_B 0x1c0000 { + VBLOCK_B@0x0 0x10000 + FW_MAIN_B(CBFS) + RW_FWID_B 0x40 + } + + RW_VPD(PRESERVE) 0x1000 + RW_NVRAM(PRESERVE) 0x6000 + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/85677?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5a6dfa10b66c20851c5012679a9bc0168d1cf17c Gerrit-Change-Number: 85677 Gerrit-PatchSet: 1 Gerrit-Owner: Carlos López <carlos.lopezr4096(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: ron minnich <rminnich(a)gmail.com>

1 0

[XS] Change in coreboot[main]: vboot: update submodule to upstream main
by Carlos López (Code Review) 19 Dec '24

19 Dec '24

Carlos López has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85676?usp=email ) Change subject: vboot: update submodule to upstream main ...................................................................... vboot: update submodule to upstream main Updating from commit f1f70f46 to 3f94e2c7. This brings, among other things, the ability to build vboot for RISC-V. Change-Id: I48f960235088c17dc59235b07926acd52e03deb2 Signed-off-by: Carlos López <carlos.lopez(a)openchip.com> --- M 3rdparty/vboot 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/85676/1 diff --git a/3rdparty/vboot b/3rdparty/vboot index f1f70f4..3f94e2c 160000 --- a/3rdparty/vboot +++ b/3rdparty/vboot @@ -1 +1 @@ -Subproject commit f1f70f46dc5482bb7c654e53ed58d4001e386df2 +Subproject commit 3f94e2c7ed58c4e67d6e7dc6052ec615dbbb9bb4 -- To view, visit https://review.coreboot.org/c/coreboot/+/85676?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I48f960235088c17dc59235b07926acd52e03deb2 Gerrit-Change-Number: 85676 Gerrit-PatchSet: 1 Gerrit-Owner: Carlos López <carlos.lopezr4096(a)gmail.com>

1 0

[XS] Change in coreboot[main]: mb/qemu-riscv: set PCI_IOBASE
by Carlos López (Code Review) 19 Dec '24

19 Dec '24

1 0

[L] Change in coreboot[main]: mb/qemu-i440fx: refactor qemu flash logic as a separate driver
by Carlos López (Code Review) 19 Dec '24

19 Dec '24

Carlos López has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85674?usp=email ) Change subject: mb/qemu-i440fx: refactor qemu flash logic as a separate driver ...................................................................... mb/qemu-i440fx: refactor qemu flash logic as a separate driver The logic for read/write detection on qemu flash can be used by other qemu boards outside i440fx and q35 (the latter currently including the code manually). Factor out the logic as a separate driver that other qemu boards can enable. Boards using the driver must implement qemu_boot_device_addr(), as the address for the flash device might change depending on the architecture. Change-Id: Iaee50b29d079564707e414bb92e949c306fb6ad3 Signed-off-by: Carlos López <carlos.lopez(a)openchip.com> --- M src/drivers/emulation/qemu/Kconfig M src/drivers/emulation/qemu/Makefile.mk A src/drivers/emulation/qemu/qemu_boot_device.c A src/include/device/qemu_boot_device.h M src/mainboard/emulation/qemu-i440fx/Kconfig M src/mainboard/emulation/qemu-i440fx/Makefile.mk M src/mainboard/emulation/qemu-i440fx/rom_media.c M src/mainboard/emulation/qemu-q35/Kconfig M src/mainboard/emulation/qemu-q35/Makefile.mk 9 files changed, 228 insertions(+), 185 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/85674/1 diff --git a/src/drivers/emulation/qemu/Kconfig b/src/drivers/emulation/qemu/Kconfig index cab0694..5fca216 100644 --- a/src/drivers/emulation/qemu/Kconfig +++ b/src/drivers/emulation/qemu/Kconfig @@ -41,3 +41,12 @@ default n help qemu fw_cfg driver + +config DRIVERS_EMULATION_QEMU_BOOT_DEVICE + bool + default n + select BOOT_DEVICE_NOT_SPI_FLASH + select BOOT_DEVICE_SUPPORTS_WRITES + help + qemu boot device driver that detects whether flash is writeable or + not. diff --git a/src/drivers/emulation/qemu/Makefile.mk b/src/drivers/emulation/qemu/Makefile.mk index 76bd864..1596808 100644 --- a/src/drivers/emulation/qemu/Makefile.mk +++ b/src/drivers/emulation/qemu/Makefile.mk @@ -13,3 +13,7 @@ verstage-$(CONFIG_DRIVERS_EMULATION_QEMU_FW_CFG) += fw_cfg.c postcar-$(CONFIG_DRIVERS_EMULATION_QEMU_FW_CFG) += fw_cfg.c ramstage-$(CONFIG_DRIVERS_EMULATION_QEMU_FW_CFG) += fw_cfg.c + +bootblock-$(CONFIG_DRIVERS_EMULATION_QEMU_BOOT_DEVICE) += qemu_boot_device.c +romstage-$(CONFIG_DRIVERS_EMULATION_QEMU_BOOT_DEVICE) += qemu_boot_device.c +ramstage-$(CONFIG_DRIVERS_EMULATION_QEMU_BOOT_DEVICE) += qemu_boot_device.c diff --git a/src/drivers/emulation/qemu/qemu_boot_device.c b/src/drivers/emulation/qemu/qemu_boot_device.c new file mode 100644 index 0000000..e424102 --- /dev/null +++ b/src/drivers/emulation/qemu/qemu_boot_device.c @@ -0,0 +1,197 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* Inspired by OvmfPkg/QemuFlashFvbServicesRuntimeDxe/QemuFlash.c from edk2 */ + +#include <arch/mmio.h> +#include <boot_device.h> +#include <console/console.h> +#include <commonlib/helpers.h> +#include <commonlib/region.h> +#include <device/qemu_boot_device.h> +#include <string.h> + +#define WRITE_BYTE_CMD 0x10 +#define BLOCK_ERASE_CMD 0x20 +#define CLEAR_STATUS_CMD 0x50 +#define READ_STATUS_CMD 0x70 +#define BLOCK_ERASE_CONFIRM_CMD 0xD0 +#define READ_ARRAY_CMD 0xFF + +#define CLEARED_ARRAY_STATUS 0x00 + +#define QEMU_FLASH_BLOCK_SIZE 0x1000 + +static ssize_t qemu_writeat(const struct region_device *rd, const void *b, + size_t offset, size_t size) +{ + const struct mem_region_device *mdev; + size_t i; + volatile char *ptr; + const char *buf = b; + + mdev = container_of(rd, __typeof__(*mdev), rdev); + ptr = &mdev->base[offset]; + + for (i = 0; i < size; i++) { + write8(ptr, WRITE_BYTE_CMD); + write8(ptr, buf[i]); + ptr++; + } + + /* Restore flash to read mode. */ + if (size > 0) { + write8(ptr - 1, READ_ARRAY_CMD); + } + + return size; +} + +static ssize_t qemu_eraseat(const struct region_device *rd, size_t offset, + size_t size) +{ + const struct mem_region_device *mdev; + size_t i; + volatile char *ptr; + + mdev = container_of(rd, __typeof__(*mdev), rdev); + ptr = &mdev->base[offset]; + + if (!IS_ALIGNED(offset, QEMU_FLASH_BLOCK_SIZE)) { + printk(BIOS_ERR, "%s: erased offset isn't multiple of block size\n", + __func__); + return -1; + } + + if (!IS_ALIGNED(size, QEMU_FLASH_BLOCK_SIZE)) { + printk(BIOS_ERR, "%s: erased size isn't multiple of block size\n", + __func__); + return -1; + } + + for (i = 0; i < size; i += QEMU_FLASH_BLOCK_SIZE) { + write8(ptr, BLOCK_ERASE_CMD); + write8(ptr, BLOCK_ERASE_CONFIRM_CMD); + ptr += QEMU_FLASH_BLOCK_SIZE; + } + + /* Restore flash to read mode. */ + if (size > 0) { + write8(ptr - QEMU_FLASH_BLOCK_SIZE, READ_ARRAY_CMD); + } + + return size; +} + +static struct region_device_ops flash_ops; +static struct mem_region_device boot_dev = + MEM_REGION_DEV_INIT(NULL, CONFIG_ROM_SIZE, &flash_ops); + +/* + * Depending on how firmware image was passed to QEMU, it may behave as: + * + * - ROM - memory mapped reads, writes are ignored (FW image mounted with + * '-bios'); + * - RAM - memory mapped reads and writes (FW image mounted with e.g. + * '-device loader'); + * - flash - memory mapped reads, write and erase possible through commands. + * Contrary to physical flash devices erase is not required before writing, + * but it also doesn't hurt. Flash may be split into read-only and read-write + * parts, like OVMF_CODE.fd and OVMF_VARS.fd. Maximal combined size of system + * firmware is hardcoded (QEMU < 5.0.0) or set by default to 8 MiB. On QEMU + * version 5.0.0 or newer, it is configurable with `max-fw-size` machine + * configuration option, up to 16 MiB to not overlap with IOAPIC memory range + * (FW image(s) mounted with '-drive if=pflash'). + * + * This function detects which of the above applies and fills region_device_ops + * accordingly. + */ +void boot_device_init(void) +{ + volatile char *ptr; + char original, readback; + static bool initialized = false; + + if (initialized) + return; + + boot_dev.base = qemu_boot_device_addr(); + + /* + * mmap, munmap and readat are always identical to mem_rdev_rw_ops, other + * functions may vary. + */ + flash_ops = mem_rdev_rw_ops; + + /* + * Find first byte different than any of the commands, simplified. + * + * Detection code few lines below writes commands and tries to read back + * the response. To make that code simpler, make sure that original byte + * is different than any of the commands or expected responses. It is + * expected that such byte will always be found - it is virtually + * impossible to write valid x86 code with just bytes ending with 0, and + * there are also ASCII characters in metadata (CBFS, FMAP) that has bytes + * matching those assumptions. + */ + ptr = (volatile char *)boot_dev.base; + original = read8(ptr); + while (original == (char)0xFF || (original & 0x0F) == 0) + original = read8(++ptr); + + /* + * Detect what type of flash we're dealing with. This also clears any stale + * status bits, so the next read of status register should return known + * value (if pflash is used). + */ + write8(ptr, CLEAR_STATUS_CMD); + readback = read8(ptr); + if (readback == CLEAR_STATUS_CMD) { + printk(BIOS_DEBUG, "QEMU flash behaves as RAM\n"); + /* Restore original content. */ + write8(ptr, original); + } else { + /* Either ROM or QEMU flash implementation. */ + write8(ptr, READ_STATUS_CMD); + readback = read8(ptr); + if (readback == original) { + printk(BIOS_DEBUG, "QEMU flash behaves as ROM\n"); + /* ROM means no writing nor erasing. */ + flash_ops.writeat = NULL; + flash_ops.eraseat = NULL; + } else if (readback == CLEARED_ARRAY_STATUS) { + /* Try writing original value to test whether flash is writable. */ + write8(ptr, WRITE_BYTE_CMD); + write8(ptr, original); + write8(ptr, READ_STATUS_CMD); + readback = read8(ptr); + if (readback & 0x10 /* programming error */) { + printk(BIOS_DEBUG, + "QEMU flash behaves as write-protected flash\n"); + flash_ops.writeat = NULL; + flash_ops.eraseat = NULL; + } else { + printk(BIOS_DEBUG, "QEMU flash behaves as writable flash\n"); + flash_ops.writeat = qemu_writeat; + flash_ops.eraseat = qemu_eraseat; + } + /* Restore flash to read mode. */ + write8(ptr, READ_ARRAY_CMD); + } else { + printk(BIOS_ERR, "Unexpected QEMU flash behavior, assuming ROM\n"); + /* + * This shouldn't happen and first byte of flash may already be + * corrupted by testing, but don't take any further risk. + */ + flash_ops.writeat = NULL; + flash_ops.eraseat = NULL; + } + } + + initialized = true; +} + +/* boot_device_ro() must be defined somewhere else for earlier stages */ +const struct region_device *boot_device_rw(void) +{ + return &boot_dev.rdev; +} diff --git a/src/include/device/qemu_boot_device.h b/src/include/device/qemu_boot_device.h new file mode 100644 index 0000000..4dfded3 --- /dev/null +++ b/src/include/device/qemu_boot_device.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef DEVICE_QEMU_BOOT_DEVICE_H +#define DEVICE_QEMU_BOOT_DEVICE_H + +void *qemu_boot_device_addr(void); + +#endif /* DEVICE_QEMU_BOOT_DEVICE_H */ diff --git a/src/mainboard/emulation/qemu-i440fx/Kconfig b/src/mainboard/emulation/qemu-i440fx/Kconfig index e17e25d..99c3cf3 100644 --- a/src/mainboard/emulation/qemu-i440fx/Kconfig +++ b/src/mainboard/emulation/qemu-i440fx/Kconfig @@ -17,9 +17,8 @@ select MAINBOARD_FORCE_NATIVE_VGA_INIT select HAVE_ASAN_IN_ROMSTAGE select NO_SMM - select BOOT_DEVICE_NOT_SPI_FLASH select BOOT_DEVICE_MEMORY_MAPPED - select BOOT_DEVICE_SUPPORTS_WRITES + select DRIVERS_EMULATION_QEMU_BOOT_DEVICE select DRIVERS_EMULATION_QEMU_FW_CFG config VBOOT diff --git a/src/mainboard/emulation/qemu-i440fx/Makefile.mk b/src/mainboard/emulation/qemu-i440fx/Makefile.mk index c20f427..6dba57a 100644 --- a/src/mainboard/emulation/qemu-i440fx/Makefile.mk +++ b/src/mainboard/emulation/qemu-i440fx/Makefile.mk @@ -1,6 +1,9 @@ ## SPDX-License-Identifier: GPL-2.0-only +bootblock-y += rom_media.c + romstage-y += memmap.c +romstage-y += rom_media.c postcar-y += memmap.c postcar-y += exit_car.S diff --git a/src/mainboard/emulation/qemu-i440fx/rom_media.c b/src/mainboard/emulation/qemu-i440fx/rom_media.c index f4fd3c3..e7e3f6c 100644 --- a/src/mainboard/emulation/qemu-i440fx/rom_media.c +++ b/src/mainboard/emulation/qemu-i440fx/rom_media.c @@ -7,19 +7,9 @@ #include <console/console.h> #include <commonlib/helpers.h> #include <commonlib/region.h> +#include <device/qemu_boot_device.h> #include <string.h> -#define WRITE_BYTE_CMD 0x10 -#define BLOCK_ERASE_CMD 0x20 -#define CLEAR_STATUS_CMD 0x50 -#define READ_STATUS_CMD 0x70 -#define BLOCK_ERASE_CONFIRM_CMD 0xD0 -#define READ_ARRAY_CMD 0xFF - -#define CLEARED_ARRAY_STATUS 0x00 - -#define QEMU_FLASH_BLOCK_SIZE 0x1000 - #if CONFIG(ELOG) #include <southbridge/intel/common/pmutil.h> @@ -35,175 +25,7 @@ void pch_log_state(void) {} #endif -static ssize_t qemu_writeat(const struct region_device *rd, const void *b, - size_t offset, size_t size) +void *qemu_boot_device_addr(void) { - const struct mem_region_device *mdev; - size_t i; - volatile char *ptr; - const char *buf = b; - - mdev = container_of(rd, __typeof__(*mdev), rdev); - ptr = &mdev->base[offset]; - - for (i = 0; i < size; i++) { - write8(ptr, WRITE_BYTE_CMD); - write8(ptr, buf[i]); - ptr++; - } - - /* Restore flash to read mode. */ - if (size > 0) { - write8(ptr - 1, READ_ARRAY_CMD); - } - - return size; -} - -static ssize_t qemu_eraseat(const struct region_device *rd, size_t offset, - size_t size) -{ - const struct mem_region_device *mdev; - size_t i; - volatile char *ptr; - - mdev = container_of(rd, __typeof__(*mdev), rdev); - ptr = &mdev->base[offset]; - - if (!IS_ALIGNED(offset, QEMU_FLASH_BLOCK_SIZE)) { - printk(BIOS_ERR, "%s: erased offset isn't multiple of block size\n", - __func__); - return -1; - } - - if (!IS_ALIGNED(size, QEMU_FLASH_BLOCK_SIZE)) { - printk(BIOS_ERR, "%s: erased size isn't multiple of block size\n", - __func__); - return -1; - } - - for (i = 0; i < size; i += QEMU_FLASH_BLOCK_SIZE) { - write8(ptr, BLOCK_ERASE_CMD); - write8(ptr, BLOCK_ERASE_CONFIRM_CMD); - ptr += QEMU_FLASH_BLOCK_SIZE; - } - - /* Restore flash to read mode. */ - if (size > 0) { - write8(ptr - QEMU_FLASH_BLOCK_SIZE, READ_ARRAY_CMD); - } - - return size; -} - -static struct region_device_ops flash_ops; -static const struct mem_region_device boot_dev = - MEM_REGION_DEV_INIT(0x100000000ULL - CONFIG_ROM_SIZE, CONFIG_ROM_SIZE, &flash_ops); - -/* - * Depending on how firmware image was passed to QEMU, it may behave as: - * - * - ROM - memory mapped reads, writes are ignored (FW image mounted with - * '-bios'); - * - RAM - memory mapped reads and writes (FW image mounted with e.g. - * '-device loader'); - * - flash - memory mapped reads, write and erase possible through commands. - * Contrary to physical flash devices erase is not required before writing, - * but it also doesn't hurt. Flash may be split into read-only and read-write - * parts, like OVMF_CODE.fd and OVMF_VARS.fd. Maximal combined size of system - * firmware is hardcoded (QEMU < 5.0.0) or set by default to 8 MiB. On QEMU - * version 5.0.0 or newer, it is configurable with `max-fw-size` machine - * configuration option, up to 16 MiB to not overlap with IOAPIC memory range - * (FW image(s) mounted with '-drive if=pflash'). - * - * This function detects which of the above applies and fills region_device_ops - * accordingly. - */ -void boot_device_init(void) -{ - volatile char *ptr; - char original, readback; - static bool initialized = false; - - if (initialized) - return; - - /* - * mmap, munmap and readat are always identical to mem_rdev_rw_ops, other - * functions may vary. - */ - flash_ops = mem_rdev_rw_ops; - - /* - * Find first byte different than any of the commands, simplified. - * - * Detection code few lines below writes commands and tries to read back - * the response. To make that code simpler, make sure that original byte - * is different than any of the commands or expected responses. It is - * expected that such byte will always be found - it is virtually - * impossible to write valid x86 code with just bytes ending with 0, and - * there are also ASCII characters in metadata (CBFS, FMAP) that has bytes - * matching those assumptions. - */ - ptr = (volatile char *)boot_dev.base; - original = read8(ptr); - while (original == (char)0xFF || (original & 0x0F) == 0) - original = read8(++ptr); - - /* - * Detect what type of flash we're dealing with. This also clears any stale - * status bits, so the next read of status register should return known - * value (if pflash is used). - */ - write8(ptr, CLEAR_STATUS_CMD); - readback = read8(ptr); - if (readback == CLEAR_STATUS_CMD) { - printk(BIOS_DEBUG, "QEMU flash behaves as RAM\n"); - /* Restore original content. */ - write8(ptr, original); - } else { - /* Either ROM or QEMU flash implementation. */ - write8(ptr, READ_STATUS_CMD); - readback = read8(ptr); - if (readback == original) { - printk(BIOS_DEBUG, "QEMU flash behaves as ROM\n"); - /* ROM means no writing nor erasing. */ - flash_ops.writeat = NULL; - flash_ops.eraseat = NULL; - } else if (readback == CLEARED_ARRAY_STATUS) { - /* Try writing original value to test whether flash is writable. */ - write8(ptr, WRITE_BYTE_CMD); - write8(ptr, original); - write8(ptr, READ_STATUS_CMD); - readback = read8(ptr); - if (readback & 0x10 /* programming error */) { - printk(BIOS_DEBUG, - "QEMU flash behaves as write-protected flash\n"); - flash_ops.writeat = NULL; - flash_ops.eraseat = NULL; - } else { - printk(BIOS_DEBUG, "QEMU flash behaves as writable flash\n"); - flash_ops.writeat = qemu_writeat; - flash_ops.eraseat = qemu_eraseat; - } - /* Restore flash to read mode. */ - write8(ptr, READ_ARRAY_CMD); - } else { - printk(BIOS_ERR, "Unexpected QEMU flash behavior, assuming ROM\n"); - /* - * This shouldn't happen and first byte of flash may already be - * corrupted by testing, but don't take any further risk. - */ - flash_ops.writeat = NULL; - flash_ops.eraseat = NULL; - } - } - - initialized = true; -} - -/* boot_device_ro() is defined in arch/x86/mmap_boot.c */ -const struct region_device *boot_device_rw(void) -{ - return &boot_dev.rdev; + return (void *)(0x100000000ULL - CONFIG_ROM_SIZE); } diff --git a/src/mainboard/emulation/qemu-q35/Kconfig b/src/mainboard/emulation/qemu-q35/Kconfig index 854c053..ed154b7 100644 --- a/src/mainboard/emulation/qemu-q35/Kconfig +++ b/src/mainboard/emulation/qemu-q35/Kconfig @@ -15,9 +15,8 @@ select MAINBOARD_FORCE_NATIVE_VGA_INIT if !CHROMEOS select MEMORY_MAPPED_TPM select MAINBOARD_HAS_CHROMEOS - select BOOT_DEVICE_NOT_SPI_FLASH select BOOT_DEVICE_MEMORY_MAPPED - select BOOT_DEVICE_SUPPORTS_WRITES + select DRIVERS_EMULATION_QEMU_BOOT_DEVICE select DRIVERS_EMULATION_QEMU_FW_CFG config VBOOT diff --git a/src/mainboard/emulation/qemu-q35/Makefile.mk b/src/mainboard/emulation/qemu-q35/Makefile.mk index fc85e64..285be9a 100644 --- a/src/mainboard/emulation/qemu-q35/Makefile.mk +++ b/src/mainboard/emulation/qemu-q35/Makefile.mk @@ -2,9 +2,11 @@ bootblock-y += bootblock.c bootblock-y += memmap.c +bootblock-y += ../qemu-i440fx/rom_media.c romstage-y += ../qemu-i440fx/memmap.c romstage-y += memmap.c +romstage-y += ../qemu-i440fx/rom_media.c postcar-y += ../qemu-i440fx/memmap.c postcar-y += ../qemu-i440fx/exit_car.S -- To view, visit https://review.coreboot.org/c/coreboot/+/85674?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iaee50b29d079564707e414bb92e949c306fb6ad3 Gerrit-Change-Number: 85674 Gerrit-PatchSet: 1 Gerrit-Owner: Carlos López <carlos.lopezr4096(a)gmail.com>

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coreboot-gerrit December 2024