coreboot-gerrit December 2024

coreboot-gerrit@coreboot.org

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[XS] Change in coreboot[main]: mb/topton/adl: Enable TPM2 (Intel fTPM/PTT)
by Matt DeVillier (Code Review) 20 Dec '24

20 Dec '24

Attention is currently required from: Alicja Michalska, Felix Singer. Matt DeVillier has posted comments on this change by Alicja Michalska. ( https://review.coreboot.org/c/coreboot/+/85611?usp=email ) Change subject: mb/topton/adl: Enable TPM2 (Intel fTPM/PTT) ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85611?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If1a52cacf2eeef68efdd98c48d5802712305f354 Gerrit-Change-Number: 85611 Gerrit-PatchSet: 3 Gerrit-Owner: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Comment-Date: Fri, 20 Dec 2024 00:23:28 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: mb/erying/tgl: Cleanup the code
by Alicja Michalska (Code Review) 19 Dec '24

19 Dec '24

Attention is currently required from: Felix Singer. Alicja Michalska has posted comments on this change by Alicja Michalska. ( https://review.coreboot.org/c/coreboot/+/85641?usp=email ) Change subject: mb/erying/tgl: Cleanup the code ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/85641/comment/2582df60_bbdf2d7c?us… : PS3, Line 11: - Moving SuperIO configuration to bootblock to make devtree cleaner > That is meant to be in the devicetree. I meant SIO GPIO. Angel did it the same way for Odroid H4+, looks much neater in my opinion. -- To view, visit https://review.coreboot.org/c/coreboot/+/85641?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9e395220025fc13e0589472e4732ea1495668554 Gerrit-Change-Number: 85641 Gerrit-PatchSet: 3 Gerrit-Owner: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Comment-Date: Thu, 19 Dec 2024 22:10:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <service+coreboot-gerrit(a)felixsinger.de>

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[XL] Change in coreboot[main]: soc/meidatek/mt8196: Add SPM loader
by Alicja Michalska (Code Review) 19 Dec '24

19 Dec '24

Attention is currently required from: Ccong Chen, Hung-Te Lin, Jarried Lin, Yidi Lin. Alicja Michalska has posted comments on this change by Ccong Chen. ( https://review.coreboot.org/c/coreboot/+/85599?usp=email ) Change subject: soc/meidatek/mt8196: Add SPM loader ...................................................................... Patch Set 8: (2 comments) File src/soc/mediatek/common/Kconfig: https://review.coreboot.org/c/coreboot/+/85599/comment/0e22cc76_520d3cff?us… : PS8, Line 122: version2 ```suggestion This option enables SPM Version 2. This version of the chip design ``` File src/soc/mediatek/mt8196/include/soc/spm.h: https://review.coreboot.org/c/coreboot/+/85599/comment/6df6eec8_17b9d14b?us… : PS8, Line 772: u32 isp_traw_pwr_con; Any reason to remove those? Will this SoC not support MIPI cameras? -- To view, visit https://review.coreboot.org/c/coreboot/+/85599?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie09346f46cb734c74776b760485e7f35d4357e5e Gerrit-Change-Number: 85599 Gerrit-PatchSet: 8 Gerrit-Owner: Ccong Chen <ot_ccong.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-CC: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-CC: Wenzhen Yu <wenzhen.yu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Ccong Chen <ot_ccong.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Thu, 19 Dec 2024 22:08:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[M] Change in coreboot[main]: Documentation: Add Erying Polestar G613 Pro
by Alicja Michalska (Code Review) 19 Dec '24

19 Dec '24

Attention is currently required from: Angel Pons, Felix Singer. Alicja Michalska has posted comments on this change by Alicja Michalska. ( https://review.coreboot.org/c/coreboot/+/81611?usp=email ) Change subject: Documentation: Add Erying Polestar G613 Pro ...................................................................... Patch Set 7: (1 comment) File Documentation/mainboard/erying/tgl/tgl_matx_board.jpg: PS6: > Yes please. Let's not merge representation images into the repo. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/81611?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5d60508dbde10373b0da2fb4ece0992760d3121c Gerrit-Change-Number: 81611 Gerrit-PatchSet: 7 Gerrit-Owner: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: coreboot org <coreboot.org(a)gmail.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Thu, 19 Dec 2024 21:57:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Comment-In-Reply-To: Alicja Michalska <ahplka19(a)gmail.com>

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[XS] Change in coreboot[main]: mb/asus/p8z77-m: Drop GPIO by I/O
by Felix Singer (Code Review) 19 Dec '24

19 Dec '24

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84617?usp=email ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/asus/p8z77-m: Drop GPIO by I/O ...................................................................... mb/asus/p8z77-m: Drop GPIO by I/O Per Fabian Groffen <grobian(a)gentoo.org> in CB:75145: This particular setting results in [ERROR] PNP: 002e.308 missing read_resources The underlying root cause was fixed by commit f5b993de4fcf (sio/nuvoton/nct6779d: Correct GPIOBASE virtual LDN). However, to make GPIO by I/O work requires setting up an I/O port resource here and a generic LPC I/O decode at southbridge/intel/bd82x6x, and both weren't done. Even if done, this newfound capability still doesn't offer much. Change-Id: I39739ab71bc644619667b3e123cc9ad85f9d109f Signed-off-by: Keith Hui <buurin(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84617 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: coreboot org <coreboot.org(a)gmail.com> --- M src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb 1 file changed, 0 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified coreboot org: Looks good to me, approved diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb index 9ff794b..50aed1b 100644 --- a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb +++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb @@ -77,7 +77,6 @@ drq 0xe6 = 0x7f # GP7x OD end device pnp 2e.9 off end # GPIO 8 - device pnp 2e.308 on end # GPIO by I/O device pnp 2e.109 on end # GPIO 1 device pnp 2e.209 on # GPIO 2 drq 0xe0 = 0xbf # GP26 output -- To view, visit https://review.coreboot.org/c/coreboot/+/84617?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I39739ab71bc644619667b3e123cc9ad85f9d109f Gerrit-Change-Number: 84617 Gerrit-PatchSet: 4 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: coreboot org <coreboot.org(a)gmail.com>

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[M] Change in coreboot[main]: Documentation: Add Topton N100 (X2F)
by Alicja Michalska (Code Review) 19 Dec '24

19 Dec '24

Alicja Michalska has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85680?usp=email ) Change subject: Documentation: Add Topton N100 (X2F) ...................................................................... Documentation: Add Topton N100 (X2F) Document the board and how to flash coreboot. Change-Id: Id585b064054b338ea8cead6edb6c5153030b9cde Signed-off-by: Alicja Michalska <alicja.michalska(a)9elements.com> --- M Documentation/mainboard/index.md A Documentation/mainboard/topton/adl/x2f-n100.jpg A Documentation/mainboard/topton/adl/x2f-n100.md 3 files changed, 90 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/85680/1 diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index cb28fa9..80e17ef 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -406,6 +406,13 @@ Beaglebone Black <ti/beaglebone-black.md> ``` +## Topton +```{toctree} +:maxdepth: 1 + +X2F-N100 <topton/adl/x2f-n100.md> +``` + ## UP ```{toctree} diff --git a/Documentation/mainboard/topton/adl/x2f-n100.jpg b/Documentation/mainboard/topton/adl/x2f-n100.jpg new file mode 100644 index 0000000..8ea7c1d --- /dev/null +++ b/Documentation/mainboard/topton/adl/x2f-n100.jpg Binary files differ diff --git a/Documentation/mainboard/topton/adl/x2f-n100.md b/Documentation/mainboard/topton/adl/x2f-n100.md new file mode 100644 index 0000000..d47b469 --- /dev/null +++ b/Documentation/mainboard/topton/adl/x2f-n100.md @@ -0,0 +1,83 @@ +# Topton N100 (X2F) Firewall Appliance + +This page describes how to run coreboot on the Topton X2F-N100. + +![](x2f-n100.jpg) + +```{eval-rst} ++-----------------+---------------------------------+----------------------+ +| Binary file | Apply | Required / Optional | ++=================+=================================+======================+ +| FSP-M & FSP-S | Intel Firmware Support Package | Required | ++-----------------+---------------------------------+----------------------+ +| me.bin | Intel Management Engine | Required (see notes) | ++-----------------+---------------------------------+----------------------+ +| descriptor.bin | Intel Flash Descriptor | Required (see notes) | ++-----------------+---------------------------------+----------------------+ +``` + +## Flashing coreboot + +WARNING: There are multiple devices from the same vendor with similar name, using different board layout, capabilities and EC/SuperIO. +Please refer to reference picture above to ensure that device you own is the same as supported by coreboot. +DO NOT attempt to flash this port on a different, "same-looking" device. Doing so *may* kill your device. +You have been warned :) + +### Internally +Vendor of this motherboard hasn't locked any flash regions, resulting in [flashprog] having full access to the SPI chip. +Assuming that user had booted Linux with `iomem=relaxed`, they can: +- Flash coreboot from stock firmware +- Flash stock firmware from coreboot +- Update coreboot build to a newer version +Without opening the case and connecting the SPI flasher. + +Please note that for AlderLake-N platform you will need to use [flashprog] v1.3.0 or newer. +[flashrom] is broken due to regressions, resulting in failed flashes and bricking the device. +[flashprog] is a better maintained fork of [flashrom], so it may change in the future. +For the time being, please use [flashprog] instead. + +You can skip extracting `SI_BIOS` and `SI_ME` regions from your ROM, and flash coreboot to `SI_BIOS` region by issuing the following command: +`flashprog -p internal --ifd -i SI_BIOS -w ./build/coreboot.rom` + +### Externally +SPI chip on this motherboard is located near the SoC, on the other side of the board (upper-right corner). +Please note that SPI voltage on this board is standard 3.3V, despite using mobile SoC and PCH. +Vendor populated this board with Winbond W25Q128JV chip in SOIC-8 package. + +## Functionality + +### Tested and working +- "Cisco-style" serial console in the front of the device (RS232 in COM form-factor). +- PC Speaker (goes beep-boop), controlled by ITE IT8625D. +- All USB ports +- All display ports +- All NIC ports (4x Intel I226-V 2.5GbE) +- M.2 NVME (PCIe x2 electrically) +- SATA port (there's only one, no SATA connectivity on M.2 slot) +- mPCIe WiFi/modem (needs an adapter from mPCIe to M.2 for modern wireless cards) +- mPCIe (USB) 4G modem +- PCIe passtrough (NICs to VMs, such as pfSense or OpenWrt using libvirt) +- Intel PTT (fTPM 2.0) + +- Payload: EDK2, LinuxBoot +- OS: Alpine Linux, Windows 11 + +### Untested or broken +- 5G modem on special M.2-like connector (lack hardware for it) +- Suspend in Windows 11 (might work, but Windows has been tested from USB drive). + +## Specification +```{eval-rst} ++-------+------------------------------+ +| SoC | Intel AlderLake N (IoT) | ++-------+------------------------------+ +| EC | ITE IT8625D | ++-------+------------------------------+ +| SPI | Winbond W25Q128 (16MiB 3.3V) | ++-------+------------------------------+ +| NIC | 4x Intel I226-V (2.5GbE) | ++-------+------------------------------+ +``` + +[flashprog]: https://flashprog.org/wiki/Flashprog +[flashrom]: https://flashrom.org/Flashrom -- To view, visit https://review.coreboot.org/c/coreboot/+/85680?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id585b064054b338ea8cead6edb6c5153030b9cde Gerrit-Change-Number: 85680 Gerrit-PatchSet: 1 Gerrit-Owner: Alicja Michalska <ahplka19(a)gmail.com>

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[M] Change in coreboot[main]: soc/intel/pantherlake: Add core scaling factors read support
by Jérémy Compostella (Code Review) 19 Dec '24

19 Dec '24

Attention is currently required from: Kapil Porwal, Pranava Y N, Subrata Banik. Hello Kapil Porwal, Pranava Y N, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85554?usp=email to look at the new patch set (#10). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/intel/pantherlake: Add core scaling factors read support ...................................................................... soc/intel/pantherlake: Add core scaling factors read support This commit adds support for reading core scaling factors via the PCODE mailbox interface. Starting with Lunar Lake, the scaling factor information is centralized in the power control unit (PCU) firmware. In order to keep all firmware in sync, it is recommended to read the scaling factors from the PCU firmware instead of using hard-coded values. The following changes were made: - Updated the Kconfig file to select SOC_INTEL_COMMON_BLOCK_RUNTIME_CORE_SCALING_FACTORS option - Modified the acpi.h header file to export the cpu_perf_eff_type enumeration for CPU performance/efficiency types. - Added a new function to the pantherlake systemagent.c file, soc_read_core_scaling_factors(), which reads the core scaling factors from the PCODE mailbox interface. The pcode READ_CORE_SCALING_FACTOR is presented in document 829201 Panther Lake Processor Mailbox Command. The performance impact on boot time is minimal. It took 12 us to read the scaling factors on a fatcat device. TEST=Successfully read performance and efficient scaling factors on a fatcat board. Change-Id: I7a8e1e66a02e4bf6b1a41277e83c6dec786fe169 Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> --- M src/soc/intel/common/block/acpi/cpu_hybrid.c M src/soc/intel/common/block/include/intelblocks/acpi.h M src/soc/intel/pantherlake/Kconfig M src/soc/intel/pantherlake/include/soc/systemagent.h M src/soc/intel/pantherlake/systemagent.c 5 files changed, 148 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/85554/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/85554?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7a8e1e66a02e4bf6b1a41277e83c6dec786fe169 Gerrit-Change-Number: 85554 Gerrit-PatchSet: 10 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>

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[M] Change in coreboot[main]: Documentation: Add Erying Polestar G613 Pro
by Alicja Michalska (Code Review) 19 Dec '24

19 Dec '24

Attention is currently required from: Alicja Michalska, Angel Pons. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81611?usp=email to look at the new patch set (#7). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: Documentation: Add Erying Polestar G613 Pro ...................................................................... Documentation: Add Erying Polestar G613 Pro Document the board and process of building/flashing coreboot on it. Change-Id: I5d60508dbde10373b0da2fb4ece0992760d3121c Signed-off-by: Alicja Michalska <ahplka19(a)gmail.com> --- A Documentation/mainboard/erying/tgl/tgl_matx.md M Documentation/mainboard/index.md 2 files changed, 174 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/81611/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/81611?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5d60508dbde10373b0da2fb4ece0992760d3121c Gerrit-Change-Number: 81611 Gerrit-PatchSet: 7 Gerrit-Owner: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: coreboot org <coreboot.org(a)gmail.com> Gerrit-Attention: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com>

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[XS] Change in coreboot[main]: mb/topton/adl: Enable TPM2 (Intel fTPM/PTT)
by Felix Singer (Code Review) 19 Dec '24

19 Dec '24

Attention is currently required from: Alicja Michalska. Felix Singer has posted comments on this change by Alicja Michalska. ( https://review.coreboot.org/c/coreboot/+/85611?usp=email ) Change subject: mb/topton/adl: Enable TPM2 (Intel fTPM/PTT) ...................................................................... Patch Set 3: Code-Review+2 (1 comment) Patchset: PS3: Cleaned up the commit message a bit. -- To view, visit https://review.coreboot.org/c/coreboot/+/85611?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If1a52cacf2eeef68efdd98c48d5802712305f354 Gerrit-Change-Number: 85611 Gerrit-PatchSet: 3 Gerrit-Owner: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Comment-Date: Thu, 19 Dec 2024 20:54:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/topton/adl: Enable TPM2 (Intel fTPM/PTT)
by Felix Singer (Code Review) 19 Dec '24

19 Dec '24

Felix Singer has uploaded a new patch set (#3) to the change originally created by Alicja Michalska. ( https://review.coreboot.org/c/coreboot/+/85611?usp=email ) Change subject: mb/topton/adl: Enable TPM2 (Intel fTPM/PTT) ...................................................................... mb/topton/adl: Enable TPM2 (Intel fTPM/PTT) Change-Id: If1a52cacf2eeef68efdd98c48d5802712305f354 Signed-off-by: Alicja Michalska <alicja.michalska(a)9elements.com> --- M src/mainboard/topton/adl/Kconfig M src/mainboard/topton/adl/devicetree.cb 2 files changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/85611/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/85611?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If1a52cacf2eeef68efdd98c48d5802712305f354 Gerrit-Change-Number: 85611 Gerrit-PatchSet: 3 Gerrit-Owner: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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coreboot-gerrit December 2024