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Change subject: 3rdparty/fsp: Update submodule to upstream master
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Patch Set 1: Code-Review+2
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Change subject: added bare Asrock H370m-ITX support
......................................................................
Patch Set 6:
(1 comment)
Patchset:
PS6:
> I would start with rebasing on the main branch, so that we don't try to debug a very old state. […]
Moved the patch over to the main branch. You still need to rebase it yourself.
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Change subject: added bare Asrock H370m-ITX support
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Patch Set 6:
(6 comments)
Patchset:
PS6:
> hi, i want to continue work on this PR. but i want fix some problems: […]
I would start with rebasing on the main branch, so that we don't try to debug a very old state. See my other comments.
File src/mainboard/asrock/h370m/Makefile.inc:
PS6:
Please rename this file to `Makefile.mk`
File src/mainboard/asrock/h370m/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/65225/comment/9b455aeb_3a2d2639?us… :
PS6, Line 3: device cpu_cluster 0 on
: device lapic 0 on end
: end
Not needed anymore.
https://review.coreboot.org/c/coreboot/+/65225/comment/1e540451_648d4d9f?us… :
PS6, Line 8: register "RMT" = "0"
Set to 0 by default, remove.
https://review.coreboot.org/c/coreboot/+/65225/comment/d5ba09e3_d06bcdf0?us… :
PS6, Line 14: device domain 0 on
Please have a look in `src/soc/intel/cannonlake/chipset_pch_h.cb` and use the alias names instead of like `pci 00.0`. There are many other mainboards in the tree using them. So you have some examples.
Also, remove PCI devices which have an equivalent configuration in the chipset device tree and remove devices which are turned off anyway.
File src/mainboard/asrock/h370m/ramstage.c:
https://review.coreboot.org/c/coreboot/+/65225/comment/d2169185_9ca58d8b?us… :
PS6, Line 12: gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
We don't do the GPIO configuration before the FSP-S runs. In some cases, FSP did GPIO configuration itself. So in order to be sure only our configuration is used, we do the configuration after FSP-S.
Please have a look into `src/mainboard/kontron/bsl6/ramstage.c` and use that way. You can do that in this file, but just move the configuration into the chip_operations driver as shown in the other mainboard.
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Change subject: added bare Asrock H370m-ITX support
......................................................................
Patch Set 6:
(1 comment)
Patchset:
PS6:
hi, i want to continue work on this PR. but i want fix some problems:
1) the m.2 slot wont recognize sata ssds
2) sleep states aren't working
does anyone has any advice? what i have tried:
1) played arround with the gpio.c. there i only can activate sata OR pcie not both.
2) played arround with devicetree.cb:
* gpeX_dw0
* s0ix_enable
* genX_dec
* superio foo
regarding the superio investigation i found out that the default values for the Nuvoton NCT5539D are wrong inside the `superio` tool.
i would appreciate any help or advice on where I could find help.
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Change subject: added bare Asrock H370m-ITX support
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Restored
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Change subject: Update fsp submodule to upstream master
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Abandoned
Superseded by CB:84986
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Change subject: util/crossgcc: Add libstdcxx target
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Patch Set 5:
(1 comment)
Patchset:
PS5:
> Where and how is that used?
it's used by chromeos to build code for the EC/ISH on new platforms. We're building picolibc from the zephyr repo, and libstdc++ here
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Change subject: util/crossgcc: Add libstdcxx target
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Patch Set 5:
(1 comment)
Patchset:
PS5:
Where and how is that used?
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