coreboot-gerrit November 2024

coreboot-gerrit@coreboot.org

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[L] Change in coreboot[main]: mb/google/fatcat/var/felino: Add initial GPIOs config
by Paul Menzel (Code Review) 21 Nov '24

21 Nov '24

Attention is currently required from: Pranava Y N, Subrata Banik, Tongtong Pan, Weimin Wu. Paul Menzel has posted comments on this change by Tongtong Pan. ( https://review.coreboot.org/c/coreboot/+/85234?usp=email ) Change subject: mb/google/fatcat/var/felino: Add initial GPIOs config ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/85234/comment/a97f3a8f_cff3e69f?us… : PS1, Line 9: schematics revision Please mention the file name. -- To view, visit https://review.coreboot.org/c/coreboot/+/85234?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4e9e81af9c3d8807e65ecd552e73305c1d109a2d Gerrit-Change-Number: 85234 Gerrit-PatchSet: 1 Gerrit-Owner: Tongtong Pan <pantongtong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Attention: Tongtong Pan <pantongtong(a)huaqin.corp-partner.google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Thu, 21 Nov 2024 13:15:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[M] Change in coreboot[main]: soc/mediatek/mt8196: Add MMinfra driver support
by Yu-Ping Wu (Code Review) 21 Nov '24

21 Nov '24

Attention is currently required from: Hung-Te Lin, Jarried Lin, Paul Menzel, Yidi Lin. Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85188?usp=email ) Change subject: soc/mediatek/mt8196: Add MMinfra driver support ...................................................................... Patch Set 5: (1 comment) File src/soc/mediatek/mt8196/mminfra_pd.c: https://review.coreboot.org/c/coreboot/+/85188/comment/fc3c1d12_ce096ea5?us… : PS5, Line 35: while (read32p(MMINFRA_MM0_GALS_PROT_TX_RDY) != 0xff) : ; > Done I agree with Paul. With a timeout or retry limit, we can print an error log. If you don't want the boot to continue, you could use "die". -- To view, visit https://review.coreboot.org/c/coreboot/+/85188?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie86f141a0957fc60d4973875c0dbcbdb57be1f75 Gerrit-Change-Number: 85188 Gerrit-PatchSet: 5 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Thu, 21 Nov 2024 12:59:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Jarried Lin <jarried.lin(a)mediatek.com>

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[L] Change in coreboot[main]: mb/google/fatcat/var/felino: Add initial GPIOs config
by Tongtong Pan (Code Review) 21 Nov '24

21 Nov '24

Tongtong Pan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85234?usp=email ) Change subject: mb/google/fatcat/var/felino: Add initial GPIOs config ...................................................................... mb/google/fatcat/var/felino: Add initial GPIOs config Configure GPIOs according to schematics revision. BUG=b:379797598 TEST=abuild -v -a -x -c max -p none -t google/fatcat -b felino Change-Id: I4e9e81af9c3d8807e65ecd552e73305c1d109a2d Signed-off-by: Tongtong Pan <pantongtong(a)huaqin.corp-partner.google.com> --- A src/mainboard/google/fatcat/variants/felino/Makefile.mk M src/mainboard/google/fatcat/variants/felino/gpio.c 2 files changed, 245 insertions(+), 241 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/85234/1 diff --git a/src/mainboard/google/fatcat/variants/felino/Makefile.mk b/src/mainboard/google/fatcat/variants/felino/Makefile.mk new file mode 100644 index 0000000..cbe8155 --- /dev/null +++ b/src/mainboard/google/fatcat/variants/felino/Makefile.mk @@ -0,0 +1,7 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += gpio.c +romstage-y += gpio.c +romstage-y += memory.c +ramstage-y += gpio.c +ramstage-$(CONFIG_FW_CONFIG) += variant.c diff --git a/src/mainboard/google/fatcat/variants/felino/gpio.c b/src/mainboard/google/fatcat/variants/felino/gpio.c index 7833fe8..645746f 100644 --- a/src/mainboard/google/fatcat/variants/felino/gpio.c +++ b/src/mainboard/google/fatcat/variants/felino/gpio.c @@ -28,233 +28,230 @@ /* GPP_A06: ESPI_RST_EC_R_N */ /* GPP_A06 : GPP_A06 ==> ESPI_RST_HDR configured on reset, do not touch */ - /* GPP_A08: X1_PCIE_SLOT_PWR_EN */ + /* GPP_A08: MIPI_RGB_XSHUTDN */ PAD_CFG_GPO(GPP_A08, 1, PLTRST), - /* GPP_A09: M.2_WWAN_FCP_OFF_N */ + /* GPP_A09: MIPI_RGB_OSC_EN */ PAD_CFG_GPO(GPP_A09, 1, PLTRST), - /* GPP_A10: M.2_WWAN_DISABLE_N */ + /* GPP_A10: WWAN_RF_DISABLE_ODL */ PAD_CFG_GPO(GPP_A10, 1, PLTRST), - /* GPP_A11: WLAN_RST_N */ + /* GPP_A11: WLAN_SOC_RST_N */ PAD_CFG_GPO(GPP_A11, 1, PLTRST), - /* GPP_A12: WIFI_WAKE_N */ + /* GPP_A12: WAKE_PCIE_N_SOC */ PAD_CFG_GPI_SCI_LOW(GPP_A12, NONE, DEEP, LEVEL), /* GPP_A13: Not used */ PAD_NC(GPP_A13, NONE), - /* GPP_A15: GPP_A15_DNX_FORCE_RELOAD */ + /* GPP_A15: HW_ID1 */ PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), /* GPP_A16: BT_RF_KILL_N */ PAD_CFG_GPO(GPP_A16, 1, DEEP), - /* GPP_A17: WIFI_RF_KILL_N */ + /* GPP_A17: PCH_WLAN_OFF_N */ PAD_CFG_GPO(GPP_A17, 1, DEEP), - /* GPP_B00: USBC_SML_CLK_PD */ + /* GPP_B00: TYPEC_PD_SOC_CLK */ PAD_CFG_NF(GPP_B00, NONE, DEEP, NF1), - /* GPP_B01: USBC_SML_DATA_PD */ + /* GPP_B01: TYPEC_PD_SOC_DAT */ PAD_CFG_NF(GPP_B01, NONE, DEEP, NF1), - /* GPP_B02: ISH_I2C0_SDA_SNSR_HDR */ - /* NOTE: IOSSTAGE: 'Ignore' for S0ix */ + /* GPP_B02: I2C_SDA_E3_SOC */ PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B02, NONE, DEEP, NF3), - /* GPP_B03: ISH_I2C0_SCL_SNSR_HDR */ - /* NOTE: IOSSTAGE: 'Ignore' for S0ix */ + /* GPP_B03: I2C_SCL_E3_SOC */ PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B03, NONE, DEEP, NF3), - /* GPP_B04: ISH_GP_0_SNSR_HDR */ - PAD_CFG_NF(GPP_B04, NONE, DEEP, NF4), - /* GPP_B05: ISH_GP_1_SNSR_HDR */ + /* GPP_B04: NC */ + PAD_NC(GPP_B04, NONE), + /* GPP_B05: MIPI_IR_LED_PWM */ PAD_CFG_NF(GPP_B05, NONE, DEEP, NF4), - /* GPP_B06: ISH_GP_2_SNSR_HDR */ - PAD_CFG_NF(GPP_B06, NONE, DEEP, NF4), - /* GPP_B07: ISH_GP_3_SNSR_HDR */ - PAD_CFG_NF(GPP_B07, NONE, DEEP, NF4), - /* GPP_B08: ISH_GP_4_SNSR_HDR */ - PAD_CFG_NF(GPP_B08, NONE, DEEP, NF4), - /* GPP_B09: M2_GEN4_SSD_RESET_N */ - PAD_CFG_GPO(GPP_B09, 1, PLTRST), - /* GPP_B10: GEN4_SSD_PWREN */ - PAD_CFG_GPO(GPP_B10, 1, PLTRST), - /* GPP_B11: MOD_TCSS1_DISP_HPD3 */ - PAD_CFG_NF(GPP_B11, NONE, DEEP, NF2), - /* GPP_B12: PM_SLP_S0_N */ + /* GPP_B06: NC */ + PAD_NC(GPP_B06, NONE), + /* GPP_B07: NC */ + PAD_NC(GPP_B07, NONE), + /* GPP_B08: NC */ + PAD_NC(GPP_B08, NONE), + /* GPP_B09: NC */ + PAD_NC(GPP_B09, NONE), + /* GPP_B10: SOC_DP1_HDMI_HPD */ + PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), + /* GPP_B11: PD1_OC_P0_P1_N */ + PAD_NC(GPP_B11, NONE), + /* GPP_B12: SLP_S0_SOC_N */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* GPP_B13: PLT_RST_N */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), - /* GPP_B14: MOD_TCSS2_DISP_HPD4 */ - PAD_CFG_NF(GPP_B14, NONE, DEEP, NF2), - /* GPP_B15: MOD_TCSS_USB_TYP_A_OC3_N */ + /* GPP_B14: NC */ + PAD_NC(GPP_B14, NONE), + /* GPP_B15: USB_A_OC3_L */ PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), - /* GPP_B16: GEN5_SSD_PWREN */ - PAD_CFG_GPO(GPP_B16, 1, PLTRST), - /* GPP_B17: Not used */ + /* GPP_B16: NC */ + PAD_NC(GPP_B16, NONE), + /* GPP_B17: NC */ PAD_NC(GPP_B17, NONE), - /* GPP_B18: ISH_I2C2_SDA_SNSR_HDR */ - /* NOTE: IOSSTAGE: 'Ignore' for S0ix */ + /* GPP_B18: ISH_I2C_EC_SDA */ PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B18, NONE, DEEP, NF1), - /* GPP_B19: ISH_I2C2_SCL_SNSR_HDR */ - /* NOTE: IOSSTAGE: 'Ignore' for S0ix */ + /* GPP_B19: ISH_I2C_EC_SCL */ PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B19, NONE, DEEP, NF1), - /* GPP_B20: M.2_WWAN_RST_N */ + /* GPP_B20: I2C2_SOC_SDA */ PAD_CFG_GPO(GPP_B20, 1, PLTRST), - /* GPP_B21: TCP_RETIMER_FORCE_PWR */ + /* GPP_B21: I2C2_SOC_SCL */ PAD_CFG_GPO(GPP_B21, 0, DEEP), - /* GPP_B22: ISH_GP_5_SNSR_HDR */ + /* GPP_B22: Cable_INT_N */ PAD_CFG_NF(GPP_B22, NONE, DEEP, NF4), - /* GPP_B23: ISH_GP_6_SNSR_HDR */ + /* GPP_B23: HW_ID0 */ PAD_CFG_NF(GPP_B23, NONE, DEEP, NF4), - /* GPP_B24: ESPI_ALERT0_EC_R_N */ + /* GPP_B24: ESPI_ALERT0_N */ PAD_NC(GPP_B24, NONE), - /* GPP_B25: X1_SLOT_WAKE_N */ + /* GPP_B25: MIPI_RGB_LDO_EN */ PAD_CFG_GPI_SCI_LOW(GPP_B25, NONE, DEEP, LEVEL), - /* GPP_C00: GPP_C0_SMBCLK */ - PAD_CFG_NF(GPP_C00, NONE, DEEP, NF1), - /* GPP_C01: GPP_C1_SMBDATA */ - PAD_CFG_NF(GPP_C01, NONE, DEEP, NF1), - /* GPP_C02: Not used */ - PAD_NC(GPP_C02, NONE), - /* GPP_C03: TCP_LAN_SML0_SCL_R */ + /* GPP_C00: NC */ + PAD_NC(GPP_C00, NONE), + /* GPP_C01: NC */ + PAD_NC(GPP_C01, NONE), + /* GPP_C02: GPPC_C2_SMB_ALERT_N */ + PAD_CFG_NF(GPP_C02, NONE, DEEP, NF1), + /* GPP_C03: SMBUS_CLK0 */ PAD_CFG_NF(GPP_C03, NONE, DEEP, NF1), - /* GPP_C04: TCP_LAN_SML0_SDA_R */ + /* GPP_C04: SMBUS_DAT0 */ PAD_CFG_NF(GPP_C04, NONE, DEEP, NF1), - /* GPP_C05: CRD1_PWREN */ - PAD_CFG_GPO(GPP_C05, 1, PLTRST), - /* GPP_C06: SML1_CLK */ - PAD_CFG_NF(GPP_C06, NONE, DEEP, NF1), - /* GPP_C07: SML1_DATA */ - PAD_CFG_NF(GPP_C07, NONE, DEEP, NF1), - /* GPP_C08: CRD2_PWREN */ + /* GPP_C05: GPPC_C5 */ + PAD_NC(GPP_C05, NONE), + /* GPP_C06: NC */ + PAD_NC(GPP_C06, NONE), + /* GPP_C07: NC */ + PAD_NC(GPP_C07, NONE), + /* GPP_C08: PCH_WP_OD */ PAD_CFG_GPO(GPP_C08, 1, PLTRST), - /* GPP_C09: CLKREQ0_X8_GEN5_DT_CEM_SLOT_N */ + /* GPP_C09: PCIE_CLKREQ_SSD1_N */ PAD_CFG_NF(GPP_C09, NONE, DEEP, NF1), - /* GPP_C10: CLKREQ1_X4_GEN5_M2_SSD_N */ - PAD_CFG_NF(GPP_C10, NONE, DEEP, NF1), - /* GPP_C11: CLKREQ2_X1_GEN4_DT_CEM_SLOT_N */ - PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1), - /* GPP_C12: CLKREQ3_X1_GEN1_GBE_LAN_N */ - PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), - /* GPP_C13: CLKREQ4_X1_GEN4_M2_WLAN_N */ + /* GPP_C10: NC */ + PAD_NC(GPP_C10, NONE), + /* GPP_C11: NC */ + PAD_NC(GPP_C11, NONE), + /* GPP_C12: NC */ + PAD_NC(GPP_C12, NONE), + /* GPP_C13: PCIE_CLKREQ_WLAN_N */ PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), - /* GPP_C14: CLKREQ5_X1_GEN4_M2_WWAN_N */ - PAD_CFG_NF(GPP_C14, NONE, DEEP, NF1), - /* GPP_C15: CRD1_CLK_EN */ + /* GPP_C14: NC */ + PAD_NC(GPP_C14, NONE), + /* GPP_C15: GPP_C15 */ PAD_CFG_GPO(GPP_C15, 1, PLTRST), - /* GPP_C16: TBT_LSX0_TXD */ - PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), - /* GPP_C17: TBT_LSX0_RXD */ - PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), - /* GPP_C18: TBT_LSX1_TXD */ + /* GPP_C16: NC */ + PAD_NC(GPP_C16, NONE), + /* GPP_C17: NC */ + PAD_NC(GPP_C17, NONE), + /* GPP_C18: TCP3_DDC_SCL */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), - /* GPP_C19: TBT_LSX1_RXD */ + /* GPP_C19: TCP3_DDC_SDA */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), - /* GPP_C20: MOD_TCSS1_LS_TX_DDC_SCL */ + /* GPP_C20: TBT_LSX1_TXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), - /* GPP_C21: MOD_TCSS1_LS_RX_DDC_SDA */ + /* GPP_C21: TBT_LSX1_RXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), - /* GPP_C22: MOD_TCSS2_LS_TX_DDC_SCL */ - PAD_CFG_NF(GPP_C22, NONE, DEEP, NF2), - /* GPP_C23: MOD_TCSS2_LS_RX_DDC_SDA */ - PAD_CFG_NF(GPP_C23, NONE, DEEP, NF2), + /* GPP_C22: TBT_LSX0_TXD */ + PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1), + /* GPP_C23: TBT_LSX0_RXD */ + PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1), - /* GPP_D00: IMGCLKOUT_1 */ + /* GPP_D00: MIPI_RGB_IR_MCLK */ PAD_CFG_NF(GPP_D00, NONE, DEEP, NF1), - /* GPP_D01: MOD_TCSS1_TYP_A_VBUS_EN */ - PAD_CFG_GPO(GPP_D01, 1, DEEP), - /* GPP_D02: Not used */ - PAD_NC(GPP_D02, NONE), - /* GPP_D03: M.2_WWAN_PERST_GPIO_N */ + /* GPP_D01: ALS_I2C_SDA */ + PAD_CFG_NF(GPP_D01, NONE, DEEP, NF3), + /* GPP_D02: ALS_I2C_SCL */ + PAD_CFG_NF(GPP_D02, NONE, DEEP, NF3), + /* GPP_D03: SLP_S0_GATE_R */ PAD_CFG_GPO(GPP_D03, 1, PLTRST), - /* GPP_D04: IMGCLKOUT_0 */ + /* GPP_D04: MIPI_RGB_MCLK */ PAD_CFG_NF(GPP_D04, NONE, DEEP, NF1), - /* GPP_D07: NC */ - PAD_NC(GPP_D07, NONE), + /* GPP_D05: UART0_ISH_RX_DBG_TX_U */ + PAD_CFG_NF(GPP_D05, NONE, DEEP, NF1), + /* GPP_D06: UART0_ISH_TX_DBG_RX_U */ + PAD_CFG_NF(GPP_D06, NONE, DEEP, NF1), + /* GPP_D07: CAM_VDD_EN_SOC */ + PAD_CFG_GPO(GPP_D07, 1, PLTRST), /* GPP_D08: NC */ PAD_NC(GPP_D08, NONE), - /* GPP_D09: PEG_SLOT_RST_N */ + /* GPP_D09: USB_MUX_SEL */ PAD_CFG_GPO(GPP_D09, 1, PLTRST), - /* GPP_D10: HDA_BCLK */ + /* GPP_D10: PMC_WLAN_CLK */ PAD_CFG_NF(GPP_D10, NONE, DEEP, NF1), - /* GPP_D11: HDA_SYNC */ + /* GPP_D11: CNV_PCM_SYNC */ PAD_CFG_NF(GPP_D11, NONE, DEEP, NF1), - /* GPP_D12: HDA_SDO */ + /* GPP_D12: PMC_SOC_OUT */ PAD_CFG_NF(GPP_D12, NONE, DEEP, NF1), - /* GPP_D13: HDA_SDI0 */ + /* GPP_D13: PMC_SOC_IN */ PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1), - /* GPP_D14: COINLESS_MODE_SELECT */ - PAD_CFG_GPI_TRIG_OWN(GPP_D14, NONE, PLTRST, LEVEL, ACPI), - /* GPP_D15: SPI_TPM_INT_N */ - PAD_CFG_GPI_APIC_LOCK(GPP_D15, NONE, LEVEL, INVERT, LOCK_CONFIG), - /* GPP_D16: HDA_RST_N_HDR */ - PAD_CFG_NF(GPP_D16, NONE, DEEP, NF1), - /* GPP_D17: HDA_SDI1_HDR */ - PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), - /* GPP_D18: CLKREQ6_X4_GEN4_M2_SSD_N */ + /* GPP_D14: NC */ + PAD_NC(GPP_D14, NONE), + /* GPP_D15: NC */ + PAD_NC(GPP_D15, NONE), + /* GPP_D16: PCH_DMIC_CLK1 */ + PAD_CFG_NF(GPP_D16, NONE, DEEP, NF2), + /* GPP_D17: PCH_DMIC_DATA1 */ + PAD_CFG_NF(GPP_D17, NONE, DEEP, NF2), + /* GPP_D18: PCIE_CLKREQ_SD_N */ PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), - /* GPP_D19: X1_DT_PCIE_RST_N */ - PAD_CFG_GPO(GPP_D19, 1, PLTRST), - /* GPP_D20: CSE_EARLY_SW */ - PAD_CFG_GPI_SCI_HIGH(GPP_D20, NONE, DEEP, LEVEL), - /* GPP_D21: GPP_D21_UFS_REFCLK */ - PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1), - /* GPP_D22: BPKI3C_SDA */ + /* GPP_D19: NC */ + PAD_NC(GPP_D19, NONE), + /* GPP_D20: NC */ + PAD_NC(GPP_D20, NONE), + /* GPP_D21: NC */ + PAD_NC(GPP_D21, NONE), + /* GPP_D22: DG_I3C_SDA */ PAD_CFG_NF(GPP_D22, NONE, DEEP, NF1), - /* GPP_D23: BPKI3C_SCL */ + /* GPP_D23: DG_I3C_SCL */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), - /* GPP_D24: PEG_SLOT_WAKE_N */ + /* GPP_D24: MIPI_IR_LDO_EN */ PAD_CFG_GPI_SCI_LOW(GPP_D24, NONE, DEEP, LEVEL), - /* GPP_D25: X4_SLOT_WAKE_N */ + /* GPP_D25: MIPI_IR_OSC_EN */ PAD_CFG_GPI_SCI_LOW(GPP_D25, NONE, DEEP, LEVEL), - /* GPP_E01: CRD2_RST_N */ - PAD_CFG_GPO(GPP_E01, 1, PLTRST), - /* GPP_E02: WWAN_WAKE_GPIO_N */ - PAD_CFG_GPI_SCI_LOW(GPP_E02, NONE, DEEP, LEVEL), - /* GPP_E03: M2_GEN5_SSD_RESET_N */ - PAD_CFG_GPO(GPP_E03, 1, PLTRST), - /* GPP_E06: SECURE_CAM_SW */ + /* GPP_E01: SLOW_R */ + PAD_CFG_GPI(GPP_E01, NONE, PLTRST), + /* GPP_E02: NC */ + PAD_NC(GPP_E02, NONE), + /* GPP_E03: NC */ + PAD_NC(GPP_E03, NONE), + /* GPP_E05: NC */ + PAD_NC(GPP_E05, NONE), + /* GPP_E06: GPP_E06 */ PAD_CFG_GPI_TRIG_OWN(GPP_E06, NONE, PLTRST, LEVEL, ACPI), - /* GPP_E07: Not used */ + /* GPP_E07: NC */ PAD_NC(GPP_E07, NONE), - /* GPP_E08: Not used */ + /* GPP_E08: NC */ PAD_NC(GPP_E08, NONE), - /* GPP_E09: USB_RD_FP_CONN_12_OC0_N */ - PAD_CFG_NF(GPP_E09, NONE, DEEP, NF1), - /* GPP_E10: CRD1_RST_N */ - PAD_CFG_GPO(GPP_E10, 1, PLTRST), - /* GPP_E11: THC0_SPI1_CLK_TCH_PNL1 */ - PAD_CFG_NF(GPP_E11, NONE, DEEP, NF3), - /* GPP_E12: THC0_SPI1_IO_0_I2C4_SCL_TCH_PNL1 */ - PAD_CFG_NF(GPP_E12, NONE, DEEP, NF3), - /* GPP_E13: THC0_SPI1_IO_1_I2C4_SDA_TCH_PNL1 */ - PAD_CFG_NF(GPP_E13, NONE, DEEP, NF3), - /* GPP_E14: THC0_SPI1_IO_2_TCH_PNL1 */ - PAD_CFG_NF(GPP_E14, NONE, DEEP, NF3), - /* GPP_E15: THC0_SPI1_IO_3_TCH_PNL1 */ - PAD_CFG_NF(GPP_E15, NONE, DEEP, NF3), - /* GPP_E16: THC0_SPI1_RST_N_TCH_PNL1 */ - /* THC NOTE: use GPO instead of GPO for THC0 Rst */ - PAD_CFG_GPO(GPP_E16, 1, DEEP), - /* GPP_E17: THC0_SPI1_CS0_N_TCH_PNL1 */ - PAD_CFG_NF(GPP_E17, NONE, DEEP, NF3), - /* GPP_E18: THC0_SPI1_INT_N_TCH_PNL1 */ + /* GPP_E09: NC */ + PAD_NC(GPP_E09, NONE), + /* GPP_E10: NC */ + PAD_NC(GPP_E10, NONE), + /* GPP_E11: NC */ + PAD_NC(GPP_E11, NONE), + /* GPP_E12: I2C0_SOC_SCL */ + PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), + /* GPP_E13: I2C0_SOC_SDA */ + PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), + /* GPP_E14: NC */ + PAD_NC(GPP_E14, NONE), + /* GPP_E15: NC */ + PAD_NC(GPP_E15, NONE), + /* GPP_E16: NC */ + PAD_NC(GPP_E16, NONE), + /* GPP_E17: NC */ + PAD_NC(GPP_E17, NONE), + /* GPP_E18: TOUCHPAD_INT_N */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF3), - /* GPP_E19: PEG_SLOT_DGPU_SEL_N */ + /* GPP_E19: HW_ID5 */ PAD_CFG_GPO(GPP_E19, 1, PLTRST), - /* GPP_E20: PEG_SLOT_DGPU_PWR_OK */ - PAD_CFG_GPI(GPP_E20, NONE, PLTRST), - /* GPP_E21: I2C_PMC_PD_INT_N */ + /* GPP_E20: HW_ID4 */ + PAD_CFG_GPO(GPP_E20, 1, PLTRST), + /* GPP_E21: TYPEC_PD_SOC_INT */ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), - /* GPP_E22: THC0_SPI1_DSYNC */ + /* GPP_E22: MIPI_IR_XSHUTDN */ PAD_CFG_NF(GPP_E22, NONE, DEEP, NF3), - /* GPP_F00: M.2_CNV_BRI_DT_BT_UART2_RTS_N */ - /* NOTE: IOSSTAGE: 'Ignore' for S0ix */ + /* GPP_F00: CNV_BRI_DT */ PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F00, NONE, DEEP, NF1), - /* GPP_F01: M.2_CNV_BRI_RSP_BT_UART2_RXD */ - /* NOTE: IOSSTAGE: 'Ignore' for S0ix */ + /* GPP_F01: CNV_BRI_RSP_SOC */ PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F01, NONE, DEEP, NF1), - /* GPP_F02: M.2_CNV_RGI_DT_BT_UART2_TXD */ - /* NOTE: IOSSTAGE: 'Ignore' for S0ix */ + /* GPP_F02: CNV_RGI_DT */ PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F02, NONE, DEEP, NF1), - /* GPP_F03: M.2_CNV_RGI_RSP_BT_UART2_CTS_N */ - /* NOTE: IOSSTAGE: 'Ignore' for S0ix */ + /* GPP_F03: CNV_RGI_RSP_SOC */ PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F03, NONE, DEEP, NF1), /* GPP_F04: CNV_RF_RESET_R_N */ /* NOTE: IOSSTAGE: 'Ignore' for S0ix */ @@ -262,82 +259,82 @@ /* GPP_F05: CRF_CLKREQ_R */ /* NOTE: IOSSTAGE: 'Ignore' for S0ix */ PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F05, NONE, DEEP, NF3), - /* GPP_F06: WLAN_WWAN_COEX3 */ - PAD_CFG_NF(GPP_F06, NONE, DEEP, NF1), - /* GPP_F07: IMGCLKOUT_2 */ - PAD_CFG_NF(GPP_F07, NONE, DEEP, NF2), - /* GPP_F08: TCH_PNL1_PWR_EN */ - PAD_CFG_GPO(GPP_F08, 1, PLTRST), + /* GPP_F06: NC */ + PAD_NC(GPP_F06, NONE), + /* GPP_F07: NC */ + PAD_NC(GPP_F07, NONE), + /* GPP_F08: NC */ + PAD_NC(GPP_F08, NONE), /* GPP_F09: NC */ PAD_NC(GPP_F09, NONE), - /* GPP_F10: PEG_SLOT_PWR_EN_N */ + /* GPP_F10: HW_ID7 */ PAD_CFG_GPO(GPP_F10, 0, PLTRST), - /* GPP_F11: MOD_TCSS2_TYP_A_VBUS_EN */ + /* GPP_F11: TC_RETIMER_FORCE_PWR */ PAD_CFG_GPO(GPP_F11, 1, DEEP), - /* GPP_F12: THC_I2C1_SCL_TCH_PAD */ - PAD_CFG_NF(GPP_F12, NONE, DEEP, NF8), - /* GPP_F13: THC_I2C1_SDA_TCH_PAD */ - PAD_CFG_NF(GPP_F13, NONE, DEEP, NF8), - /* GPP_F14: Not used */ + /* GPP_F12: NC */ + PAD_NC(GPP_F12, NONE), + /* GPP_F13: NC */ + PAD_NC(GPP_F13, NONE), + /* GPP_F14: NC */ PAD_NC(GPP_F14, NONE), - /* GPP_F15: Not used */ - PAD_NC(GPP_F15, NONE), - /* GPP_F16: Not used */ + /* GPP_F15: GSC_PCH_INT_ODL */ + PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), + /* GPP_F16: NC */ PAD_NC(GPP_F16, NONE), - /* GPP_F17: Not used */ - PAD_CFG_GPI_INT(GPP_F17, NONE, PLTRST, EDGE_BOTH), - /* GPP_F18: TCH_PAD_INT_N */ - PAD_CFG_GPI_APIC(GPP_F18, NONE, PLTRST, EDGE_SINGLE, INVERT), - /* GPP_F19: GPP_PRIVACY_LED_CAM2 */ + /* GPP_F17: NC */ + PAD_NC(GPP_F17, NONE), + /* GPP_F18: NC */ + PAD_NC(GPP_F18, NONE), + /* GPP_F19: GPP_F19 */ PAD_CFG_GPO(GPP_F19, 0, PLTRST), - /* GPP_F20: GPP_PRIVACY_LED_CAM1_CVS_HST_WAKE */ - PAD_CFG_GPO(GPP_F20, 0, PLTRST), - /* GPP_F22: THC1_SPI2_DSYNC */ - PAD_CFG_NF(GPP_F22, NONE, DEEP, NF3), - /* GPP_F23: SMC_LID */ - PAD_CFG_GPI_SCI_LOW(GPP_F23, NONE, DEEP, LEVEL), + /* GPP_F20: NC */ + PAD_NC(GPP_F20, NONE), + /* GPP_F22: NC */ + PAD_NC(GPP_F22, NONE), + /* GPP_F23: NC */ + PAD_NC(GPP_F23, NONE), - /* GPP_H00: Not used */ + /* GPP_H00: GPP_H00 */ PAD_NC(GPP_H00, NONE), - /* GPP_H01: CRD_CAM_STROBE */ - PAD_CFG_GPO(GPP_H01, 0, PLTRST), - /* GPP_H02: DEBUG_TRACE_PNP */ - PAD_CFG_GPO(GPP_H02, 1, PLTRST), - /* GPP_H03: MIC MUTE */ - PAD_CFG_NF(GPP_H03, NONE, DEEP, NF1), - /* GPP_H04: I2C2_SDA_CAM_FLSH */ + /* GPP_H01: GPP_H01 */ + PAD_NC(GPP_H01, NONE), + /* GPP_H02: GPP_H02 */ + PAD_NC(GPP_H02, NONE), + /* GPP_H03: NC */ + PAD_NC(GPP_H03, NONE), + /* GPP_H04: MIPI_IR_SDA */ PAD_CFG_NF(GPP_H04, NONE, DEEP, NF1), - /* GPP_H05: I2C2_SCL_CAM_FLSH */ + /* GPP_H05: MIPI_IR_SCL */ PAD_CFG_NF(GPP_H05, NONE, DEEP, NF1), - /* GPP_H06: I2C3_SDA_PSS */ + /* GPP_H06: CAM_I2C_DAT_CONN */ PAD_CFG_NF(GPP_H06, NONE, DEEP, NF1), - /* GPP_H07: I2C3_SCL_PSS */ + /* GPP_H07: CAM_I2C_CLK_CONN */ PAD_CFG_NF(GPP_H07, NONE, DEEP, NF1), /* GPP_H08: UART0_BUF_RXD */ PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1), /* GPP_H09: UART0_BUF_TXD */ PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1), - /* GPP_H10: UART0_BUF_RTS */ + /* GPP_H10: HW_ID6 */ PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), - /* GPP_H11: UART0_BUF_CTS */ - PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), - /* GPP_H13: CPU_C10_GATE_N_R */ + /* GPP_H11: NC */ + PAD_NC(GPP_H11, NONE), + /* GPP_H13: CPU_C10_GATE_N */ PAD_CFG_NF(GPP_H13, NONE, DEEP, NF1), - /* GPP_H14: NC */ - PAD_NC(GPP_H14, NONE), - /* GPP_H15: NC */ - PAD_NC(GPP_H15, NONE), - /* GPP_H16: WWAN_PWREN */ - PAD_CFG_GPO(GPP_H16, 1, PLTRST), - /* GPP_H17: MIC MUTE LED */ + /* GPP_H14: AUTOOPEN_ALS_I2C_SDA */ + PAD_CFG_NF(GPP_H14, NONE, DEEP, NF3), + /* GPP_H15: AUTOOPEN_ALS_I2C_SCL */ + PAD_CFG_NF(GPP_H15, NONE, DEEP, NF3), + /* GPP_H16: NC */ + PAD_NC(GPP_H16, NONE), + /* GPP_H17: SOC_SCI_N */ PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), - /* GPP_H19: I3C0_SDA_HDR */ + /* GPP_H19: HW_ID3 */ PAD_CFG_NF(GPP_H19, NONE, DEEP, NF2), - /* GPP_H20: I3C0_SCL_HDR */ + /* GPP_H20: HW_ID2 */ PAD_CFG_NF(GPP_H20, NONE, DEEP, NF2), - /* GPP_H21: I2C1_SDA_I3C1_SDA_CAM_FLSH_CVS */ + /* GPP_H21: PCH_I2C_GSC_SDA */ PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1), - /* GPP_H22: I2C1_SCL_I3C1_SCL_CAM_FLSH_CVS */ + /* GPP_H22: PCH_I2C_GSC_SCL */ PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1), /* GPP_S00: SNDW3_CLK_CODEC */ @@ -352,47 +349,47 @@ PAD_CFG_NF(GPP_S04, NONE, DEEP, NF2), /* GPP_S05: SNDW2_DATA0 */ PAD_CFG_NF(GPP_S05, NONE, DEEP, NF2), - /* GPP_S06: SNDW1_CLK */ - PAD_CFG_NF(GPP_S06, NONE, DEEP, NF3), - /* GPP_S07: SNDW1_DATA0 */ - PAD_CFG_NF(GPP_S07, NONE, DEEP, NF3), + /* GPP_S06: SWIRE_AMP_CLK */ + PAD_NC(GPP_S06, NONE), + /* GPP_S07: SWIRE_AMP_DATA0 */ + PAD_NC(GPP_S07, NONE), /* GPP_V00: PM_BATLOW_N */ PAD_CFG_NF(GPP_V00, NONE, DEEP, NF1), /* GPP_V01: BC_ACOK_MCP */ PAD_CFG_NF(GPP_V01, NONE, DEEP, NF1), - /* GPP_V02: LANWAKE_N_R */ - PAD_CFG_NF(GPP_V02, NONE, DEEP, NF1), + /* GPP_V02: NC */ + PAD_NC(GPP_V02, NONE), /* GPP_V03: PWRBTN_MCP_N */ PAD_CFG_NF(GPP_V03, NONE, DEEP, NF1), /* GPP_V04: PM_SLP_S3_N */ PAD_CFG_NF(GPP_V04, NONE, DEEP, NF1), /* GPP_V05: PM_SLP_S4_N */ PAD_CFG_NF(GPP_V05, NONE, DEEP, NF1), - /* GPP_V06: PM_SLP_A_N */ - PAD_CFG_NF(GPP_V06, NONE, DEEP, NF1), + /* GPP_V06: NC */ + PAD_NC(GPP_V06, NONE), /* GPP_V07: Not used */ - PAD_NC(GPP_V07, NONE), + PAD_CFG_NF(GPP_V07, NONE, DEEP, NF1), /* GPP_V08: SLP_WLAN_N */ PAD_CFG_NF(GPP_V08, NONE, DEEP, NF1), - /* GPP_V09: PM_SLP_S5_N */ - PAD_CFG_NF(GPP_V09, NONE, DEEP, NF1), - /* GPP_V10: LANPHYPC_R_N */ - PAD_CFG_NF(GPP_V10, NONE, DEEP, NF1), - /* GPP_V11: PM_SLP_LAN_N */ - PAD_CFG_NF(GPP_V11, NONE, DEEP, NF1), - /* GPP_V12: WAKE_N */ - PAD_CFG_NF(GPP_V12, NONE, DEEP, NF1), - /* GPP_V13: GPP_V13_CATERR_N */ - PAD_CFG_NF(GPP_V13, NONE, DEEP, NF1), - /* GPP_V14: GPP_V14_FORCEPR_N */ - PAD_CFG_NF(GPP_V14, NONE, DEEP, NF1), - /* GPP_V15: GPP_V15_THERMTRIP_N */ - PAD_CFG_NF(GPP_V15, NONE, DEEP, NF1), - /* GPP_V16: GPP_V16_VCCST_EN */ + /* GPP_V09: NC */ + PAD_NC(GPP_V09, NONE), + /* GPP_V10: NC */ + PAD_NC(GPP_V10, NONE), + /* GPP_V11: NC */ + PAD_NC(GPP_V11, NONE), + /* GPP_V12: NC */ + PAD_NC(GPP_V12, NONE), + /* GPP_V13: NC */ + PAD_NC(GPP_V13, NONE), + /* GPP_V14: NC */ + PAD_NC(GPP_V14, NONE), + /* GPP_V15: NC */ + PAD_NC(GPP_V15, NONE), + /* GPP_V16: VCCST_EN */ PAD_CFG_NF(GPP_V16, NONE, DEEP, NF1), - /* GPP_V17: TCP_RT_S0IX_ENTRY_EXIT_N */ - PAD_CFG_GPO(GPP_V17, 1, DEEP), + /* GPP_V17: GPP_V17 */ + PAD_NC(GPP_V17, NONE), }; /* Early pad configuration in bootblock */ @@ -412,10 +409,10 @@ /* Pad configuration in romstage */ static const struct pad_config romstage_gpio_table[] = { - /* GPP_C00: GPP_C0_SMBCLK */ - PAD_CFG_NF(GPP_C00, NONE, DEEP, NF1), - /* GPP_C01: GPP_C1_SMBDATA */ - PAD_CFG_NF(GPP_C01, NONE, DEEP, NF1), + /* GPP_C03: GPP_C0_SMBCLK */ + PAD_CFG_NF(GPP_C03, NONE, DEEP, NF1), + /* GPP_C04: GPP_C0_SMBDATA */ + PAD_CFG_NF(GPP_C04, NONE, DEEP, NF1), }; const struct pad_config *variant_gpio_table(size_t *num) -- To view, visit https://review.coreboot.org/c/coreboot/+/85234?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4e9e81af9c3d8807e65ecd552e73305c1d109a2d Gerrit-Change-Number: 85234 Gerrit-PatchSet: 1 Gerrit-Owner: Tongtong Pan <pantongtong(a)huaqin.corp-partner.google.com>

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[XS] Change in coreboot[main]: nb/via/cx700/romstage: Include missing static.h header
by Angel Pons (Code Review) 21 Nov '24

21 Nov '24

Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85232?usp=email ) Change subject: nb/via/cx700/romstage: Include missing static.h header ...................................................................... nb/via/cx700/romstage: Include missing static.h header Commit 755ecc259c42 ("nb/via/cx700: Implement raminit") is missing an include for static.h and breaks the main branch. Fix it. Change-Id: I836ab03b4eba6f32a2ae576eafc465543179cd05 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85232 Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/via/cx700/romstage.c 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved Lean Sheng Tan: Looks good to me, approved Werner Zeh: Looks good to me, approved Subrata Banik: Looks good to me, approved diff --git a/src/northbridge/via/cx700/romstage.c b/src/northbridge/via/cx700/romstage.c index b73dd91..d554b76 100644 --- a/src/northbridge/via/cx700/romstage.c +++ b/src/northbridge/via/cx700/romstage.c @@ -8,6 +8,7 @@ #include <static_devices.h> #include <arch/romstage.h> #include <cbmem.h> +#include <static.h> #include "chip.h" #include "raminit.h" -- To view, visit https://review.coreboot.org/c/coreboot/+/85232?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I836ab03b4eba6f32a2ae576eafc465543179cd05 Gerrit-Change-Number: 85232 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: nb/via/cx700/romstage: Include missing static.h header
by Subrata Banik (Code Review) 21 Nov '24

21 Nov '24

Attention is currently required from: Felix Singer. Subrata Banik has posted comments on this change by Felix Singer. ( https://review.coreboot.org/c/coreboot/+/85232?usp=email ) Change subject: nb/via/cx700/romstage: Include missing static.h header ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85232?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I836ab03b4eba6f32a2ae576eafc465543179cd05 Gerrit-Change-Number: 85232 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Comment-Date: Thu, 21 Nov 2024 12:05:07 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: nb/via/cx700/romstage: Include missing static.h header
by Felix Singer (Code Review) 21 Nov '24

21 Nov '24

Felix Singer has posted comments on this change by Felix Singer. ( https://review.coreboot.org/c/coreboot/+/85232?usp=email ) Change subject: nb/via/cx700/romstage: Include missing static.h header ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > Ah, right, Jenkins still needs to happen. Yeah, I think so. I build-tested locally. Should fix it. -- To view, visit https://review.coreboot.org/c/coreboot/+/85232?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I836ab03b4eba6f32a2ae576eafc465543179cd05 Gerrit-Change-Number: 85232 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Thu, 21 Nov 2024 11:50:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com>

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[XS] Change in coreboot[main]: nb/via/cx700/romstage: Include missing static.h header
by Angel Pons (Code Review) 21 Nov '24

21 Nov '24

Attention is currently required from: Felix Singer. Angel Pons has posted comments on this change by Felix Singer. ( https://review.coreboot.org/c/coreboot/+/85232?usp=email ) Change subject: nb/via/cx700/romstage: Include missing static.h header ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > I assume this broke the tree, submitting. Ah, right, Jenkins still needs to happen. -- To view, visit https://review.coreboot.org/c/coreboot/+/85232?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I836ab03b4eba6f32a2ae576eafc465543179cd05 Gerrit-Change-Number: 85232 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Comment-Date: Thu, 21 Nov 2024 11:48:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com>

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[XS] Change in coreboot[main]: nb/via/cx700/romstage: Include missing static.h header
by Angel Pons (Code Review) 21 Nov '24

21 Nov '24

Attention is currently required from: Felix Singer. Angel Pons has posted comments on this change by Felix Singer. ( https://review.coreboot.org/c/coreboot/+/85232?usp=email ) Change subject: nb/via/cx700/romstage: Include missing static.h header ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: I assume this broke the tree, submitting. -- To view, visit https://review.coreboot.org/c/coreboot/+/85232?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I836ab03b4eba6f32a2ae576eafc465543179cd05 Gerrit-Change-Number: 85232 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Comment-Date: Thu, 21 Nov 2024 11:47:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: nb/via/cx700/romstage: Include missing static.h header
by Angel Pons (Code Review) 21 Nov '24

21 Nov '24

Attention is currently required from: Felix Singer. Angel Pons has posted comments on this change by Felix Singer. ( https://review.coreboot.org/c/coreboot/+/85232?usp=email ) Change subject: nb/via/cx700/romstage: Include missing static.h header ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85232?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I836ab03b4eba6f32a2ae576eafc465543179cd05 Gerrit-Change-Number: 85232 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Comment-Date: Thu, 21 Nov 2024 11:47:24 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: soc/mediatek/mt8196: Add MMinfra driver support
by Jarried Lin (Code Review) 21 Nov '24

21 Nov '24

Attention is currently required from: Hung-Te Lin, Paul Menzel, Yidi Lin, Yu-Ping Wu. Jarried Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85188?usp=email ) Change subject: soc/mediatek/mt8196: Add MMinfra driver support ...................................................................... Patch Set 5: (2 comments) Patchset: PS4: > The callbacks are registered to MTCMOS module, and during the MTCMOS power-on process, those callba […] Done File src/soc/mediatek/mt8196/mminfra_pd.c: https://review.coreboot.org/c/coreboot/+/85188/comment/f8235d7d_d84fcf87?us… : PS5, Line 35: while (read32p(MMINFRA_MM0_GALS_PROT_TX_RDY) != 0xff) : ; > Since this is a very basic MM register setting, if the while loop gets stuck, it indicates some hard […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/85188?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie86f141a0957fc60d4973875c0dbcbdb57be1f75 Gerrit-Change-Number: 85188 Gerrit-PatchSet: 5 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Thu, 21 Nov 2024 11:35:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Jarried Lin <jarried.lin(a)mediatek.com> Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com>

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coreboot-gerrit November 2024